KR20000066848A - Memory Cell Layout Structure - Google Patents

Abstract

PURPOSE: A layout structure of a memory cell is provided to improve the chip integration and a wiring process by using a cross active layout structure. CONSTITUTION: A layout structure of a memory cell comprises a semiconductor substrate, an active area, a plurality of first word line(121-128), a plurality of second word line(221-224); and a couple of bit line(11a,11b). The active area is formed with a plurality of cross line. The first word line runs to a longitudinal direction of the active area. The second word line runs to another longitudinal direction of the active area. The second word line is perpendicular to the first word line. The bit line couple is formed on the active area. The bit line couple is perpendicular to the first word line direction.

Description

Memory Cell Layout Structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell layout structure of a semiconductor memory device, and more particularly, to a memory cell layout structure having a cross type active layout structure.

1 is a schematic diagram showing a circuit diagram of a memory cell of the prior art.

Referring to FIG. 1, bit line pairs 1a and 1b are arranged perpendicular to word lines 20 to 25, and memory cell MC1 is connected at an intersection point between bit line 1a and word line 20. Memory Cell) MC2 is connected at the intersection between bit line 1b and word line 21, Memory Cell MC3 is connected at the intersection between bit line 1a and word line 23, and Memory Cell MC 4 is connected at It is connected at the intersection between bit line 1b and word line 25.

Each of the memory cells MC1 to MC4 is composed of one MOS transistor and one capacitor. Bit line pairs 1a and 1b are connected to bit line equalizing, pre-charging circuits, sense amplifiers, and transfer gates (not shown). .

FIG. 2 is a prior art DRAM memory cell layout shown in FIG. 1.

Referring to FIG. 2, word lines 21, 22,... Are arranged orthogonal to folded bit line pairs 1a, 1b, memory cells MC1 and MC 3 are arranged along bit line 1a, Memory cells MC2 and MC4 are arranged along bit line 1b. The MOS transistor of memory cell MC3 is connected to bit line 1a at bit line contact 7. Capacitors 8a and 8b are formed on the top layer of memory cell MC3 via storage contacts. In the memory cell layout described above, for example, one bit line 1a and two word lines 23 and 24 are arranged on one active 33.

In the above-described prior art, there are many limitations in the high speed semiconductor device and the ultra-integrated circuit by operating two word lines in one bit line, and there are problems such as problems in the wiring forming process of the manufacturing process. .

Accordingly, an object of the present invention is to provide a memory cell layout structure capable of improving the integration degree, facilitating the wiring process, and driving four word lines with one bit line.

Another object of the present invention is to provide a memory device capable of improving the integration degree, facilitating a wiring process, and driving four word lines with one bit line.

A memory cell layout structure according to the present invention for achieving the above object is a semiconductor substrate, a plurality of cross-shaped active region, a plurality of first word lines running perpendicular to the longitudinal direction of the active region, and A plurality of second word lines running perpendicular to the other length direction and perpendicular to the first word line, and formed in the active region connected to the first word line and the second word line and directed in the direction of the first word line It has a pair of bit lines running perpendicular to it.

In accordance with another aspect of the present invention, a memory device includes a pair of first word lines running in one direction, a pair of second word lines running in a vertical direction in the one direction, and a second word line. One bit line running in a parallel direction, and four memory cells formed at the intersection of the bit line, the first word line and the second word line.

1 is a schematic diagram showing a circuit diagram of a memory cell of the prior art.

FIG. 2 is a prior art DRAM memory cell layout shown in FIG. 1.

3 is a schematic diagram showing a circuit diagram of a memory cell according to the present invention.

FIG. 4 is a DRAM memory cell layout of the present invention as shown in FIG.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic diagram showing a circuit diagram of a memory cell according to the present invention.

Referring to FIG. 3, the bit line pairs 11a and 11b are arranged perpendicular to the plurality of first word lines 120 to 125, and the memory cell MC1 is the bit line 11a and the first word line 120. The memory cell MC2 is connected at the intersection between the bit line 11b and the first word line 121, and the memory cell MC3 is connected to the bit line 11a and the first word line. The memory cell MC 4 is connected at the intersection between the bit line 11b and the first word line 125. Each of the memory cells MC1 to MC4 includes one MOS transistor and one capacitor.

The bit line pairs 11a and 11b are arranged in parallel to the plurality of second word lines 221 to 224, and the memory cell MC7 is connected at the intersection point between the bit lines 11a and the second word line 221. The memory cell MC5 is connected at the intersection between the bit line 11b and the second word line 222, and the memory cell MC 8 is connected at the intersection between the bit line 11b and the second word line 223. The memory cell MC 6 is connected at the intersection between the bit line 11b and the second word line 224. Each of the memory cells MC5 to MC 8 includes one MOS transistor and one capacitor. Four memory cells MC are arranged around bit line contacts commonly used as a source or a drain. The four memory cells MC are composed of one bit line, two first word lines arranged perpendicular to the bit lines, and two second word lines arranged parallel to the bit lines.

FIG. 4 is a DRAM memory cell layout of the present invention as shown in FIG.

Referring to FIG. 4, a plurality of first word lines 121, 122, 123,... Are arranged orthogonal to bit line pairs 11a and 11b, and memory cells MC1 and MC 3 are arranged along bit line 11a. Memory cells MC2 and MC4 are arranged along bit line 11b. The MOS transistor of memory cell MC3 is connected to bit line 11a at bit line contact 107. Capacitors 108a and 108b are formed in the upper layer of the memory cell MC3 through storage contacts.

Meanwhile, the plurality of second word lines 221, 222,... Are arranged in parallel to the bit line pairs 11a and 11b, and the memory cells MC 7 and MC 5 are arranged along the bit line 11a. MC 6 is arranged along bit line 11b. For example, the MOS transistor of the memory cell MC 7 is connected to the bit line 11a at the bit line contact 107 and the capacitor 109a is formed on the top layer of the memory cell MC 7 through the storage contact. The MOS transistor of the memory cell MC 8 is connected to the bit line 11b at the bit line contact 107 and the capacitor 110a is formed on the top layer of the memory cell MC 8 through the storage contact. First word lines 121 and 122 running in the cross-type active region in a direction orthogonal to the bit lines, and second word lines 221 and 222 intersecting with the first word lines. Four memory cells MC are arranged in one cross-type active region.

The manufacturing process of the DRAM having the layout will be described. A first word defining an active region and a device isolation region in a semiconductor substrate, forming a gate oxide film in the active region, and running in one direction Patterning a line, depositing an insulating layer to insulate the first word line, exposing an active region in which the first word line is not disposed by a photo / etching operation, and then applying a gate oxide film to the exposed active region Forming and patterning a second word line running in one orthogonal direction, depositing an insulating layer to insulate the second word line, and forming a semiconductor by photo / etching in the center of the cross-shaped active region in the memory cell region. A bit line contact is formed that exposes the substrate and the bit line that electrically connects the contact is patterned. An insulating layer for insulating the bit line is deposited, a storage contact is formed by photo / etching in the cross-shaped active region, and a capacitor is formed on the top layer of the memory cell MC in a conventional well known manner. Never)

As described above, the memory cell layout structure of the semiconductor memory device according to the present invention includes a semiconductor substrate, a plurality of cross-shaped active regions, a plurality of first word lines running perpendicular to a longitudinal direction of the active region, and the active A plurality of second word lines which are orthogonal to another longitudinal direction of the region and are perpendicular to the first word line, and are formed in the active region connected to the first word line and the second word line; It has a pair of bit lines running perpendicular to the direction of.

Therefore, the present invention has an advantage of improving the degree of integration by forming four word lines in one bit line as a cross-type active region.

Claims (4)

A semiconductor substrate, A plurality of cross-shaped active regions, A plurality of first word lines running perpendicular to a longitudinal direction of the active region; A plurality of second word lines running orthogonal to another longitudinal direction of said active region and perpendicular to said first word line; And a pair of bit lines formed in the active region connected to the first word line and the second word line and running perpendicular to the direction of the first word line. The memory cell layout structure of claim 1, wherein the first word line and the second word line are insulated from each other by an interlayer insulating layer. A pair of first word lines running in one direction, A pair of second word lines running in the vertical direction of the one direction; One bit line running in a direction parallel to the second word line; And four memory cells formed at the intersections of the bit line with the first word line and the second word line. The memory device of claim 3, wherein the memory cell comprises one transistor and one capacitor.