JPH03248559A - Mask rom - Google Patents

Abstract

PURPOSE:To realize high-density integration and high-speed operation of a memory by providing word lines for giving electrical isolation between memory cells in addition to word lines for cell selection. CONSTITUTION:First-level word lines 25 are provided to isolate memory cells 13 electrically from each other, and individual memory cells are selected by second-level word lines 27 and bit lines 35. This design does not use a LOCOS structure. A contact hole 34 is formed in each region surrounded by both word lines 25 and 27, and the bit lines 35 are connected with the source and drain regions 31 of all the memory cells 13. In spite of all the cells being connected with the source and drain regions, high-density integration is possible because of the elimination of a LOCOS structure. In addition, the channel can be made wider, and thus high-speed operation is possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mask ROM used as a data memory of a kanji generator or a speech synthesizer.

[Summary of the invention]

In the mask ROM as described above, the present invention provides word lines for electrically isolating memory cells from each other in addition to word lines for selecting memory cells.
This makes it possible to achieve high integration and high-speed operation.

[Conventional technology]

In a mask ROM, information has conventionally been written depending on the presence or absence of a contact hole for a bit line.

However, this requires one contact hole for each memory cell, making it difficult to achieve high integration.

Therefore, methods have been developed to increase the degree of integration by writing information by adjusting the dark value voltage and reducing the number of contact holes.

For example, rNational Technical R
eport 4 Vol.

32 No. 1 (Feb, 1986) p. 17~
22 shows a first conventional example in which the number of contact holes is reduced by connecting a plurality of transistors in series.

Also, “Nikkei Electronics J (1980, 7,
21) On pages 189 to 201, there is a second page as shown in Figure 4.
A conventional example is shown. In this second conventional example, one memory cell 1 is formed by two bit lines (not shown) and a word line 12 which are connected to a contact hole 11 and are adjacent to each other.
3 and check the continuity between adjacent bit lines.

In this second conventional example, as is clear from FIG. 4, there are two contact holes 11 per memory cell 13.

[Problems to be Solved by the Invention] However, the first conventional example described above has a high resistance when the transistor is turned on, and is not suitable for high-speed operation.

Furthermore, in the second conventional example described above, as is clear from FIG. 4, the main 14 memory cells 13 are electrically isolated from each other by the LOGO3 film 14. Therefore, high integration is difficult, and the channel width of the transistor is narrow, so it is not suitable for high-speed operation.

(Means for Solving the Problems) A mask ROM according to the present invention includes a plurality of first layer word lines 25 extending parallel to each other, and a plurality of word lines 25 extending parallel to each other and parallel to each other so as to intersect with the first layer word lines 25. A contact hole 34 is formed in a region surrounded by a plurality of second-layer word lines 27 extending in the second layer, the first-layer word line 25, and the second-layer word line 27. and a bit line 35 passing over the intersection of the first layer word line 25 and the second layer word line 27 and extending so as to connect the contact holes 34. ing.

[Effect]

In the mask ROM according to the present invention, the selection of the memory cells 13 is performed by the bit line 35 and the second layer word line 27, and the first layer word line 25 is used to electrically isolate the memory cells 13 from each other. use Therefore, the LOGO3 structure is not adopted.

In addition, the first layer word line 25 and the second layer word line 2
Since the contact hole 34 is formed in the region surrounded by 7, the bit line 35 is connected to the source/drain regions 31 of all the memory cells 13.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 3.

In order to manufacture this embodiment, as shown in FIGS. 2A and 3A, the surface of the Si substrate 21 is oxidized to form the gate insulating film 22.
First form.

Thereafter, the resist 23 is patterned so as to expose only the channel region of the transistor that does not turn on even if selected among the transistors of each memory cell 13. Then, impurity 24 for adjusting the dark value voltage is ion-implanted into the Sl substrate 11 using the resist 23 as a mask.

Next, as shown in FIGS. 2B and 3B, the resist 23
is removed, and a first layer word line 25 made of a polycrystalline Si film or the like is patterned. Then, the gate insulating film 26 is formed by oxidizing the surface of the word line 250 and the like.

Next, as shown in FIGS. 2C and 3C, a second layer of word lines 27 made of a polycrystalline Si film or the like is patterned.

Then, using the word lines 25 and 27 as a mask, the source
By implanting impurity ions into the Si substrate 11 to form the drain region and annealing, the source region is formed.
A drain region 31 and a threshold voltage adjustment region 32 are formed.

Next, as shown in FIGS. 2D and 3D, a reflow film 33 is formed as an insulating film between the eyebrows, and the source/drain region 33 is
A contact hole 34 reaching 1 is formed in the reflow film 33 or the like.

Then, the reflow film 33 is reflowed, the bit line 35 made of Af is patterned, and an overcoat film (not shown) is further formed to complete the present embodiment.

In this embodiment manufactured as described above, the memory cells 13 are selected by the bit line 35 and the word line 27 in the second layer, and the word line 25 in the first layer electrically connects the memory cells 13 to each other. Used for separation.

That is, the word lines 25 on at least both sides of the selected memory cell 13 are set to a low potential to prevent a channel from being formed under the word lines 25.

Therefore, as is clear from FIGS. 2 and 3, the LOGO3 structure is not adopted in this embodiment.

However, it is naturally possible to form this embodiment and a circuit requiring the LOGO3 structure on the same Si substrate 21.

As is clear from FIGS. 1 and 3, the bit lines 35 are connected to the source/drain regions 31 of all memory cells 13.
However, the number of contact holes 34 per one memory cell 13 is two.

〔Effect of the invention〕

Since the mask ROM according to the present invention does not employ the LOGO3 structure, high integration is possible even if bit lines are connected to the source/drain regions of all memory cells.

Furthermore, since the LOGO3 structure is not adopted, the channel width can be widened, and since bit lines are connected to the source/drain N regions of all memory cells, high-speed operation is possible.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, and FIGS. 2 and 3 sequentially show the manufacturing process of the embodiment, along the lines ■-■ and ■-■ in FIG. 1, respectively. FIG. FIG. 4 is a plan view of a second conventional example of the present invention. In addition, in the symbols used in the drawings, 13-・----11---------・--Memory cell 2
5------------・・・・--------1 Word line in the first layer Word line in the second layer Source/drain region contact hole Bit line embedding Tsuchiya

Claims (1)

[Claims] A plurality of first layer word lines extending parallel to each other, and a plurality of second layer words extending parallel to each other so as to intersect these first layer word lines. a contact hole formed in a region surrounded by the first layer word line and the second layer word line; and a contact hole formed in a region surrounded by the first layer word line and the second layer word line; and a bit line extending so as to pass over the intersection with the word line and connect the contact holes.