KR100228351B1 - Manufacture of semiconductor device - Google Patents

Abstract

1. Fields to which the invention described in the claims belong

Semiconductor memory device manufacturing.

2. The technical problem to be solved by the invention

This is to solve the problem of not being able to secure sufficient cell ratio because the length of the driving transistor is limited by forming a word line with a conductive layer used as a gate of the driving transistor.

3. Summary of Solution to Invention

By forming a word line with a conductive layer different from the conductive layer for forming the driving transistor gate, the word line and the driving transistor are overlapped to secure sufficient cell ratio and stable cell characteristics.

4. Important uses of the invention

Used in the manufacture of semiconductor memory devices.

Description

Semiconductor memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure of a static random access memory (SRAM) cell and a method of manufacturing the same, which are capable of securing a process margin and increasing a cell ratio without increasing a cell area. It is about.

As shown in FIG. 1, a conventional SRAM cell has a structure in which a first polysilicon layer used as a gate of an access transistor is used as a word line 18. As shown in FIG. In this cell structure, the driving transistor 13 is usually formed vertically between the word line 18 and the word line 18, which limits the length of the driving transistor, thereby limiting the cell ratio. The layout problem as described above is that it is impossible to implement an SRAM cell having a stable characteristic, and this problem is particularly serious in an SRAM having a small cell area.

As a result, in order to secure the maximum cell ratio in the conventional SRAM cell area, it is necessary to adopt a layout that forms the length of the driving transistor as long as possible. Such layout reduces the end capacitance of the driving transistor, decreases node contact resistance, and the like. It is a factor that makes other aspects vulnerable, causing problems such as short-circuit between the end capacitor and the word line.

An object of the present invention is to provide an SRAM cell structure and a method of manufacturing the same, in which a word line is formed to overlap a driving transistor in an SRAM cell, thereby increasing the cell ratio by increasing the length of the driving transistor.

A semiconductor memory device of the present invention for achieving the above object comprises a drive transistor having a gate consisting of a first conductive layer; A second word line including a second conductive layer formed to overlap the driving transistor in a predetermined area above the driving transistor, and a first word line including a first conductive layer connected to the first word line through a contact; It comprises a word line.

In accordance with another aspect of the present invention, a method of manufacturing a semiconductor memory device includes forming a first conductive layer on a semiconductor substrate, and patterning the first conductive layer to form a gate of a first word line and a driving transistor. Forming an interlayer insulating film over the entire surface of the substrate, selectively etching the interlayer insulating film to form a contact hole exposing a predetermined portion of the first word line, forming a second conductive layer over the entire surface of the substrate, and Patterning the second conductive layer to form a second word line connected to the first word line through the contact hole.

1 is a conventional SRAM cell layout.

2 is a SRAM cell layout according to the present invention.

3 (a) to 3 (e) are process flowcharts showing the SRAM cell manufacturing method according to the present invention.

* Explanation of symbols for main parts of the drawings

1 gate oxide film 2 silicon substrate

3: field oxide film 3a: driving transistor gate

3b: wordline 4: spacer

5: interlayer insulating film 6: photoresist pattern

7: contact hole 8: polyside layer

8a: wordline

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 shows an SRAM cell layout according to the present invention.

In the SRAM cell according to the present invention, a word line 3b made of a polysilicon layer as a first conductive layer and a word line 8a made of a polyside layer as a second conductive layer are connected to each other through a contact 7. The word line of the SRAM cell constitutes a word line, and the portion of the word line 8a made of the polyside layer as the second conductive layer is formed so as to overlap the upper portion of the edge portion of the driving transistor 3a.

That is, since the word line and the driving transistor are formed on the same plane and cannot overlap each other by forming the word lines together as the first conductive layer forming the driving transistor gate, in the case of the present invention, as described above, the driving transistor The word line of the edge portion may be formed to overlap the upper portion of the driving transistor by forming the second conductive layer instead of the first conductive layer forming the driving transistor.

Accordingly, the shorting problem between the driving transistor edge portion and the word line can be solved, and the length of the driving transistor can be increased, thereby increasing the cell ratio. In addition, since the driving transistor can be formed by moving in parallel in the direction in which the end capacitor is formed, it is possible to secure a sufficient node contact to lower the node contact resistance. In addition, since the margin between the third conductive layer and the access transistor gate formed in the nose contact and the driving transistor end capacitor margin can be increased, stable cell characteristics can be secured.

Referring to FIGS. 3 (a) to 3 (e), the SRAM cell manufacturing method according to the present invention will be described as follows. 3 (a) to 3 (e) show the cross-sectional structure along the line AA ′ of FIG. 2.

First, as shown in FIG. 3 (a), a gate oxide film 1 is formed on a semiconductor substrate 100 divided into an active region and an element isolation region by a field oxide film 3, and as a first conductive layer on the front surface of the substrate, The polysilicon layer 3 is formed.

Subsequently, as shown in FIG. 3 (b), the polysilicon layers 3a and 3b are patterned to form gates and word lines 3b of the access transistors and gates 3a of the driving transistors. ), And ion implantation is performed to form the source and drain regions.

Next, as shown in FIG. 3C, an oxide film is formed on the entire surface of the substrate, for example, and then a predetermined photoresist pattern 6 for forming the contact region 7 is formed on the oxide film.

Next, as shown in FIG. 3 (d), the oxide layer 5 is etched using the photoresist pattern 6 as a mask to form a contact hole 7 exposing the word line 3b, and then over the entire surface thereof. As the second conductive layer 8, for example, a polyside layer made of polysilicon and tungsten silicide is formed.

Subsequently, as shown in FIG. 3 (e), the polyside layer 8 is patterned, so that the word line 8a of the driving transistor edge portion connected to the word line 3b of the access transistor region through the contact hole 7 is formed. Form.

As described above, the word line 8a formed at the edge of the driving transistor is formed of a polyside layer, which is a second conductive layer instead of the first conductive layer constituting the driving transistor, so that the word line is formed to overlap the upper portion of the driving transistor. It becomes possible. As a result, the length of the driving transistor can be sufficiently increased to secure a desired cell ratio.

In addition, a contact hole 7 connecting the word line 3b made of polysilicon, which is the first conductive layer, and the word line 8a made of polyside, which is the second conductive layer, are connected to each other. It is formed in the cell by using a mask for forming a bit line contact and a Vss contact, so that a separate mask process is not required. Therefore, the number of processes is not increased and the process is not complicated.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention, the length of the driving transistor in the SRAM cell can be lengthened sufficiently without changing the cell area to secure a desired cell ratio, and the driving transistor can be formed by moving in parallel in the direction in which the end capacitor is formed. By securing sufficient node contact, the node contact resistance can be lowered. In addition, since the margin between the third conductive layer and the access transistor gate formed in the node contact and the driving transistor end capacitor margin can be increased, stable cell characteristics can be secured.

Claims (10)

A drive transistor having a gate formed of a first conductive layer; A second word line including a second conductive layer formed to overlap the driving transistor in a predetermined area above the driving transistor, and a first word line including a first conductive layer connected to the second word line through a contact; And a word line. The semiconductor memory device of claim 1, wherein the driving transistor and the word line are disposed to be perpendicular to each other. The semiconductor memory device of claim 1, wherein the first conductive layer is a polysilicon layer. The semiconductor memory device of claim 1, wherein the second conductive layer is a polyside layer. The semiconductor memory device of claim 1, wherein the second word line overlaps an edge portion of the driving transistor. Forming a first conductive layer on a semiconductor substrate, patterning the first conductive layer to form a gate of a first word line and a driving transistor, forming an interlayer insulating film over the entire substrate, and forming the interlayer insulating film Selectively etching to form a contact hole exposing a predetermined portion of the first word line, forming a second conductive layer on the entire surface of the substrate, and patterning the second conductive layer to form a first hole through the contact hole And forming a second word line connected to the word line. The method of claim 6, wherein the second word line overlaps the gate of the driving transistor at a predetermined portion. The method of claim 7, wherein the second word line is overlapped at an edge of the driving transistor gate. The method of claim 6, wherein the first conductive layer is formed of polysilicon. The method of claim 6, wherein the second conductive layer is formed of polyside.