KR20020034314A - Method of manufacturing sram cell - Google Patents

Abstract

PURPOSE: A method for fabricating a static random access memory(SRAM) cell is provided to prevent cell data from being broken by charges injected from the outside even if the size of a cell is decreased, by connecting a dummy plate with a cell node storing data, Vss and Vcc so that cell capacitance is increased. CONSTITUTION: An SRAM has a transfer transistor, a drive transistor and a load transistor. Data is stored in the cell node to which a common drain terminal of the drive transistor and the load transistor and a source terminal of the transfer transistor are connected. An interlayer dielectric is formed on the cell node. The interlayer dielectric is selectively patterned to form a contact hole exposing a predetermined portion of the cell node. The dummy plate(42) is connected to the cell node through the contact hole, overlapping the drive transistor and the load transistor.

Description

Manufacturing method of SRAM cell {METHOD OF MANUFACTURING SRAM CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a memory device, wherein an electron hole pair (EHP) generated by alpha particles reduces an error in a cell node. The present invention relates to a method for manufacturing an SRAM cell.

In general, a unit cell of a static random access memory (SRAM) is composed of six transistors 6T, which is composed of a drive transistor, an access transistor, and a load element. do.

Here, the driving transistor and the exciter transistor use an NMOS, and the load device uses a resistor, a PMOS, a full CMOS, a polysilicon load, or a thin film transistor (TFT).

FIG. 1 is an equivalent circuit diagram of an FCMOS type SRAM cell according to the prior art, in which a word line WL is connected to each gate, and an excitation transistor Q1 having a positive bit line BL and a sub bit line / BL connected to a drain thereof. , Q3), a load cell (Q5, Q6) to which a source voltage (V _CC ) is applied to a source terminal, a drain cell having a drain terminal of the load transistors (Q5 and Q6) and a source terminal of the access transistors (Q1 and Q3) commonly connected to each other. A node (N) and a subcell node (/ N) and the load transistors Q5 and Q6 are connected in series and have a CMOS structure in which a gate is connected in common, and the gate is the positive cell node and the subcell node (/ N). It consists of drive transistors Q2 and Q4 cross-coupled to each other. Here, the driving transistors Q2 and Q4 and the access transistors Q1 and Q3 are NMOS, the ground voltage V _SS is applied to the source of the driving transistors Q2 and Q4, and the load transistor uses PMOS. .

In the FCMOS type SRAM cell configured as described above, an electron-hole pair (EHP) generated by alpha particles (α-Particle) breaks the charges stored in the cell, so as to improve the SER (Soft Error Rate) fail. Cell capacitance (C _cell ) must be maintained above a certain level.

However, since the design rule is scaled down and the cell size can be secured only when the cell size is reduced, the cell capacitance (C _cell ) is reduced to cause an SER fail.

2A to 2E are layout diagrams showing a method of manufacturing an FCMOS type SRAM cell according to the prior art.

As shown in FIG. 2A, the field region 12 is formed in the semiconductor substrate 11 using a device isolation mask to define the active layer 13.

As shown in FIG. 2B, after polysilicon is formed on the entire surface including the active layer 13, the polysilicon is selectively patterned to form four gate lines 14a, 14b, 15a, and 15b. Here, the gate lines 14a and 14b arranged at the center of the cell region among the four gate lines 14a, 14b, 15a, and 15b are gates of the load transistor and the driving transistor, and the load transistors and the driving transistors are CMOS type. It has the same gate line. In this case, the gate lines 14a, 14b, 15a, and 15b may be formed in a stacked layer structure such as a gate oxide layer, polysilicon, tungsten, or a hard mask, and spacers (not shown) may be formed on sidewalls of the gate lines.

Subsequently, P-type source / drain (not shown) and N-type source / drain (not shown) are applied to the active layer using P-type and N-type impurity ion implantation, respectively, using the gate lines 14a, 14b, 15a, and 15b as masks. ).

As shown in FIG. 2C, after forming an interlayer insulating film (not shown) on the entire surface including the gate lines 14a, 14b, 15a, and 15b, the interlayer insulating film is selectively patterned to form cell node contact holes and bit lines. Forming a pad contact hole, forming a conductive film in the cell node contact hole and the bit line contact hole, and then selectively patterning the cell node contacts 16a, 16b, 17a, 17b, 18a, and 18b and the bit line pad contact 19a. , 19b). In this case, the cell node contacts 16a, 16b, 17a, 17b, 18a, and 18b include positive cell node contacts 16a, 17a, and 18b and bushel node contacts 16b, 17b, and 18a, and the bit line pads. The contacts 19a and 19b include a positive bit line pad contact 19a and a sub bit line pad contact 19b.

In detail, the cell node contacts 16a, 16b, 17a, 17b, 18a, and 18b may be a region in which a source of a first exciter transistor and a drain of a first driving transistor are commonly connected, a drain of a first load transistor, and the first node. A region including positive cell node contacts 16a, 17a, and 18b formed on a common gate line of the second driving transistor and the second load transistor, respectively, in which the source of the second existor transistor and the drain of the second driving transistor are commonly connected; And a subcell node contact 16b, 17b, and 18b formed on a common gate line of the drain of the load transistor and the first driving transistor and the first load transistor, respectively.

In addition, positive bit line pad contacts / sub bit line pad contacts 19a and 19b are formed in the drains of the first and second exciter transistors to connect subsequent bit lines.

As shown in FIG. 2D, an interlayer insulating film (not shown) is formed on the entire surface including the cell node contacts 16a, 16b, 17a, 17b, 18a, and 18b and the bit line pad contacts 19a and 19b. The interlayer insulating film is selectively patterned to form contact holes for local wiring. Subsequently, a conductive film is formed on the entire surface including the local wiring contact hole, and then selectively patterned to form a first local wiring 20a for commonly connecting the positive cell node contacts 16a, 17a, and 18b. Here, the first local wiring 20a is used as the positive cell node N.

A second local wiring 20b is formed to connect the subcell node contacts 16b, 17b, and 18a in common.

Data is stored in the positive cell and the subcell node as described above.

In addition, a bit line pad 21a and a sub bit line pad 21b are formed to be connected to the bit line pad contact 19a and the sub bit line pad contact 19b.

As shown in FIG. 2E, the V _CC contact 22a and the V _CC line 22b are formed to connect the source of the first and second load transistors to a common connected area, and the source of the first and second driving transistors. Form a V _SS contact 23a and a V _SS line 23b connected to a common connected area.

As shown in FIGS. 2A to 2E, the capacitance C _cell of the cell node N includes the capacitance C _Njunc and the first region of the region where the drain of the first driving transistor and the source of the first access transistor are commonly connected. It consists of the sum of the capacitance of the drain of the load transistor (C _Pjunc ), the capacitance of the first driving transistor (C _NMOS ) and the capacitance of the first load transistor (C _PMOS ). C _cell ) is reduced by about 30%, resulting in soft errors. In other words, as the cell size decreases, the overall capacitance area decreases, so that the capacitance value decreases in proportion to this. Therefore, if the capacitance value decreases, it becomes vulnerable to SER.

In particular, since the FCMOS requires low voltage operation, the error rate may be worse and there is a problem in that the cell capacitance (C _cell ) should be maintained at about 67 fF or more.

On the other hand, there is a method of increasing the junction area or increasing the gate capacitance in order to increase the capacitance of the cell, but this has a problem of increasing the cell size again.

The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method for manufacturing an SRAM cell suitable for preventing a soft error caused by a decrease in cell size and cell capacitance.

1 is an equivalent circuit diagram of a typical FCMOS type SRAM cell;

2A to 2E are layout views of an FCMOS type SRAM cell according to the prior art;

3A to 3E are layout views showing a method of manufacturing an FCMOS type SRAM cell according to the first embodiment of the present invention;

4 is a cross-sectional view taken along the line AA ′ of FIG. 3E;

5 is a layout diagram of an FCMOS type SRAM cell according to a second embodiment of the present invention;

6 is a layout diagram of an FCMOS type SRAM cell according to a third embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: field area

33: active layer 34a, 34b, 35a, 35b: gate line

36a, 37a, 38b: positive cell node contact 36b, 37b, 38a: busel node contact

39a, 39b: bit line pad contacts 40a, 40b: first and second local wiring

41a, 41b: bit line pad 42: dummy plate

43a: V _CC contact 44a: V _SS contact

A method of manufacturing an SRAM cell of the present invention for achieving the above object includes a transfer transistor, a driving transistor, and a load transistor, wherein a common connected drain terminal of the driving transistor and the load transistor and a source terminal of the transfer transistor are commonly joined. An SRAM manufacturing method for storing data in a cell node, the method comprising: forming a dummy plate connected to the cell node to increase capacitance of the cell node, wherein the SRAM cell of the present invention is provided. The manufacturing method of the SRAM cell of the present invention comprises the step of forming a dummy plate connected to the source terminal of the load transistor in order to increase the capacitance of the cell node. Source stage of the drive transistor to increase capacitance Characterized in that it comprises a step of forming a dummy plate connected to.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3E illustrate a method of manufacturing an FCMOS SRAM cell for increasing capacitance of an FCMOS SRAM cell according to a first embodiment of the present invention.

As shown in FIG. 3A, a field region 32 is formed in the semiconductor substrate 31 using a device isolation mask to define an active layer 33.

As shown in FIG. 3B, after polysilicon is formed on the entire surface including the active layer 33, the polysilicon is selectively patterned to form four gate lines 34a, 34b, 35a, and 35b. Here, the gate lines 34a and 34b arranged in the center of the cell region among the four gate lines 34a, 34b, 35a, and 35b are gates of the load transistor and the driving transistor, and the load transistor and the driving transistor are CMOS type. It has the same gate line. In this case, the gate lines 34a, 34b, 35a, and 35b may be formed in a stacked layer structure such as a gate oxide film, polysilicon, tungsten, or a hard mask, and spacers (not shown) may be formed on sidewalls of the gate lines.

Subsequently, a P-type source / drain stage (not shown) and an N-type source / drain stage (not shown) are applied to the active layer using P-type and N-type impurity ion implantation using the gate lines 34a, 34b, 35a, and 35b as masks, respectively. (Not shown). That is, the drain terminal of the first and second driving transistors and the source terminal of the first and second exciter transistors are formed in common, and the source terminals of the first and second load transistors to which the power voltage V _CC is applied are formed in common. Source terminals of the first and second driving transistors to which the ground voltage V _SS is applied are commonly formed.

As shown in FIG. 3C, after forming an interlayer insulating film (not shown) on the entire surface including the gate lines 34a, 34b, 35a, and 35b, the interlayer insulating film is selectively patterned to form cell node contact holes and bit lines. Forming a pad contact hole, forming a conductive film in the cell node contact hole and the bit line contact hole, and then selectively patterning the cell node contacts 36a, 36b, 37a, 37b, 38a, and 38b and the bit line pad contact 39a. , 39b). In this case, the cell node contacts 36a, 36b, 37a, 37b, 38a, and 38b include positive cell node contacts 36a, 37a and 38b and busel node contacts 36b, 37b and 38a, and the bit line pads. The contacts 39a and 39b include a positive bit line pad contact 39a and a sub bit line pad contact 39b.

In detail, the cell node contacts 36a, 36b, 37a, 37b, 38a, and 38b may have a region in which a source of a first exemplifier transistor and a drain of a first driving transistor are commonly connected, a drain of a first load transistor, and the first node. A region including positive cell node contacts 36a, 37a, and 38b formed on a common gate line of the second driving transistor and the second load transistor, respectively, wherein the source of the second existor transistor and the drain of the second driving transistor are commonly connected; And a subcell node contact (36b, 37b, 38b) formed at each of the drain of the load transistor and the common gate line of the first driving transistor and the first load transistor.

In addition, positive bit line pad contacts / sub bit line pad contacts 39a and 39b are formed at the drains of the first and second exciter transistors to connect subsequent bit lines.

As shown in FIG. 3D, an interlayer insulating film (not shown) is formed on the entire surface including the cell node contacts 36a, 36b, 37a, 37b, 38a, and 38b and the bit line pad contacts 39a and 39b. The interlayer insulating film is selectively patterned to form contact holes for local wiring. Subsequently, a conductive film is formed on the entire surface including the local wiring contact hole, and then selectively patterned to form a first local wiring 40a for commonly connecting the positive cell node contacts 36a, 37a, and 38b. In this case, the first local wiring 40a is used as the positive cell node N.

A second local wiring 40b is formed to connect the subcell node contacts 36b, 37b, 38a in common.

Data is stored in the positive cell and the subcell node as described above.

In addition, a bit line pad 41a and a sub bit line pad 41b are formed to be connected to the bit line pad contact 39a and the sub bit line pad contact 39b.

As shown in FIG. 3E, after forming an interlayer insulating film (not shown) on the entire surface including the first and second local wirings 40a and 40b, the interlayer insulating film is selectively patterned to form the second local wiring 40b. The contact hole is exposed to form a), and a plate film is formed on the entire surface including the contact hole. For reference, although FIG. 3E includes a part according to the previous process before forming the dummy plate 42, reference numerals will be omitted.

Subsequently, the plate film is selectively patterned and connected to the second local wiring 40b, and overlaps a common gate terminal of the first and second load transistors, the first and second load transistors, and the first and second driving transistors. The dummy plate 42 is formed.

Subsequently, a V _CC contact 43a and a V _CC line 43b connected to a common source terminal of the first and second load transistors are formed, and V connected to a region to which the sources of the first and second driving transistors are commonly connected. _SS contacts 44a and V _SS lines 44b are formed.

Thus, the second by connecting the dummy plates 42, a local wiring (40b), a cell capacitance (C _cell) is C _nj + C _pj + C _nmos + C _pmos + C is the _Li the second local wiring (40b overlap The capacitance increases by. That is, since the C _Li increases and the area is large, the room of the cell capacitance is greatly increased. In this case, when the portion connecting the dummy plate 42 is switched to another film, a stacked capacitor may be formed.

For example, if the process proceeds to the first local wiring 40a in a conventional manner and the dummy plate 42 is connected to the second local wiring 40b, the dummy plate instead of the normal second local wiring after the second local wiring contact is defined. In other words, when the dummy plate including the second local wiring is formed, the capacitance C _Li is formed between the first local wiring 40a and the dummy plate 42.

4 is a cross-sectional view taken along the line AA ′ of FIG. 3E, and the dummy plate 42 is connected to the second local wiring 40b.

In a second method, as shown in FIG. 5, after the first and second local wirings 40a and 40b are formed, a V _CC contact is defined, and then a dummy plate 42 connected to the V _CC contact 43a. ). At this time, the dummy plate 42 includes a normal V _CC line.

As such, when the V _CC terminal and the dummy plate are connected, a capacitor between the local wiring and the V _CC may be formed.

In a third method, as shown in FIG. 6, after forming the first and second local wirings 40a and 40b, the V _SS contact is defined and the dummy plate 42 embedded in the V _SS contact 44a. ). At this time, the dummy plate 42 includes a conventional V _SS line.

As such, when the V _SS terminal and the dummy plate 42 are connected to each other, a capacitor is formed between the local wiring and the V _SS , and the V _SS contact resistance is reduced.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention increases the cell capacitance by connecting dummy plates to cell nodes, V _SS and V _CC , which store data, thereby preventing breakage of cell data due to externally injected charges even when the cell size is reduced. Therefore, there is an effect that can prevent the soft error even at low voltage.

Claims (6)

A method of manufacturing an SRAM including a transfer transistor, a driving transistor, and a load transistor, and storing data in a cell node in which a common terminal of a drain terminal of the driving transistor and a load transistor and a source terminal of the transfer transistor are commonly bonded to each other. Forming a dummy plate connected to the cell node to increase the capacitance of the cell node. The method of claim 1, Forming the dummy plate, After the cell node is formed, forming an interlayer dielectric layer on the cell node; Selectively patterning the interlayer insulating layer to form a contact hole exposing a predetermined portion of the cell node; And Forming a dummy plate connected to the cell node through the contact hole and overlapping the driving transistor and the load transistor; SRAM cell manufacturing method characterized in that comprises a. A method of manufacturing an SRAM including a transfer transistor, a driving transistor, and a load transistor, and storing data in a cell node in which a common terminal of a drain terminal of the driving transistor and a load transistor and a source terminal of the transfer transistor are commonly joined. And forming a dummy plate connected to a source terminal of the load transistor to which a power supply voltage is applied in order to increase the capacitance of the cell node. The method of claim 3, wherein Forming the dummy plate, Forming a contact hole for a power voltage at which a source terminal of the load transistor is partially exposed; Forming the dummy plate connected to the source terminal of the load transistor through the contact hole and overlapping the load transistor and the common gate terminal of the load transistor and the driving transistor; SRAM cell manufacturing method characterized in that comprises a. A method of manufacturing an SRAM including a transfer transistor, a driving transistor, and a load transistor, and storing data in a cell node in which a common terminal of a drain terminal of the driving transistor and a load transistor and a source terminal of the transfer transistor are commonly joined. And forming a dummy plate connected to the source terminal of the driving transistor to which the ground voltage is applied to increase the capacitance of the cell node. The method of claim 5, Forming the dummy plate, Forming a source terminal of the driving transistor and forming a contact hole for a ground voltage to which the source terminal of the driving transistor is exposed; Forming the dummy plate connected to the source terminal of the driving transistor through the ground voltage contact hole and overlapping the common terminal gate terminal of the driving transistor and the load transistor and the source terminal of the driving transistor; SRAM cell manufacturing method characterized in that comprises a.