JPH05226611A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make the device highly integrated one by forming a folded bit line structure wherein memory cells are arranged in matrix form and by shortening the side length of each memory cell. CONSTITUTION:Memory cells are located like a matrix and bit lines BL1-BL5 are extended to connect the memory cells A, etc., which are arranged in the Y direction. And, a word line WL is extended to connect the memory cells A-C which are connected to every other bit line BL1, BL3 and BL5 respectively and which are so arranged as to cross the bit lines BL1, BL3 and BL5 at an angle. When the word line WL is selected, data stored in the memory cells A, B, C, etc., is output to every other bit line BL1, BL3, BL5, etc., and no data is output to bit lines BL2, BL4, etc. An unselected word line part 23 of the word line WL which is between the memory cells dominates half the word line WL for one memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device called DRAM.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional example of a laminated capacitor type DRAM having a folded bit line structure. DRAM
Then, one transistor 11 and one capacitor 12
One memory cell is composed of and, and the word line WL serves as the gate electrode of the transistor 11 in the memory cell A.

The storage node electrode 15 of the capacitor 12 is in contact with the N ⁺ type diffusion layer 13, which is one of the source and drain of the transistor 11, through a contact hole 14. N, which is the other of the source and drain,
The counter electrode 17 of the capacitor 12 is provided on the ⁺ type diffusion layer 16.
Through the contact hole 18 formed in the opening of
The bit line BL1 is in contact with the memory cell A.

In this conventional example, as is apparent from FIG. 4, the bit line BL1 and the like extend in the direction connecting the diffusion layers 13 and 16, that is, the y direction in FIG. 4, and in this y direction. The word lines WL and the like extend in the orthogonal x direction.

By the way, since this one prior art example has a folded bit line configuration, it is more resistant to noise than an open bit line configuration, but as is clear from FIG. 4, focusing on one word line, that is, the x direction, Only one memory cell is formed on two bit lines. Therefore, the memory cells are not arranged in a close-packed matrix.

For this reason, the portion where the word line WL or the like between the diffusion layers 13 and 16 extends in the x direction is located on the field oxide film 21 between the memory cells adjacent in the y direction. ing. Therefore, in the word line WL and the like, the portion between the diffusion layers 13 and 16 is the so-called selected word line portion 2.
2, a portion of the word line WL or the like on the field oxide film 21 between the memory cells adjacent to each other in the y direction serves as a so-called non-selected word line portion 23.

[0007]

However, as is apparent from FIG. 4, when two unselected word line portions 23 extend between memory cells adjacent to each other in the y direction, Not only the line width of the non-selected word line portions 23 themselves but also the interval between the non-selected word line portions 23 is necessary in the y direction. Therefore, it is difficult to reduce the length of the side of the memory cell in the y direction.

As described above, since the memory cells are not arranged in the closest packed matrix, the number of memory cells of the folded bit line configuration is half the number of memory cells of the open bit line configuration. Therefore, in the conventional example shown in FIG.
It was difficult to reduce the area of the memory cell array, and high integration could not be realized.

[0009]

In a semiconductor memory device according to the present invention, memory cells are arranged in a matrix, and bit lines are connected by connecting the memory cells A arranged in the row or column direction of the matrix. BL1 to BL5 extend, and every other bit line BL1, BL3,
Connected to BL5 and these bit lines BL1, BL
3, the memory cells A arranged obliquely to BL5
The word line WL extends from connecting C to C.

[0010]

In the semiconductor memory device according to the present invention, since the word line WL connects the memory cells A to C connected to every other bit line BL1, BL3, BL5, the word line WL is used to read the memory data. Depending on WL, storage cell A ~
When C is selected, the stored data is output only every other bit line BL1, BL3, BL5, and the stored data is not output to all the bit lines BL1 to BL5. Therefore, the bit lines BL adjacent to each other
A folded bit line configuration can be formed with 1, BL2 and the like.

Moreover, since the word lines WL connect the memory cells A to C arranged obliquely to the bit lines BL1 to BL5, every other bit line BL1, BL3, B is connected.
Only the memory cells A to C connected to L5 are connected to the word line W
Even if L is connected, every other bit line BL1,
Other bit lines BL2 and B sandwiched between BL3 and BL5
By extending the word line WL between the memory cells connected by L4, these memory cells can be connected by another word line. Therefore, no memory cell to which the word line is not connected does not occur.

That is, the folded bit line structure can be formed despite the memory cells A to C being arranged in a close-packed matrix, and thus the folded bit line structure can be formed. Nevertheless, the number of so-called non-selected word line portions 23 between the memory cells of the word line WL may be 0.5 per memory cell.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention applied to a laminated capacitor type DRAM having a folded bit line structure will be described below with reference to FIGS.
Will be described with reference to. The same reference numerals are given to the components corresponding to the conventional example shown in FIG.

In order to manufacture this embodiment, FIG.
As shown in FIG. 1, the field oxide film 21 is formed in the element isolation region of the semiconductor substrate 24 by the conventionally known selective oxidation method to form the element active regions arranged in a matrix as shown in FIG. Then, the interlayer insulating film 25 which is a SiO ₂ film
Of the contact hole 18 reaching the semiconductor substrate 24
Are opened in the interlayer insulating film 25.

Then, a first-layer polycrystalline Si film is deposited on the semiconductor substrate 24, and the first-layer polycrystalline Si film is patterned to form bit lines BL1 and the like. These bit lines BL1 and the like have diffusion layers 13 and 1 to be formed later.
The field oxide film 21 between the memory cells adjacent to each other in the x direction orthogonal to the y direction in FIG. A branch portion 26 extending to the contact hole 18 of the memory cell on one side of the bit line BL1 is provided.

Next, as shown in FIG. 2B, the bit line B
The interlayer insulating film 25 is removed by etching using L1 or the like as a mask, and in this state, the gate oxide film 2 is formed on the surface of the element active region.
Form 7. Then, the second-layer polycrystalline Si film and the SiO ₂ film on the semiconductor substrate 24 are sequentially deposited by the CVD method, and these are patterned to form the word line WL and the like and the offset insulating film 28 thereon. To form. Then, using the word line WL and the field oxide film 21 as a mask, impurities are ion-implanted into the semiconductor substrate 24 to form the diffusion layers 13 and 16.

Next, as shown in FIG. 2C, an interlayer insulating film 31, which is a SiO ₂ film, is deposited on the entire surface by the CVD method, and y
A resist 32 (FIG. 1) having an opening extending in the x direction on the field oxide film 21 between the memory cells arranged in the direction and in the vicinity thereof is patterned on the interlayer insulating film 31. Then, using the resist 32 as a mask, the interlayer insulating film 3
1 is performed by RIE to open the contact hole 14 surrounded by the field oxide film 21 and the word line WL in the interlayer insulating film 31 in a self-aligned manner.

Next, as shown in FIG. 2D, a third-layer polycrystalline Si film on the semiconductor substrate 24 is deposited by the CVD method, and the third-layer polycrystalline Si film is patterned. hand,
The storage node electrode 15 of the capacitor 12 is formed. Then, an ONO film is deposited, and a fourth film on the semiconductor substrate 24 is further deposited.
A polycrystalline Si film of the layer is deposited by the CVD method, and the capacitor insulating film 33 of the capacitor 12 and the counter electrode 17 are formed of these.

The DRA of this embodiment manufactured as described above
In M, the essential structure of the memory cell itself is the same as that of the conventional example shown in FIG. 4, and the process steps are not increased as compared with the conventional example as is apparent from the above description.

In the DRAM of this embodiment as described above, for example, the word line WL is the selected word line portion 22 of the memory cells A, B, C and the like. Therefore, the potential of the word line WL is set to 5
When set to V, the transistors 11 in the memory cells A, B, C, etc.
Are turned on, and the storage data of these storage cells A, B, C, etc. are output to every other bit line BL1, BL3, BL5, etc.

However, the bit lines BL1, BL3, BL5
For the bit lines BL2, BL4, etc., between the contact holes 18, etc., the interlayer insulating film 31 on the contact hole 18 and the field oxide film 2
Since the word line WL extends over 1 and these portions are non-selected word line portions 23, the bit line BL
No stored data is output to 2, BL4 and the like.

Therefore, if the bit lines BL1 and BL2 are connected to the same sense amplifier, for example, the bit line BL2
Since the potential of the bit line BL2 remains at the precharge level and the potential of the bit line BL2 can be used as the reference potential for the bit line BL1, the folded bit line configuration is formed by the bit lines BL1 and BL2.

In the embodiment shown in FIG. 1, the word lines WL and the like are entirely linear, and the word lines WL and the like obliquely intersect both the element active region and the field oxide film 21. However, as shown in FIG. 3, the word line W is formed only for the field oxide film 21 between the memory cells arranged in the x direction.
You may cross L etc. diagonally.

However, in the embodiment shown in FIG. 1 as well, since the inclination angle of the word line WL or the like with respect to the element active region and the field oxide film 21 is small, the word line WL in the y direction is small.
And the like, and the side length in the y direction of the memory cell does not increase so much.

[0025]

In the semiconductor memory device according to the present invention, a folded bit line structure can be formed even though the memory cells are arranged in a densest matrix, and thus the folded bit line structure can be formed. Although it can be formed, the number of so-called non-selected word line portions between the memory cells among the word lines may be 0.5 per memory cell. Can be shortened. Therefore, the area of the memory cell array can be reduced, and high integration can be realized.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a side sectional view sequentially showing a manufacturing process at a position along line II-II in FIG.

FIG. 3 is a plan view of a main part of a modified example of the embodiment.

FIG. 4 is a plan view of a conventional example of the present invention.

[Explanation of symbols]

 A memory cell B memory cell C memory cell WL word line BL1 bit line BL2 bit line BL3 bit line BL4 bit line BL5 bit line

Claims (1)

[Claims] 1. A semiconductor memory device comprising a memory cell composed of a transistor and a capacitor, wherein the memory cells are arranged in a matrix, and the memory cells arranged in a row or column direction of the matrix are arranged. A semiconductor in which bit lines extend in connection with each other and word lines extend in connection with the memory cells connected to every other bit line and arranged in a direction oblique to the bit lines. Storage device.