KR20000061842A - Manufacturing method for mos transistor - Google Patents
Manufacturing method for mos transistor Download PDFInfo
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- KR20000061842A KR20000061842A KR1019990011222A KR19990011222A KR20000061842A KR 20000061842 A KR20000061842 A KR 20000061842A KR 1019990011222 A KR1019990011222 A KR 1019990011222A KR 19990011222 A KR19990011222 A KR 19990011222A KR 20000061842 A KR20000061842 A KR 20000061842A
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- gate
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- oxide film
- metal
- polysilicon
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 64
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 15
- 230000002265 prevention Effects 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims description 48
- 230000004888 barrier function Effects 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 23
- 238000005468 ion implantation Methods 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 8
- 125000001475 halogen functional group Chemical group 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 239000003963 antioxidant agent Substances 0.000 claims description 3
- 230000003078 antioxidant effect Effects 0.000 claims description 3
- -1 hydrogen ions Chemical class 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000010405 reoxidation reaction Methods 0.000 abstract description 16
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000003064 anti-oxidating effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
Abstract
Description
본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 특히 실리콘 게이트의 상부에 금속게이트가 적층된 구조의 게이트를 갖는 모스 트랜지스터의 제조공정에 있어서, 그 게이트 형성시 그 금속게이트의 측면에 불순물 이온을 주입한 후, 다결정실리콘 게이트를 형성하고, 재산화막을 형성함으로써 금속게이트가 산화되는 것을 방지하여 모스 트랜지스터의 특성을 향상시키는데 적당하도록 한 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor manufacturing method. In particular, in the manufacturing process of a MOS transistor having a gate having a structure in which metal gates are stacked on top of a silicon gate, impurity ions are implanted into the side of the metal gate when the gate is formed. Thereafter, the present invention relates to a MOS transistor fabrication method in which a polysilicon gate is formed and a reoxidation film is formed to prevent the metal gate from being oxidized, thereby making it suitable for improving characteristics of the MOS transistor.
도1a 내지 도1d는 종래 모스 트랜지스터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 일부에 필드산화막(2)을 증착하여, 소자형성영역을 정의하고, 그 소자형성영역의 상부에 게이트산화막(3)을 증착하는 단계(도1a)와; 상기 게이트산화막(3)의 상부에 다결정실리콘, 배리어금속, 금속, 산화막을 순차적으로 증착하고, 패턴을 형성하여 상기 게이트산화막(3)의 중앙상부에 순차적으로 적층된 다결정실리콘 게이트(4), 배리어금속층(5), 금속 게이트(6), 캡산화막(7)을 형성한 후, 상기 구조의 상부전면에 절연막(8)을 증착한 다음, 경사이온주입을 통해 상기 다결정실리콘 게이트(4)의 측면 기판(1) 하부영역에 할로방지영역(9)을 형성하는 단계(도1b)와; 불순물 이온주입공정을 통해 상기 다결정실리콘 게이트(4)의 측면 기판(1) 하부영역에 저농도 소스 및 드레인(10)을 형성하는 단계(도1c)와; 상기 다결정실리콘 게이트(4), 배리어금속층(5), 금속 게이트(6), 캡산화막(7)의 측면에 형성된 절연막(8)의 측면에 측벽(11)을 형성한 후, 불순물 이온주입을 통해 상기 측벽(11)의 측면 기판하부에 고농도 소스 및 드레인(12)을 형성하는 단계(도1d)로 구성된다.1A to 1D are cross-sectional views illustrating a manufacturing process of a conventional MOS transistor. As shown in FIG. Depositing a gate oxide film 3 on the substrate (Fig. 1A); Polycrystalline silicon, a barrier metal, a metal, an oxide film are sequentially deposited on the gate oxide film 3, a pattern is formed, and the polysilicon gate 4 and the barrier are sequentially stacked on the center of the gate oxide film 3. After forming the metal layer 5, the metal gate 6, and the cap oxide film 7, the insulating film 8 is deposited on the upper surface of the structure, and then the side surface of the polysilicon gate 4 is inclined through ion implantation. Forming a halo prevention region 9 in the lower region of the substrate 1 (FIG. 1B); Forming a low concentration source and drain 10 in the lower region of the side substrate 1 of the polysilicon gate 4 through an impurity ion implantation process (FIG. 1C); After forming the sidewall 11 on the side of the insulating film 8 formed on the side of the polysilicon gate 4, the barrier metal layer 5, the metal gate 6, the cap oxide film 7 through the impurity ion implantation And forming a highly concentrated source and drain 12 under the side substrate of the side wall 11 (FIG. 1D).
이하, 상기와 같이 구성된 종래 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the conventional MOS transistor manufacturing method configured as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)의 상부 일부에 필드산화막(2)을 증착하여, 노출된 기판(1) 영역인 소자형성영역을 정의하고, 그 소자형성영역의 상부에 게이트산화막(3)을 증착한다.First, as shown in FIG. 1A, a field oxide film 2 is deposited on a portion of an upper portion of the substrate 1 to define an element formation region, which is an exposed substrate 1 region, and a gate oxide layer on the element formation region. (3) is deposited.
그 다음, 도1b에 도시한 바와 같이 상기 게이트산화막(3)과 필드산화막(2)의 상부전면에 다결정실리콘, 배리어금속, 금속, 산화막을 순차적으로 증착하고, 그 산화막의 상부에 포토레지스트를 도포하고, 노광 및 현상하여 게이트 패턴을 형성한 후, 그 포토레지스트를 식각마스크로 사용하는 식각공정으로 상기 산화막, 금속, 배리어금속, 다결정실리콘을 순차적으로 식각하여 상기 게이트산화막(3)의 중앙상부에 다결정실리콘 게이트(4)를 형성하고, 그 다결정실리콘 게이트(4)의 상부에 순차적으로 적층된 배리어금속층(5), 금속 게이트(6), 캡산화막(7)구조를 형성한다.Next, as shown in FIG. 1B, polycrystalline silicon, a barrier metal, a metal, and an oxide film are sequentially deposited on the upper surfaces of the gate oxide film 3 and the field oxide film 2, and a photoresist is applied on the oxide film. After exposure and development to form a gate pattern, the oxide film, the metal, the barrier metal, and the polysilicon are sequentially etched in an etching process using the photoresist as an etching mask, and the upper portion of the gate oxide film 3 is formed. The polysilicon gate 4 is formed, and the barrier metal layer 5, the metal gate 6, and the cap oxide film 7 which are sequentially stacked on the polysilicon gate 4 are formed.
그 다음, 상기 구조의 상부전면에 얇은 절연막(8)을 증착하고, 그 절연막(8)을 이온주입버퍼로 사용하는 경사이온주입공정으로 불순물 이온을 이온주입하여 상기 다결정실리콘 게이트(4)의 측면 기판(1) 하부영역과 그 다결정실리콘 게이트(4) 하부주변부의 기판영역에 할로방지영역(9)을 형성한다.Next, a thin insulating film 8 is deposited on the upper surface of the structure, and impurity ions are implanted in a gradient ion implantation process using the insulating film 8 as an ion implantation buffer to form side surfaces of the polysilicon gate 4. The halo prevention region 9 is formed in the lower region of the substrate 1 and the substrate region of the lower peripheral portion of the polysilicon gate 4.
그 다음, 도1c에 도시한 바와 같이 상기 구조에 불순물이온을 이온주입하여 상기 다결정실리콘 게이트(4)의 측면 기판(1)하부에 저농도 소스 및 드레인(10)을 형성한다.Then, as shown in FIG. 1C, impurity ions are implanted into the structure to form a low concentration source and drain 10 under the side substrate 1 of the polysilicon gate 4.
그 다음, 도1d에 도시한 바와 같이 상기 구조의 상부전면에 절연막을 두껍게 증착하고, 그 절연막을 건식식각하여 상기 다결정실리콘 게이트(4), 배리어금속층(5), 금속 게이트(6), 캡산화막(7)의 측면에 증착되어 있는 절연막(8)의 측면에 측벽(11)을 형성한다.Then, as shown in Fig. 1D, a thick insulating film is deposited on the upper surface of the structure, and the insulating film is dry etched to form the polysilicon gate 4, the barrier metal layer 5, the metal gate 6, and the cap oxide film. The side wall 11 is formed in the side surface of the insulating film 8 deposited on the side surface (7).
그 다음, 상기 측벽(11)을 이온주입 마스크로 사용하는 이온주입공정으로 불순물 이온을 이온주입하여 상기 측벽(11)의 측면 기판하부에 고농도 소스 및 드레인을 형성하여 모스 트랜지스터를 제조한다.Next, an impurity ion is implanted in the ion implantation process using the sidewall 11 as an ion implantation mask to form a high concentration source and drain under the side substrate of the sidewall 11 to manufacture a MOS transistor.
상기의 과정에서 보통 다결정실리콘 게이트를 형성하는 과정에서 그 다결정실리콘 게이트(4)의 측면이 손상되며, 이를 복원하기 위해서는 그 다결정실리콘 게이트(4)의 측면에 재산화막을 형성하게 되나, 이와 같은 과정에서 상기 금속 게이트(6)와 배리어금속층(5)의 측면부가 산화되어 모스 트랜지스터의 특성이 열화되는 경우가 있으며, 이를 방지하기 위해 다결정실리콘 게이트(4)의 측면 산화를 위한 반응가스에 수증기와 질소가스외에 수소가스를 사용해야 하며, 이때에는 반응가스의 추가에 의한 가스관의 설치 등 비용이 증가하게 된다.In the above process, the side of the polysilicon gate 4 is usually damaged in the process of forming the polysilicon gate, and in order to restore the polysilicon gate 4, a reoxidation film is formed on the side of the polysilicon gate 4, The sidewalls of the metal gate 6 and the barrier metal layer 5 may be oxidized to deteriorate characteristics of the MOS transistor. In order to prevent this, the reaction gas for lateral oxidation of the polysilicon gate 4 may be water vapor and nitrogen. In addition to the gas, hydrogen gas should be used, and the cost of the gas pipe is increased due to the addition of the reaction gas.
상기한 바와 같이 종래 모스 트랜지스터 제조방법은 금속 게이트와 다결정실리콘 게이트를 동일 마스크를 사용하는 식각공정을 통해 순차적으로 형성함으로써, 식각공정에 의한 다결정실리콘의 측면손상을 복원하기 위해 재산화막을 증착하는 경우 그 다결정실리콘 게이트의 상부측에 위치하는 금속게이트의 측면이 산화되어 모스 트랜지스터의 특성이 열화되는 문제점이 있었다.As described above, in the conventional method of manufacturing a MOS transistor, a metal gate and a polysilicon gate are sequentially formed through an etching process using the same mask, thereby depositing a reoxidation film to restore side damage of the polysilicon by the etching process. There is a problem in that the side surface of the metal gate located on the upper side of the polysilicon gate is oxidized to deteriorate the characteristics of the MOS transistor.
이와 같은 문제점을 감안한 본 발명은 금속 게이트의 측면산화를 방지하면서 다결정실리콘 게이트의 측면에 재산화막을 증착할 수 있는 모스 트랜지스터 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a MOS transistor manufacturing method capable of depositing a reoxidation film on the side of a polysilicon gate while preventing side oxidation of the metal gate.
도1a 내지 도1d는 종래 모스 트랜지스터의 제조공정 수순단면도.1A to 1D are cross-sectional views of a manufacturing process of a conventional MOS transistor.
도2a 내지 도2e는 본 발명 모스 트랜지스터 제조공정 수순단면도.2A to 2E are cross-sectional views of a MOS transistor manufacturing process of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:필드산화막1: Substrate 2: Field Oxide
3:게이트산화막 4:다결정실리콘 게이트3: gate oxide film 4: polysilicon gate
5:배리어 금속층 6:금속 게이트5: Barrier metal layer 6: Metal gate
7:캡산화막 8:절연막7: Cap oxide film 8: Insulation film
9:할로방지영역 10:저농도 소스 및 드레인9: halo protection area 10: low concentration source and drain
11:측벽 12:고농도 소스 및 드레인11: side wall 12: high concentration source and drain
13:산화방지막 14:재산화막13: Antioxidation film 14: Reoxidation film
상기와 같은 목적은 금속 게이트를 형성하고, 다결정실리콘 게이트의 형성 이전에 그 금속 게이트의 측면에 산화방지막을 형성한 후, 다결정실리콘 게이트를 형성하고, 그 다결정실리콘 게이트의 측면을 산화시킴으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설 명하면 다음과 같다.The above object is achieved by forming a metal gate, forming an anti-oxidation film on the side of the metal gate before forming the polysilicon gate, forming a polysilicon gate, and oxidizing the side of the polysilicon gate. When described in detail with reference to the accompanying drawings, the present invention as follows.
도2a 내지 도2e는 본 발명 모스 트랜지스터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 형성하여 소자형성영역을 정의하고, 그 소자형성영역의 상부에 게이트산화막(3)을 형성하는 단계(도1a)와; 상기 게이트산화막(3)의 상부전면에 다결정실리콘(4), 배리어금속, 금속, 산화막을 순차적으로 증착하고, 사진식각공정을 통해 상기 산화막과 그 하부의 금속, 배리어금속을 패터닝하여, 캡산화막(7), 금속 게이트(6), 배리어금속층(5)을 형성한 다음, 수소이온을 경사이온주입하여 상기 금속 게이트(6)와 배리어금속층(5)의 측면에 산화방지막(13)을 형성하는 단계(도2b)와; 상기 캡산화막(7)을 식각마스크로 사용하는 식각공정으로 상기 다결정실리콘(4)을 식각하여 다결정실리콘 게이트(4)를 형성한 후, 그 다결정실리콘 게이트(4)를 산화시켜, 그 다결정실리콘 게이트(4)의 측면에 재산화막(14)을 형성하고, 상기의 구조 상부전면에 절연막(8)을 증착하는 단계(도2c)와; 경사이온주입을 통해 상기 재산화막(14)의 하부 및 그 측면 하부의 기판(1) 영역에 할로방지영역(9)을 형성한다음, 상기 캡산화막(7)과 필드산화막(2)을 이온주입마스크로 사용하는 이온주입공정으로 상기 재산화막(14)의 측면 기판(1) 하부에 저농도 소스 및 드레인(10)을 형성하는 단계(도2d)와; 상기 다결정실리콘 게이트(4), 배리어금속층(5), 금속 게이트(6), 캡산화막(7) 적층구조의 측면에 증착된 절연막(8)의 측면에 측벽(11)을 형성하고, 불순물 이온주입공정을 통해 상기 측벽(11)의 측면 기판(1) 하부에 고농도 소스 및 드레인(12)을 형성하는 단계(도2e)를 포함하여 구성된다.2A through 2E are cross-sectional views of a manufacturing process of the MOS transistor according to the present invention. As shown in the drawing, the field oxide film 2 is formed on the substrate 1 to define an element formation region, and the upper portion of the element formation region. Forming a gate oxide film 3 on the substrate (Fig. 1A); The polycrystalline silicon 4, the barrier metal, the metal, and the oxide film are sequentially deposited on the upper surface of the gate oxide film 3, and the patterned oxide film, the metal and the barrier metal below thereof are patterned through a photolithography process, and a cap oxide film ( 7), forming the metal gate 6 and the barrier metal layer 5, and then forming the anti-oxidation film 13 on the side of the metal gate 6 and the barrier metal layer 5 by injecting hydrogen ions inclined ions. (Fig. 2b); In the etching process using the cap oxide film 7 as an etching mask, the polysilicon 4 is etched to form a polysilicon gate 4, and then the polysilicon gate 4 is oxidized to form the polysilicon gate 4. Forming a reoxidation film (14) on the side of (4) and depositing an insulating film (8) on the upper surface of the structure (FIG. 2C); Through the gradient ion implantation, a halo prevention region 9 is formed in the region of the substrate 1 at the lower side of the reoxidation film 14 and the lower side of the reoxidation film 14, and then ion implantation of the cap oxide film 7 and the field oxide film 2. Forming a low concentration source and drain 10 under the side substrate 1 of the reoxidation film 14 by an ion implantation process used as a mask (FIG. 2D); Sidewalls 11 are formed on the sidewalls of the insulating film 8 deposited on the sidewalls of the polysilicon gate 4, the barrier metal layer 5, the metal gate 6, and the cap oxide film 7, and impurity ion implantation is performed. Forming a high concentration source and drain 12 under the side substrate 1 of the sidewall 11 through the process (FIG. 2E).
이하, 상기와 같은 본 발명 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the method of manufacturing the MOS transistor of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 형성하여 소자형성영역을 정의하고, 그 소자형성영역의 상부에 게이트산화막(3)을 형성한다.First, as shown in FIG. 2A, the field oxide film 2 is formed on the substrate 1 to define the device formation region, and the gate oxide film 3 is formed on the device formation region.
그 다음, 도2b에 도시한 바와 같이 상기 게이트산화막(3)과 필드산화막(2)의 상부전면에 다결정실리콘(4), 배리어금속, 금속, 산화막을 순차적으로 증착한다.Next, as shown in FIG. 2B, polycrystalline silicon 4, a barrier metal, a metal, and an oxide film are sequentially deposited on the upper surfaces of the gate oxide film 3 and the field oxide film 2. As shown in FIG.
그 다음, 상기 산화막의 상부전면에 포토레지스트를 도포하고, 노광 및 현상하여 게이트 패턴을 형성한 후, 그 게이트 패턴을 식각마스크로 사용하는 식각공정으로 상기 증착된 산화막과 금속, 배리어금속을 식각하여 배리어 금속층(5), 금속 게이트(6), 캡산화막(7)의 적층구조를 형성한다.Next, a photoresist is applied to the upper surface of the oxide film, exposed and developed to form a gate pattern, and then the deposited oxide film, the metal, and the barrier metal are etched by an etching process using the gate pattern as an etching mask. A laminated structure of the barrier metal layer 5, the metal gate 6, and the cap oxide film 7 is formed.
이때, 상기 증착한 다결정실리콘을 식각하지 않는다.At this time, the deposited polysilicon is not etched.
그 다음, 상기의 구조에서 수소이온을 경사이온주입하여 상기 금속 게이트(6)와 배리어 금속층(5)의 측면에 산화방지막(13)을 형성한다.Then, in the above structure, hydrogen ions are implanted with gradient ions to form an antioxidant film 13 on the side surfaces of the metal gate 6 and the barrier metal layer 5.
그 다음, 도2c에 도시한 바와 같이 상기 캡산화막(7)을 식각마스크로 사용하는 식각공정으로 상기 노출되어있는 다결정실리콘을 식각하여 다결정실리콘 게이트(4)를 형성한다.Next, as shown in FIG. 2C, the exposed polysilicon is etched by an etching process using the cap oxide film 7 as an etching mask to form a polysilicon gate 4.
이와 같은 식각공정으로 상기 다결정실리콘 게이트(4)의 측면은 손상되며, 이를 복원하기 위해 산화막을 증착하여 상기 다결정실리콘 게이트(4)의 측면에 재산화막(14)을 형성하게 된다. 이때의 재산화막(14)을 형성하는 공정은 일반적인 산화공정에서와 같이 수증기와 질소가스를 사용하여 형성하며, 이때 상기 배리어 금속층(5)과 금속 게이트(6)의 측면에는 수소이온주입에 의한 산화방지막(13)의 형성으로 산화를 방지할 수 있게 된다. 이와 같은 과정은 미리주입된 수소의 환원작용과 재산화막(14) 형성시 사용하는 수증기의 산화작용이 균형을 이루어 가능해진다.In this etching process, the side surface of the polysilicon gate 4 is damaged, and an oxide film is deposited to restore the polysilicon gate 4 to form the reoxidation film 14 on the side surface of the polysilicon gate 4. At this time, the step of forming the reoxidation film 14 is formed by using water vapor and nitrogen gas as in the normal oxidation process, wherein the side of the barrier metal layer 5 and the metal gate 6 is oxidized by hydrogen ion injection The formation of the prevention film 13 makes it possible to prevent oxidation. This process can be achieved by balancing the reduction of the pre-injected hydrogen and the oxidation of the water vapor used in the formation of the reoxidation film (14).
그 다음, 도2d에 도시한 바와 같이 상기의 구조에 경사이온주입공정을 통해 할로방지영역(9)을 형성함과 아울러 일반적인 이온주입공정을 통해 상기 다결정실리콘 게이트(4)의 측면에 형성된 재산화막(14)의 측면 하부 기판(1)에 저농도 소스 및 드레인(10)을 형성한다.Next, as shown in FIG. 2D, a halo prevention region 9 is formed in the above structure through a gradient ion implantation process, and a reoxidation film formed on the side of the polysilicon gate 4 through a general ion implantation process. A low concentration source and drain 10 are formed in the lower side substrate 1 of 14.
그 다음, 도2e에 도시한 바와 같이 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 다결정실리콘 게이트(4), 배리어금속층(5), 금속 게이트(6), 캡산화막(7) 적층구조의 측면에 증착된 절연막(8)의 측면에 측벽(11)을 형성하고, 그 측벽(11)을 이온주입마스크로 하는 이온주입공정으로 불순물 이온을 주입하여 상기 측벽(11)의 측면 기판(1) 하부에 고농도 소스 및 드레인(12)을 형성하여 모스 트랜지스터를 형성하게 된다.Next, as shown in FIG. 2E, an insulating film is deposited on the upper surface of the structure, and the insulating film is etched dry to form the polysilicon gate 4, the barrier metal layer 5, the metal gate 6, and the cap oxide film ( 7) A sidewall 11 is formed on the side of the insulating film 8 deposited on the side of the laminated structure, and impurity ions are implanted in the ion implantation process using the sidewall 11 as an ion implantation mask to form the sidewall 11. The MOS transistor is formed by forming a high concentration source and drain 12 under the side substrate 1.
상기한 바와 같이 본 발명은 다결정실리콘 게이트와 금속 게이트를 갖는 모스 트랜지스터를 형성하는 과정에서, 그 금속 게이트의 측면에 산화방지막을 형성한 후, 다결정실리콘 게이트를 형성하고, 그 다결정실리콘 게이트의 측면 손상을 복원하기 위한 재산화막을 형성함으로써, 기존의 산화공정을 그대로 사용하면서 소자의 특성을 향상시키는 효과가 있다.As described above, in the process of forming a MOS transistor having a polysilicon gate and a metal gate, an anti-oxidation film is formed on the side of the metal gate, and then a polysilicon gate is formed, and the side damage of the polysilicon gate is formed. By forming a reoxidation film for restoring the structure, there is an effect of improving the characteristics of the device while using the existing oxidation process as it is.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100376868B1 (en) * | 2000-11-06 | 2003-03-19 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100585011B1 (en) * | 2000-06-30 | 2006-05-29 | 주식회사 하이닉스반도체 | Method for forming gateelectrode in semiconductor device |
| US7098123B2 (en) | 2003-02-19 | 2006-08-29 | Samsung Electronics Co., Ltd. | Methods of forming a semiconductor device having a metal gate electrode and associated devices |
| KR100632619B1 (en) * | 2000-06-30 | 2006-10-09 | 주식회사 하이닉스반도체 | Gate electrode formation method of semiconductor device |
| KR100646984B1 (en) * | 2000-06-30 | 2006-11-17 | 주식회사 하이닉스반도체 | Method of manufacturing a gate electrode in a semiconductor device |
| KR100695896B1 (en) * | 2006-02-22 | 2007-03-19 | 삼성전자주식회사 | Method of forming semiconductor device having metal gate electrode and the device so formed |
-
1999
- 1999-03-31 KR KR1019990011222A patent/KR100289808B1/en not_active IP Right Cessation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100585011B1 (en) * | 2000-06-30 | 2006-05-29 | 주식회사 하이닉스반도체 | Method for forming gateelectrode in semiconductor device |
| KR100632619B1 (en) * | 2000-06-30 | 2006-10-09 | 주식회사 하이닉스반도체 | Gate electrode formation method of semiconductor device |
| KR100646984B1 (en) * | 2000-06-30 | 2006-11-17 | 주식회사 하이닉스반도체 | Method of manufacturing a gate electrode in a semiconductor device |
| KR100376868B1 (en) * | 2000-11-06 | 2003-03-19 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| US7098123B2 (en) | 2003-02-19 | 2006-08-29 | Samsung Electronics Co., Ltd. | Methods of forming a semiconductor device having a metal gate electrode and associated devices |
| KR100695896B1 (en) * | 2006-02-22 | 2007-03-19 | 삼성전자주식회사 | Method of forming semiconductor device having metal gate electrode and the device so formed |
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