KR20000056249A - Field Effect Transistor with reduced parastic capacitance &method for fabricating thereof - Google Patents

Abstract

PURPOSE: A method for manufacturing a field effect transistor(TFT) is provided to reduce a parasitic capacitance caused by a gate fringe capacitance by stably forming an air gap in a region where a dielectric layer of the gate spacer is formed. CONSTITUTION: A method for manufacturing a field effect transistor(TFT) comprises the steps of: forming a gate pattern including a gate electrode on a semiconductor substrate in which an isolation process is carried out, a capping layer on the gate electrode, and a first gate spacer surrounding a sidewall of the gate electrode and the capping layer; forming a multi-layered epitaxial layer having a raised structure on the semiconductor substrate having the gate pattern; depositing and etching an insulation layer for a second gate spacer on a resultant structure having a stack of the epitaxial layer, so as to form the second gate spacer which is lower than the first gate spacer in height, the second gate spacer covering a facet of an edge of the epitaxial layer; forming a third gate spacer on the second gate spacer and on a sidewall of the first gate spacer after depositing and etching an insulation layer for the third gate spacer on the resultant structure; performing a wet-etching to eliminate the capping layer and the second gate spacer; forming a first and second silicide layers on the gate electrode and the epitaxial layer; and forming an interlayer dielectric covering the resultant structure.

Description

Field effect transistor with reduced parasitic capacitance and its manufacturing method {Field Effect Transistor with reduced parastic capacitance & method for fabricating}

The present invention relates to a semiconductor device, and more particularly, to a field effect transistor (FET) and a method of manufacturing the same.

As the size and design rules of semiconductor devices are gradually reduced, the scale-down of metal oxide semiconductor FETs (MOSFETs), which is an important element constituting semiconductor devices, is also accelerating. The increase in the degree of integration of the semiconductor device and the reduction of the power consumption of the semiconductor device are also considered to be important, and the improvement of the operation speed of the semiconductor device has emerged as an important problem to be solved. There are many factors to consider in improving the operation speed of semiconductor devices, but one of them is a parasitic capacitance problem. The parasitic capacitance is present in various parts of the completed semiconductor device, causing a delay in operation speed. One of the parasitic capacitances is a gate peripheral capacitance caused by a dielectric film between a gate electrode and a channel of a source / drain. Fringe capacitance). The capacitance around the gate deteriorates the characteristics of the gate electrode, causing a gate delay time.

In order to reduce the parasitic capacitance caused by the capacitance around the gate, the structure of the field effect transistor (FET) which forms an air gap in the dielectric film at the gate spacer location exists in theory, but the field effect of the structure Since the transistor has an adverse effect on the oxide film, which is a gate insulating film, it is difficult to apply the transistor realistically due to the reliability construction of the semiconductor device or the process repeatability.

The technical problem to be achieved by the present invention is the parasitic capacitance due to the gate fringe capacitance by stably forming an air gap in the place where the dielectric film of the gate spacer is formed using a triple spacer structure. At the same time, the electric field effect can suppress the adverse effect on the semiconductor device by the facet generated at the edge of the epilayer when the epilayers are stacked by the selective epitaxial growth (SEG). To provide a transistor (FET).

Another object of the present invention is to provide a method for manufacturing a field effect transistor that can reduce the parasitic capacitance.

1 to 5 are cross-sectional views illustrating a field effect transistor and a method of manufacturing the same to reduce parasitic capacitance according to a first embodiment of the present invention.

6 to 11 are cross-sectional views illustrating a field effect transistor and a method of manufacturing the same for reducing parasitic capacitances according to a second embodiment of the present invention.

Explanation of the No. 1 for the main part of the drawing

100: semiconductor substrate, 102: field oxide film,

104: gate insulating film, 106: gate electrode,

108: capping layer, 110: first gate spacer,

112: epi layer, 114: shallow junction source / drain regions,

116: second gate spacer, 118: third gate spacer,

120: source / drain regions of deep junctions,

122: air gap, 124: first silicide layer,

126: second silicide layer, 128: interlayer dielectric film (ILD)

In order to achieve the above technical problem, the present invention provides, through the first embodiment, (1) a semiconductor substrate, (2) a gate electrode formed in a predetermined region of the semiconductor substrate, and (3) a first silicide formed on the gate electrode. And an epitaxial layer formed on the semiconductor substrate next to the gate electrode formed on the sidewalls of the gate electrode and the first silicide layer, and on the semiconductor substrate next to the gate electrode on which the first gate spacer is formed. (epi layer), (6) a second gate spacer formed on the epi layer outside the first gate spacer, (7) a third gate spacer formed on the epi layer outside the second gate spacer, and (8 A second silicide layer formed on the epi layer surface, an interlayer insulating film (ILD) covering the entire semiconductor substrate, and (9) the first and third gate spacers and the interlayer. Provides a field effect transistor that can reduce the parasitic capacitance, characterized in comprising an air gap is configured in the upper and lower portions of the second gate spacer is closed by a smoke screen.

In order to achieve the above technical problem, the present invention provides, through a second embodiment, (1) a semiconductor substrate, (2) a gate electrode formed in a predetermined region of the semiconductor substrate, and (3) a first silicide formed on the gate electrode. And an epitaxial layer formed on the semiconductor substrate next to the gate electrode formed on the sidewalls of the gate electrode and the first silicide layer, and on the semiconductor substrate next to the gate electrode on which the first gate spacer is formed. (epi layer), (6) a third gate spacer configured outside the first gate spacer and having a shape in which a lower portion of the first gate spacer does not touch the epi layer, and (7) a second structure formed on the epi layer. A third gate spacer lowered by a silicide layer, (8) an interlayer insulating film (ILD) covering the entire resultant product, and (9) the interlayer insulating film and over the edge of the epi layer. Provided is a field effect transistor that can reduce parasitic capacitance, characterized in that it has an air gap configured in the rack.

According to a preferred embodiment of the present invention, it is preferable that the first and third gate spacers are made of a nitride film, and the second gate spacers are made of an oxide film.

Preferably, it is preferable that the epi layer further comprises a source / drain region of shallow junction and deep junction.

In accordance with another aspect of the present invention, a capping layer formed on an upper portion of a gate electrode and a sidewall of the gate electrode and a capping layer is formed on a semiconductor substrate in which device isolation is performed. A first step of forming a gate pattern having a first gate spacer formed thereon; a second step of laminating an epi layer having a structure raised on the surface of the semiconductor substrate except for the gate pattern; A third process of depositing and etching an insulating film for three gate spacers to form second and third gate spacers, a fourth process of performing wet etching so that the capping layer is removed, and the second gate spacer is overetched; And a fifth process of forming first and second silicide layers on the epitaxial layer and on the gate electrode from which the capping layer is removed, and the resultant product. Provides a method for producing a field effect transistor that can reduce the parasitic capacitance which is characterized in that it comprises a sixth step of forming an interlayer insulating film (ILD).

In accordance with another aspect of the present invention, there is provided a gate electrode on a semiconductor substrate in which device isolation is performed. A first process of forming a gate pattern having a capping layer formed on the gate electrode and a first gate spacer surrounding sidewalls of the gate electrode and the capping layer; and a structure that is formed on a surface of the semiconductor substrate on which the gate pattern is formed A second step of stacking an epitaxial layer of the epitaxial layer; and depositing and etching an insulating film for a second gate spacer on a resultant layer of the epitaxial layer to cover an edge face of the epitaxial layer, and forming a height higher than that of the first gate spacer. Forming a second gate spacer having a low temperature; and forming a third gate spacer on the second gate spacer and on the sidewalls of the first gate spacer by depositing and etching an insulating film for a third gate spacer on the resultant. A fourth process of performing wet etching to remove the capping layer and the second gate spacer, and the capping process. And a seventh step of forming a first and a second silicide layer on the removed gate electrode and the epitaxial layer, and a seventh step of forming an interlayer insulating film (ILD) covering the resultant. It provides a method of manufacturing a field effect transistor that can reduce the.

According to a preferred embodiment of the present invention, in the first embodiment, the thicknesses of the second and third gate spacers are preferably formed to sufficiently cover the facet of the epi layer in a subsequent etching process. .

In addition, the wet etching may be performed by using an etching selectivity difference between the second gate spacer and the first and third gate spacers.

According to the present invention, it is possible to realize a reliable semiconductor device having an air gap on the side of the gate spacer, and to solve the problem of imbalance in the junction depth caused by the edge facet of the epi layer, while providing a shallow junction. (shallow junction) can be implemented, and the problem that the gate electrode and the source / drain regions are disconnected from each other can be suppressed, and by forming an air gap partially on the second gate spacer, a second silicide layer can be formed on the epi layer. Encroachment problems can be prevented from occurring in the silicide reaction process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The invention can be practiced in other ways without departing from its spirit and essential features. For example, in the above preferred embodiment, the field oxide film is an oxide film by a trench process, but this may be an oxide film by LOCOS. In addition, even if the second gate spacer is not an oxide film, even if the second gate spacer is substituted with any film quality having an etching selectivity with the first and third gate spacers, the effect sought in the present invention can be achieved. Therefore, the content described in the following preferred embodiments is exemplary and not intended to be limiting.

<First Embodiment>

1 to 5 are cross-sectional views illustrating a field effect transistor and a method of manufacturing the same to reduce parasitic capacitance according to a first embodiment of the present invention.

Referring to FIG. 1, a trench isolation process is performed on a silicon single crystal semiconductor substrate 100 to form a field oxide layer 102 defining an active region and an inactive region. Subsequently, a gate insulating film 104 is formed through oxidation, and a gate electrode 106, for example, a polysilicon layer is deposited on the gate insulating film 104, and is deposited on the gate electrode 106. A capping layer 108 formed of an oxide film SiO ₂ is formed. Subsequently, the capping layer 108, the gate electrode 106, and the gate insulating layer 104 are etched in a direction perpendicular to the semiconductor substrate 100, and then, an ion implantation process is performed using an ion implantation mask, thereby forming the semiconductor substrate 100. ) Form a source / drain region (LDD: Lightly Source / Drain region) with a shallow junction. The capping layer 108 and the gate electrode 106 may be deposited by depositing a first gate spacer insulating layer, for example, a nitride layer SiN, on the resultant of the shallow junction source / drain region 114, and anisotropic etching. And a first gate spacer 110 on sidewalls of the gate insulating film 104. Subsequently, the epi layer 112 due to selective epitaxial growth (SEG) is excluded except for the gate pattern, that is, the gate electrode 106, the capping layer 108, and the first gate spacer 110. The semiconductor substrate 100 is formed of an elevated source / drain.

Referring to FIG. 2, an oxide film and a nitride film to be used as the second and third gate spacers 116 and 118 are sequentially stacked on the entire surface of the semiconductor substrate on which the epitaxial layer 112 by the SEG is formed. . Here, since the air cap is formed on the second gate spacer 116 by using an etching selectivity between the second gate spacer 116 and the first and third gate spacers 110 and 118, the insulating film for the gate spacer is used. This should be taken into account when determining the material.

Referring to FIG. 3, dry etching is performed on the insulating layers for the second and third gate spacers to cover the outside of the first gate spacer 110 on the epitaxial layer 112. Third gate spacers 116 'and 118' are formed. In this case, since the facet is formed at the edge of the epitaxial layer 112 when the SEG is performed on the epitaxial layer 112, the second and third gate spacers 116 ′ and 118 ′ are formed for the epitaxial layer 112. After the dry etching process, the second and third gate spacers 116 'and 118' are simultaneously exposed to the outside. Accordingly, the thicknesses of the second and second gate spacers 116 ′ and 118 ′ may be formed to a thickness sufficient to cover the inside of the facet generated at the edge of the epi layer 112. Subsequently, an ion implantation process is performed on the gate pattern on which the third gate spacer 118 ′ is formed using an ion implantation mask to form a source / drain region 120 having a deep junction. Subsequently, annealing is performed to activate the ion-implanted impurities. In the ion implantation process, the second and third gate spacers 116 ′ and 118 ′ are disproportionately under the facet because the facet of the epi layer 112 covers the edge facet sufficiently. The problem of forming source / drain regions with partial deep junctions at deeper depths can be suppressed.

Referring to FIG. 4, the wet etching is performed on the semiconductor substrate on which the source / drain 120 having the deep junction is formed, and the upper and lower portions of the exposed second gate spacer 116 ′ are overetched. ) To form a space in which the air gap 122 is to be formed. In this case, the wet etching may be performed using an etchant such as BOE (Buffered Oxide Etchant) solution, which may have an etching selectivity between the second gate spacer 116 ′ and the first and third gate spacers 110 and 118 ′. Is suitable. At this time, a portion of the second gate spacer 116 'is also removed while undercuts are formed on the upper and lower portions of the second gate spacer 116', but the capping layer 108 made of an oxide layer on the gate electrode 106 is formed. ) Are also removed together self-aligned. As a result, a space A having a predetermined shape is formed on the gate electrode 106. Therefore, since the capping layer 108 is also removed by the wet etching, the gate electrode 106 and the source / drain regions are shortened in the highly integrated semiconductor device having a fine line width.

Referring to FIG. 5, when a metal layer for silicide formation is deposited on the resultant and heat treatment is performed, polysilicon of the gate electrode 106 and the epi layer 112 and the w-laminated metal and silicide reaction occur. Subsequently, when the metal layer on the gate spacer that did not cause the silicide reaction is removed by a cleaning process, a first silicide layer 124 is formed on the gate electrode 106, and a second silicide layer is formed on the epitaxial layer 112. 126 are formed respectively. Finally, when the interlayer dielectric layer 128 (ILD) is deposited to a thickness sufficient to cover the structure formed on the semiconductor substrate 100, the air cap 122 may be formed in the undercut portion of the second gate spacer 116 ′. air gap) is stably formed.

Therefore, the structure of the FET according to the first embodiment described above includes a semiconductor substrate 100, a gate electrode 106 formed in a predetermined region of the semiconductor substrate, a first silicide layer 124 formed on the gate electrode, A first gate spacer 110 formed on the sidewalls of the gate electrode and the first silicide layer, an epitaxial layer 112 formed on the semiconductor substrate next to the gate electrode on which the first gate spacer is formed, and having a structure higher than that of the semiconductor substrate; A second gate spacer 116 ′ formed on the epi layer outside the first gate spacer, a third gate spacer 118 ′ formed on the epi layer outside the second gate spacer, and formed on a surface of the epi layer. A second silicide layer 126, an interlayer insulating film 128 covering the entire semiconductor substrate, and a first sealing layer sealed by the first and third gate spacers and the interlayer insulating film. It consists of an air gap 122 formed at the top and bottom of the two gate spacers.

<2nd Example>

The first embodiment is a method of forming an air gap on the upper and lower portions of the second gate spacer, but the FET according to the second embodiment of the present invention is a second gate spacer is formed outside the first gate spacer of the epi layer It is a method of forming an air gap by forming an edge cut surface to cover and completely removing it in a subsequent process. In describing the field-effect transistor and its manufacturing method which can reduce the parasitic capacitance according to the second embodiment of the present invention, the same parts as those of the first embodiment will be omitted so as not to be redundant and easy to understand. For the sake of brevity, the reference numerals are constructed to correspond to the first embodiment.

6 to 11 are cross-sectional views illustrating a field effect transistor and a method of manufacturing the same for reducing parasitic capacitances according to a second embodiment of the present invention.

Referring to FIG. 6, a field oxide film 202 is formed on a semiconductor substrate 200, and a gate insulating film 203, a gate electrode 206, and a cap are positioned at predetermined positions of an active region defined by the field oxide film 202. After forming the ping layer 208 in the shape of a pattern, the source / drain regions 214 (LDD) having a shallow junction with the semiconductor substrate 100 are formed using an ion implantation mask. Subsequently, the first gate spacer 210 is formed, and the epitaxial layer 212 formed by the SEG is formed to have a structure that is raised. Thereafter, a second gate spacer 216 layer covering the entire surface of the semiconductor substrate is deposited to a predetermined thickness.

Referring to FIG. 7, the second gate spacer 216 ′ is formed to sufficiently cover the edge facet of the epi layer 212 by performing dry etching on the resultant. Such dry etching can be formed by appropriately adjusting the mixing ratio and etching time of the etching gas. Therefore, the second gate spacer 216 ′ is configured to sufficiently cover the edge face of the epi layer 212 so that a deep junction may be disproportionately formed when forming a source / drain region having a subsequent deep junction. It can be suppressed.

Referring to FIG. 8, a third gate spacer is formed on the entire surface of the semiconductor substrate on which the second gate spacer 216 'is formed by using a nitride film having an etching selectivity different from that of the oxide film, which is the second gate spacer 216'. (218) is deposited to a certain thickness.

Referring to FIG. 9, a dry etch is performed on the insulating layer 218 for forming the third gate spacer to cover an outer upper portion of the first gate spacer 210, and a lower portion of the second gate spacer is formed on the insulating layer 218. A third gate spacer 218 'having a structure mounted on the 216' is formed. Thereafter, the pattern with the gate electrode is implanted with an ion implantation mask to form a source / drain region 220 having a deep junction. At this time, after performing the heat treatment process for activation under the influence of the second gate spacer 216 ′, the deep junction is not disproportionately formed.

Referring to FIG. 10, the second gate spacer 216 may be wet-etched using an etching selectivity of the second gate spacer 216 ′ and the first and third gate spacers 210 and 218 ′. Remove ') completely. At this time, since the capping layer 208 on the gate electrode 206 is also an oxide film, the capping layer 208 is removed from the gate electrode 206 B in a self-aligned manner to suppress defects in which the gate electrode 206 and the source / drain regions are disconnected. Perform the function. In addition, the epitaxial layer 212 of the third gate spacer 218 ′ and the raised structure maintain a constant gap, so that the silicide layer is also formed on the edge facet of the epitaxial layer 212 in a subsequent silicide layer forming process. Formed to reduce the resistance of the semiconductor element. At the same time, encroachment by the second silicide layer (226 of FIG. 10) formed in the source / drain region occurs because the silicide reaction occurs relatively less than the other epitaxial epitaxial layer 212 at the edge of the epi layer 212. The advantage of preventing the phenomenon also occurs.

Referring to FIG. 10, a metal layer for forming a silicide layer is laminated on the resultant, and a heat treatment is performed to form a first silicide layer 224 on the gate electrode 206 and a second silicide layer 226 on the epitaxial layer 212. Form each. Finally, an air gap 222 is formed in a stable shape by depositing the interlayer insulating layer 228 having a thickness that can completely cover the structure formed on the semiconductor substrate 100. Parasitic capacitance existing between the source / drain and the gate electrode can be reduced.

Therefore, the structure of the FET formed by the second embodiment of the present invention described above has a semiconductor substrate 200, a gate electrode 206 formed in a predetermined region of the semiconductor substrate, and a first silicide formed on the gate electrode. And an epitaxial layer formed on the semiconductor substrate next to the gate electrode on which the gate electrode and the first silicide layer are formed, and the semiconductor substrate next to the gate electrode on which the first gate spacer is formed. 212, a third gate spacer 218 ′ formed outside the first gate spacer and having a lower portion of the first gate spacer that does not touch the epi layer, a second silicide layer formed on the epi layer; 226, an interlayer insulating film 228 covering the entire resultant product and a third gate spacer that is sealed by the interlayer insulating film and is over an edge of the epi layer. It is made of an air cap (222, Air gap).

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, first, a primary gate spacer can be formed and an air gap can be stably formed on the side thereof to implement a semiconductor device capable of reducing parasitic capacitance.

Second, a source / strain region (LDD) having a shallow junction can be realized while solving the problem of disparity in the junction depth caused by the edge face of the epi layer formed by the SEG process.

Third, in the wet etching process for removing the second gate spacer, the capping layer on the gate electrode is also removed, thereby solving the problem of shorting the gate and source / drain regions in a semiconductor device having a fine pattern. Process margin can be secured.

Fourth, it is possible to suppress the encroachment problem caused by the second silicide layer grown on the edge cut surface of the epi layer in the silicide reaction process by separating the third gate spacer and the cut surface of the epi layer at regular intervals.

Claims (12)

Semiconductor substrates; A gate electrode formed in a predetermined region of the semiconductor substrate; A first silicide layer formed on the gate electrode; A first gate spacer disposed on sidewalls of the gate electrode and the first silicide layer; An epi layer formed on the semiconductor substrate next to the gate electrode on which the first gate spacer is formed to have a structure higher than that of the semiconductor substrate; A second gate spacer formed on the epi layer outside the first gate spacer; A third gate spacer formed on the epi layer outside the second gate spacer; A second silicide layer formed on the epi layer surface; An interlayer insulating film (ILD) covering the entire semiconductor substrate; And And parasitic capacitances of the first and third gate spacers and air gaps formed at upper and lower portions of the second gate spacers sealed by the interlayer insulating layer. The method of claim 1, And the first and third gate spacers are formed of a nitride film (SiN). The method of claim 1, The second gate spacer is a field effect transistor that can reduce the parasitic capacitance, characterized in that the oxide film (SiO ₂ ) material. A gate electrode on the semiconductor substrate where device isolation has been performed. A first process of forming a gate pattern having a capping layer formed on the gate electrode and a first gate spacer surrounding sidewalls of the gate electrode and the capping layer; A second step of laminating an epitaxial layer having a structure raised on the surface of the semiconductor substrate except for the gate pattern; A third process of depositing and etching second and third gate spacer insulating films on the resultant layer of epitaxial layers to form second and third gate spacers; A fourth process of removing the capping layer and performing wet etching to overetch the second gate spacer; A fifth process of forming first and second silicide layers on the epitaxial layer and on the gate electrode from which the capping layer is removed; And And a sixth step of forming an interlayer insulating film (ILD) covering said resultant. The method of claim 4, wherein The thicknesses of the second and third gate spacers of the third process may be such that the thickness of the parasitic capacitance may be reduced to sufficiently cover the facet of the epi layer in a subsequent etching process. Manufacturing method. The method of claim 4, wherein The wet etching of the fourth process may be performed by using a difference between an etching selectivity of the second gate spacer and the first and third gate spacers, and the parasitic capacitance may be reduced. Semiconductor substrates; A gate electrode formed in a predetermined region of the semiconductor substrate; A first silicide layer formed on the gate electrode; A first gate spacer disposed on sidewalls of the gate electrode and the first silicide layer; An epi layer formed on the semiconductor substrate next to the gate electrode on which the first gate spacer is formed to have a structure higher than that of the semiconductor substrate; A third gate spacer configured outside the first gate spacer and configured such that a lower portion of the first gate spacer does not contact the epitaxial layer; A second silicide layer formed on the epi layer; An interlayer insulating film (ILD) covering the entire resultant product; And And a parasitic capacitance that is closed by the interlayer insulating layer and has an air gap formed under a third gate spacer on an edge of the epitaxial layer. The method of claim 7, wherein The epi layer has a shallow junction source / drain region and a deep junction source / drain region characterized in that the parasitic capacitance can reduce the field effect transistor. The method of claim 7, wherein The first and third gate spacers are field effect transistors that can reduce the parasitic capacitance, characterized in that the nitride film made of a material. A gate electrode on the semiconductor substrate where device isolation has been performed. A first process of forming a gate pattern having a capping layer formed on the gate electrode and a first gate spacer surrounding sidewalls of the gate electrode and the capping layer; A second step of stacking an epitaxial layer having a structure raised on a surface of the semiconductor substrate on which the gate pattern is formed; A third gate spacer which covers the edge face of the epi layer and forms a second gate spacer having a lower formation height than the first gate spacer by depositing and etching an insulating film for a second gate spacer on a resultant layer of the epi layer; fair; Depositing and etching a third gate spacer insulating layer on the resultant to form a third gate spacer on the sidewall of the first gate spacer and on the second gate spacer; A fifth process of performing wet etching to remove the capping layer and the second gate spacer; A sixth step of forming first and second silicide layers on the epitaxial layer and on the gate electrode from which the capping layer is removed; And And a seventh step of forming an interlayer insulating film (ILD) covering the resultant. The method of claim 10, After forming the third gate spacer of the fourth process, a parasitic capacitance is further performed to form a source / drain region having a deep junction with the epi layer using the gate pattern as an ion implantation mask. A method for manufacturing a field effect transistor that can be reduced. The method of claim 10, The wet etching of the fifth process may be performed by using a difference between etching selectivities of the second gate spacer and the first and third gate spacers, and the parasitic capacitance may be reduced.