KR100412144B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100412144B1 KR100412144B1 KR10-2002-0027003A KR20020027003A KR100412144B1 KR 100412144 B1 KR100412144 B1 KR 100412144B1 KR 20020027003 A KR20020027003 A KR 20020027003A KR 100412144 B1 KR100412144 B1 KR 100412144B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 238000001039 wet etching Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 반도체 기판상에 트렌치와 트렌치 절연막을 형성하는 단계; 상기 트렌치 절연막이 형성된 기판상에 게이트를 형성하는 단계; 상기 트레치의 측벽에 모우트를 형성하는 단계; 상기 게이트와 트렌치 사이의 기판상에 선택적 에피택셜 성장층을 형성하는 단계; 및 상기 게이트 양측면 아래의 기판 및 선택적 에피택셜 성장층에 소정의 이온을 주입하여 확산층을 형성하는 단계를 포함하며, SOI 웨이퍼를 이용함으로써 고집적소자 제조시 게이트 길이 감소에 따른 접합누설전류 문제를 해결할 수 있으며, 트렌치 측벽에 모우트를 형성한 후에 실리콘 측면성장을 유발하여 트렌치 절연막 상부에까지 확산층을 확대하여 트렌치 설계시 확산층 영역을 감소시킬 수 있어 반도체 소자의 집적도를 대폭적으로 향상시킬 수 있는 효과가 있는 것이다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a trench and a trench insulating film on a semiconductor substrate; Forming a gate on the substrate on which the trench insulating film is formed; Forming a moat on a sidewall of the trench; Forming a selective epitaxial growth layer on the substrate between the gate and the trench; And forming a diffusion layer by implanting predetermined ions into the substrate and the selective epitaxial growth layer under both sides of the gate, and using a SOI wafer to solve the problem of junction leakage current due to the reduction of the gate length in the fabrication of a high density device. In addition, after forming the trench on the sidewalls of the trench, silicon side growth may be induced to extend the diffusion layer to the upper portion of the trench insulating layer, thereby reducing the diffusion layer region in the trench design, thereby greatly improving the integration degree of the semiconductor device. .
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는 실리콘 온 인슐레이터 웨이퍼의 확산층 영역을 트렌치 상부에까지 확대하여 소자의 고집적화를 이룰 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of achieving high integration of a device by extending a diffusion layer region of a silicon on insulator wafer to an upper portion of a trench.
일반적으로 반도체 소자가 고집적화가 될수록 게이트 길이가 감소하고, 이에 따른 트랜지스터의 단채널 효과를 줄이기 위하여 소오스/드레인의 확산층의 접합깊이 감소가 수반되고 있다. 그렇지만, 확산층의 접합깊이가 감소함에 따라 접합누설전류가 증가되는 문제점이 고집적소자의 제조에 큰 관건이 되고 있다. 더욱이, 실리사이드 형성이 필수적인 로직 소자에 있어서는 더욱더 그러하다.In general, as semiconductor devices become more integrated, gate lengths decrease, and accordingly, in order to reduce short channel effects of transistors, a junction depth of a source / drain diffusion layer is accompanied. However, the problem that the junction leakage current increases as the junction depth of the diffusion layer decreases has become a key to the fabrication of highly integrated devices. Moreover, this is even the case for logic devices where silicide formation is essential.
종래 이러한 문제점을 해결하기 위하여, 초고집적소자에서는 절연막 위에 실리콘 단결정층이 있는 구조의 웨이퍼, 즉 실리콘 온 인슐레이터(Silicon On Insulator; 이하, SOI라 약칭함) 웨이퍼를 이용하여 낮은 확산층의 접합깊이에 따른 문제점을 해결하였다. 이러한 SOI 웨이퍼는 회로를 형성하는 기판 표면과 하층 사이에 얇은 절연막층이 매립되어 있기 때문에 기생 용량(parasitic capacitance)이 감소되어 소자의 성능을 높일 수 있는 특징이 있다. 또한, 같은 전압에서 동작 속도를 빠르게 할 수 있고, 같은 속도에서 전원 전압을 낮게 할 수 있는 웨이퍼이다.In order to solve such a problem in the related art, in the ultra-high density device, a wafer having a silicon single crystal layer on the insulating layer, that is, a silicon on insulator (hereinafter referred to as SOI) wafer, is used according to the junction depth of the low diffusion layer. The problem was solved. Since the SOI wafer has a thin insulating layer interposed between the substrate surface and the lower layer forming the circuit, parasitic capacitance is reduced, thereby improving the performance of the device. In addition, the wafer can be made faster at the same voltage, and lower the power supply voltage at the same speed.
그러나, 종래 기술에 따른 반도체 소자의 제조방법에 있어서는 다음과 같은 문제점이 있다.However, the manufacturing method of the semiconductor device according to the prior art has the following problems.
종래 기술에 있어서, 게이트 길이 감소에 따른 접합누설전류 문제를 어느 정도 해결했다 하더라도 콘택형성 영역 확보를 위한 소오스/드레인 영역이 줄어들지 않아 소자의 고집적화에 큰 장애가 되고 있는 실정이다. 따라서, 게이트 길이의 감소에도 불구하고 소자의 집접화가 증가하지 않는 문제점이 있다.In the prior art, even if the problem of junction leakage current due to the reduction of the gate length is solved to some extent, the source / drain region for securing the contact formation region is not reduced, which is a serious obstacle to high integration of the device. Therefore, there is a problem that the device integration does not increase despite the decrease in the gate length.
이에, 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 트렌치 측벽에 모우트(moat)를 형성한 후에 실리콘 측면성장을 유발하여 트렌치 절연막 상부로 확산층을 확대함으로써 트랜지스터 설계시 확산층 영역을 그만큼 줄일 수 있어 고집적화를 이룰 수 있는 반도체 소자의 제조방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-described problems in the prior art, an object of the present invention by forming a moat on the trench sidewalls to cause silicon lateral growth to expand the diffusion layer over the trench insulating film The present invention provides a method of manufacturing a semiconductor device capable of achieving high integration by reducing the diffusion layer region in transistor design.
도 1 내지 도 5는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1 to 5 are cross-sectional views for each process for explaining a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100; 반도체 기판 102,106; 실리콘층100; Semiconductor substrates 102,106; Silicon layer
104; 실리콘옥사이드층 150; 트렌치104; Silicon oxide layer 150; Trench
200,200a; 트렌치 절연막 300; 게이트200,200a; A trench insulating film 300; gate
350; LDD350; LDD
400a,400b; 선택적 에피택셜 성장층(Selective Epitaxial growth layer)400a, 400b; Selective Epitaxial Growth Layer
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은, 반도체 기판상에 트렌치와 트렌치 절연막을 형성하는 단계; 상기 트렌치 절연막이 형성된 기판상에 게이트를 형성하는 단계; 상기 트레치의 측벽에 모우트를 형성하는 단계; 상기 게이트와 트렌치 사이의 기판상에 선택적 에피택셜 성장층을 형성하는 단계; 및 상기 게이트 양측면 아래의 기판 및 선택적 에피택셜 성장층에 소정의 이온을 주입하여 확산층을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a trench and a trench insulating film on a semiconductor substrate; Forming a gate on the substrate on which the trench insulating film is formed; Forming a moat on a sidewall of the trench; Forming a selective epitaxial growth layer on the substrate between the gate and the trench; And implanting predetermined ions into the substrate and the selective epitaxial growth layer under both sides of the gate to form a diffusion layer.
본 발명에 의하면 확산층 영역을 트렌치 상부에까지 확대할 수 있어 소자의 고집적화를 이룰 수 있게 된다.According to the present invention, the diffusion layer region can be extended to the upper portion of the trench, thereby achieving high integration of the device.
이하, 본 발명에 따른 반도체 소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.1 to 5 are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 제조방법은, 도 1에 도시된 바와 같이, 실리콘(Si) 등의 반도체층(102)(106) 사이에 실리콘옥사이드층(104)이 매립되어 있는 반도체 기판(100) 표면을 선택적으로 제거하여 트렌치(150)를 형성한다. 그다음, 상기 트렌치(150)의 매립과 평탄화를 통하여 트렌치 절연막(200)을 형성한다.In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1, a semiconductor substrate 100 having a silicon oxide layer 104 buried between semiconductor layers 102 and 106, such as silicon (Si). The surface is selectively removed to form the trench 150. Next, the trench insulating layer 200 is formed by filling and planarizing the trench 150.
이때, 후속하는 모우트(Moat) 형성시 식각되는 양을 고려하여 상기 트렌치 절연막(200)은 상기 기판(100) 표면으로부터 1,000Å ~ 2,000Å 높이로 형성한다.In this case, the trench insulating layer 200 may be formed to have a height of 1,000 Å to 2,000 Å from the surface of the substrate 100 in consideration of the amount of etching during subsequent moat formation.
이어서, 도 2에 도시된 바와 같이, 상기 트렌치 절연막(200)이 형성된 기판(100)상에 게이트 산화막, 폴리실리콘 등의 전극층 및 게이트 스페이서를 포함한 게이트(300)를 형성한다. 한편, 상기 게이트(300) 양측면 아래의 기판(100)에 소정의 이온을 주입하여 LDD(350;Lightly Doped Drain)를 형성한다.Next, as illustrated in FIG. 2, a gate 300 including a gate oxide layer, an electrode layer such as polysilicon, and a gate spacer is formed on the substrate 100 on which the trench insulating layer 200 is formed. Meanwhile, a predetermined ion is implanted into the substrate 100 under both sides of the gate 300 to form a lightly doped drain (LDD) 350.
그런다음, 도 3에 도시된 바와 같이, 상기 트렌치 절연막(200)을 일부 제거하여 상기 트렌치(150) 측벽에 모우트(A)를 형성한다. 상기 모우트(A)를 형성하는 단계는 HF와 BOE(Buffer Oxide Etchant)중 어느 하나를 이용한 습식각 공정으로 상기 트렌치 절연막(200)을 등방성 식각한다. 이때, 상기 습식각 공정은 식각되어 일부가 제거된 트렌치 절연막(200a) 표면 높이가 상기 기판(100)의 표면 높이와 같아질 때까지 진행한다.Next, as shown in FIG. 3, the trench insulating layer 200 is partially removed to form the moat A on the sidewall of the trench 150. The forming of the moat (A) isotropically etches the trench insulating layer 200 by a wet etching process using any one of HF and BOE (Buffer Oxide Etchant). In this case, the wet etching process is performed until the surface height of the trench insulating layer 200a, which is partially removed, is equal to the surface height of the substrate 100.
이어서, 도 4에 도시된 바와 같이, 상기 게이트(300) 상부와, 상기 게이트(300) 및 트렌치(150) 사이의 기판(100)상에 선택적 에피택셜 성장층 1(400a)과 선택적 에피택셜 성장층 2(400b)를 각각 형성한다. 특히, 상기 게이트(300) 및 트렌치(150) 사이의 선택적 에피택셜 성장층 2(400b)는 상기 트렌치(150) 측벽에 노출된 실리콘층(106) 등을 핵생성 부위로 하여 측면성장을 유도하여 형성한다. 상기 선택적 에피택셜층(400a)(400b)은 SiH2Cl2와 HCl를 이용한 화학기상증착법으로 약 300Å ~ 1,000Å 두께로 형성한다. 상기와 같은 공정에 의해서 상기 게이트(300) 및 트렌치(150) 사이의 선택적 에피택셜 성장층 2(400b)는 상기트렌치 절연막(200a) 상부 일부에까지 형성된다.Subsequently, as shown in FIG. 4, selective epitaxial growth layer 1 (400a) and selective epitaxial growth on the substrate 100 between the gate 300 and between the gate 300 and the trench 150. Layer 2 400b is formed, respectively. In particular, the selective epitaxial growth layer 2 400b between the gate 300 and the trench 150 induces lateral growth by using the silicon layer 106 exposed on the sidewall of the trench 150 as a nucleation site. Form. The selective epitaxial layers 400a and 400b are formed to have a thickness of about 300 kPa to 1,000 kPa by chemical vapor deposition using SiH 2 Cl 2 and HCl. By the above process, the selective epitaxial growth layer 2 400b between the gate 300 and the trench 150 is formed on a portion of the upper portion of the trench insulating layer 200a.
한편, 상기 선택적 에피택셜 성장층(400a)(400b)을 형성하는 단계 이전에, 상기 기판(100)상에 원할한 선택적인 증착을 위하여 전처리로서 수소의 환원성 분위기에서 800℃ ~ 900℃ 온도로 약 1분 ~ 10분 동안 열처리하는 단계를 진행할 수 있다.On the other hand, before the step of forming the selective epitaxial growth layer (400a, 400b), about 800 ℃ ~ 900 ℃ temperature in a reducing atmosphere of hydrogen as a pretreatment for the desired selective deposition on the substrate 100 The heat treatment may be performed for 1 minute to 10 minutes.
그다음, 도 5에 도시된 바와 같이, 상기 게이트(300) 양측면 아래의 기판(100)에 확산층(500)이 형성될 수 있도록 상기 게이트(300) 및 트렌치(150) 사이의 선택적 에피택셜 성장층 2(400b)에 소정의 이온을 주입한다. 그러면, 상기 선택적 에피택셜 성장층 2 (400b)도 확산층 역할을 하게 됨으로써 확산층 영역이 상기 트렌치 절연막(200a) 상부 일부에까지 확대되는 결과가 된다.Next, as shown in FIG. 5, the selective epitaxial growth layer 2 between the gate 300 and the trench 150 so that the diffusion layer 500 may be formed on the substrate 100 under both sides of the gate 300. Predetermined ions are implanted into 400b. Then, the selective epitaxial growth layer 2 400b also serves as a diffusion layer, which results in the diffusion layer region being extended to a part of the upper portion of the trench insulating layer 200a.
이후, 예정된 후속 공정을 진행하여 반도체 소자를 완성한다.Thereafter, a predetermined subsequent process is performed to complete the semiconductor device.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method according to the present invention has the following effects.
본 발명에 있어서는, SOI 웨이퍼를 이용함으로써 고집적소자 제조시 게이트 길이 감소에 따른 접합누설전류 문제를 해결할 수 있으며, 트렌치 측벽에 모우트를 형성한 후에 실리콘 측면성장을 유발하여 트렌치 절연막 상부에까지 확산층을 확대하여 트렌치 설계시 확산층 영역을 감소시킬 수 있다. 따라서, 본 발명에 의하면 반도체 소자의 집적도를 대폭적으로 향상시킬 수 있는 효과가 있다.In the present invention, by using the SOI wafer, it is possible to solve the problem of junction leakage current due to the reduction of the gate length during the fabrication of high-integration devices, and to increase the diffusion layer to the upper portion of the trench insulation layer by causing the silicon side growth after forming the trench on the trench sidewalls. Thereby reducing the diffusion layer region in the trench design. Therefore, according to the present invention, there is an effect that can greatly improve the degree of integration of the semiconductor device.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990073748A (en) * | 1998-03-02 | 1999-10-05 | 윤종용 | How to Form Trench Isolation in Integrated Circuits |
| KR20000075409A (en) * | 1999-05-20 | 2000-12-15 | 윤종용 | Method of Forming T-Shape Isolation Layer, Method of Elevated Salicide Source/Drain Region Using thereof and Semiconductor Device Having T-Shape Isolation Layer |
| KR20000075278A (en) * | 1999-05-31 | 2000-12-15 | 윤종용 | A semiconductor device comprising source/drain area extruded over a field area and method for forming the same |
| KR20010068649A (en) * | 2000-01-07 | 2001-07-23 | 박종섭 | Method for isolating semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990073748A (en) * | 1998-03-02 | 1999-10-05 | 윤종용 | How to Form Trench Isolation in Integrated Circuits |
| KR20000075409A (en) * | 1999-05-20 | 2000-12-15 | 윤종용 | Method of Forming T-Shape Isolation Layer, Method of Elevated Salicide Source/Drain Region Using thereof and Semiconductor Device Having T-Shape Isolation Layer |
| KR20000075278A (en) * | 1999-05-31 | 2000-12-15 | 윤종용 | A semiconductor device comprising source/drain area extruded over a field area and method for forming the same |
| KR20010068649A (en) * | 2000-01-07 | 2001-07-23 | 박종섭 | Method for isolating semiconductor devices |
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