KR20000050293A - Semiconductor device for high speed data dutput - Google Patents

Abstract

PURPOSE: A semiconductor device for outputting a high-speed data is provided to prevent an overlap between a latch data and a transmission control signal in both worst and best conditions by suitably combining a data patch signal and a level shifter enable signal and by generating the transmission control signal, and to obtain a stable data outputting. CONSTITUTION: A main sense amplifier(100) senses a data read from a memory cell and outputs a sensing data. An output driver(400) outputs a data. A level shifter(200) converts a level of the sensing data and outputs a level shifting data. A data output buffer(300) latches the level shifting data and outputs the latched data through the output driver(400) in response to a data patch signal, a first enable signal and an output enable signal. A self-reset controller(500) generates first and second enable signals for controlling the main sense amplifier(100) and the level shifter(200) so that the sensing data is self-latched and self-reset in response to the first control signal and the level shifting data, and provides the second enable signal to the data output buffer(300) to transmit the self-latched data.

Description

Semiconductor device for high speed data dutput

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed data output semiconductor device, and more particularly, to a high speed data output semiconductor device capable of outputting data at high speed by having a salp latch and a reset function.

FIG. 1 is a block diagram illustrating a conventional high speed data output semiconductor device. As illustrated in FIG. 1, a data read from a memory cell (not shown) is sensed and amplified, and sensing data SAS and SASB are amplified. A level shifter 20 for level converting the sensing data SAS and SASB from the main sense amplifier 10 and outputting level shifting data DATAA and DATAAB; And latching the level shifting data DATAA and DATAAB to the first latch, and latching the data latched to the first latch to the second latch in response to the data patch signal KDATAP. The data output buffer 30 outputs the data latched to the second latch through the output driver 40 in response to the output enable signal OE, the first control signal MSAENP and the level shifting data First and in response to DATAA, DATAAB) The second enable signals MSAEN and KDPRECB are generated, and the data sensed by the main sense amplifier 10 by the first and second enable signals MSAEN and KDPRECB are stored in the first latch of the output buffer 30. And a salp reset control unit 50 for controlling the main sense amplifier 10 and the level shifter 20 so that the sap reset is performed immediately after the rat latch.

Referring to FIG. 2, the data output buffer 30 includes inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, INV8, INV9, and INV10, and PMOS transistors MP1, MP2, MP3, and the like. MP4, MP5, MP6, MP7, MP8, NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, and NAND gates ND1, ND2, and the inverter INV5 includes data. Invert the patch signal KDATAP to output the first transmission control signal KDATAB, and the inverter INV6 is coupled to invert the first transmission control signal KDATAB to output the second transmission control signal KDATA. .

The inverter pairs INV3 and INV4 and the inverter pairs INV7 and INV8 form a first latch 31 and a second latch 32, respectively.

In the semiconductor device for high-speed data output having the above-described configuration, the level shifting data DATAA and DATAAB in the previous cycle are held latched in the first latch 31 and then transferred by the data fetch signal KDATAP. And the transfer control signal KDATA are transferred to the second latch 32 and latched in the current cycle in which they are active at logic "low" and logic "high" levels, respectively. The data latched in the second latch 32 is an output. It is output in response to the enable signal OE and is output to an external data input / output (I / O) pad via an off-chip driver, that is, an output driver 40.

Meanwhile, the first latch 31 is self-reset as the main sense amplifier 10 and the level shifter 20 are disabled immediately after the latch data DATAB and DATABB are transferred to the second latch 32.

As described above, the conventional technology has a number of clock latches and a reset function to reduce the number of clocks so that data can be output at a high speed without limiting cycle time, and in particular, the level shifting data DATAA and DATAAB are developed. The pulse widths of the first enable signal MSAEN and the second enable signal KDPRECB are adjusted according to the degree, and thus stable and fast operation can be performed even under various conditions such as temperature, process, and power supply voltage. .

3 is a waveform diagram showing simulation results when a supply voltage VDD is set to 3.1 V and a temperature Temp is set to 80 ° C. and a worst case model parameter is applied to a conventional high speed data output semiconductor device. to be.

FIG. 4 is a waveform diagram showing simulation results when a supply voltage VDD is set to 3.6 V and a temperature Temp is set to 10 ° C. and a model parameter of the best condition is applied to a conventional high speed data output semiconductor device. .

As can be seen from the waveform diagram, in the worst condition, the above-described data output operation is normally performed every clock cycle, but in the best condition, the transition speed of all signals is increased. In particular, as shown in Fig. 4, when the transmission speed of the latch data DATAB and DATABB is much faster than the transmission speed of the first transmission control signal KDATA, the first transmission control signal KDATA is logic "high". During the operation, the latch data DATAB and DATABB are transferred to the second latch 32 of the next stage two times, thereby causing a data output failure.

In general, since the transmission control signal KDATA is generated in conjunction with tKQ, a transistor having a larger size than that of other paths is used in the transmission control signal KDATA generation path as much as possible. Therefore, the transmission control signal KDATA has a small speed difference between the worst case condition and the best condition. Where tKQ represents the data output valid time for the clock. In other words, the first and second transfer control signals KDATAB and KDATA caused by the data patch signal KDATAP generated from the clock XCK are activated to latch the data latched in the first latch 31 to the second latch 32. ) And the effective time until read out of the chip via the off-chip driver 40.

On the other hand, since the latch data DATAB and DATABB come through a longer data path, the speed difference between the worst condition and the best condition increases accordingly, thereby causing the aforementioned data output failure problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and to provide a semiconductor device for high-speed data output that can prevent the overlap of the data signal and the transmission control signal in the current cycle.

In order to achieve the above object, a feature of the semiconductor device for high-speed data output according to the present invention is a high-speed sensor including a main sense amplifier for sensing data read from a memory cell and outputting sensing data, and an output driver for outputting data. A semiconductor device for data output, comprising: level shifting means for level converting sensing data from the main sense amplifier to output level shifting data; A first latch and a second latch, the second latch latching the level shifting data to the first latch, and logically combining the data patch signal and the first enable signal to the third latched data to the first latch. A data output buffering means for latching with two latches and outputting data latched to the second latch through the output driver in response to an output enable signal; And first and second enable signals for controlling the main sense amplifier and the level shifting means such that the sensing data is salph reset after being sense latched to the data output buffering means in response to a first control signal and the level shifting data. And self reset control means for supplying the second enable signal to the data output buffering means such that data latched to the first latch is transmitted to the second latch.

1 is a block diagram for explaining a conventional high speed data output semiconductor device.

FIG. 2 is a detailed circuit diagram illustrating the data output buffer of FIG. 1. FIG.

3 is a waveform diagram showing simulation results when applying the worst case model parameter to the apparatus of FIG. 1; FIG.

FIG. 4 is a waveform diagram showing simulation results when applying model parameters of the best condition to the apparatus of FIG. 1; FIG.

5 is a block diagram for explaining a high speed data output semiconductor device according to the present invention;

FIG. 6 is a detailed circuit diagram illustrating the level shifter of FIG. 5. FIG.

FIG. 7 is a detailed circuit diagram illustrating a data output buffer and an output driver of FIG. 5. FIG.

FIG. 8 is a detailed circuit diagram illustrating the self reset controller of FIG. 5. FIG.

FIG. 9 is a waveform diagram showing simulation results when the model parameter is the best condition for the apparatus of FIG. 5; FIG.

* Explanation of symbols for the main parts of the drawings

100; Main sense amplifier 200; Level shifter

300; Data output buffer 301; First latch

302; Second latch 400; Off-chip driver

500; Self reset control unit

Hereinafter, one preferred embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a block diagram illustrating a semiconductor device for high-speed data output according to an embodiment of the present invention. As illustrated in FIG. 5, a sensing data SAS and SASB are output by sensing data read from a memory cell (not shown). A level shifter 200 for outputting the level shifting data DATAA and DATAAB by level converting the main sense amplifier 100, an output driver 400 for outputting data, sensing data SAS and SASB, and a level The system latches the shifting data DATAA and DATAAB, and outputs the shift latched data to the output driver 400 in response to the data patch signal KDATAP, the first enable signal MSAEN, and the output enable signal OE. The main sense to sense the data output buffer 300, the first control signal (MSAENP) and the sensing data (SAS, SASB) in the data output buffer 300 after the sampling is latched in response to the level shifting data Amplifier 100 and Level Generates first and second enable signals MSAEN and KDPRECB for controlling the printer 200, and transmits the second enable signal KDPRECB to the data output buffer 300 for transmission of the salp latched data. It consists of a self-resetting control part 500 which supplies to.

The first control signal MSAENP is a clock signal which is a basis for generating the first enable signal MSAEN for enabling the main sense amplifier 100 and is a signal that is always generated during a cell data read operation.

The data patch signal KDATAP is a pure pulse signal generated from an external clock and is usually made through the fastest path.

As shown in FIG. 6, the level shifter 100 includes a PMOS transistor MP1 having a source coupled to a power supply voltage source and driven in response to a second enable signal KDPRECB, and a source having a PMOS transistor MP1. Between PMOS transistors MP2 and MP3 commonly coupled to the drain of the PMOS transistors MP2 and MP3 and driven by the output data SAS and SASB of the main sense amplifier 10 and between the drain and ground of the pair of PMOS transistors MP2 and MP3. Respectively coupled to the NMOS transistors MN1 and MN2 having a gate cross-coupled to the drains of the PMOS transistors MP2 and MP3, and an output node that is a connection point between the PMOS transistor MP2 and the NMOS transistor MN1. N1) and PMOS transistors MP3 and NMOS transistor MN2, which are coupled between output node N2 and ground, respectively, in response to the second enable signal KDPRECB. NMOS transistor to pull down N2) to ground level It consists of the emitter (MN3, MN4).

As shown in FIG. 7, the data output buffer includes inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, INV8, and INV9, and PMOS transistors MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, NMOS transistors MN5, MN6, MN7, MN8, MN9, MN10, and NAND gates ND1, ND2, and ND3.

The inverter pairs INV3 and INV4 and the inverter pairs INV6 and INV7 form a first latch 301 and a second latch 302, respectively.

The NAND gate ND1 negatively multiplies the data patch signal KDATAP and the second enable signal KDPRECB to generate a transmission control signal KDATAB, and the inverter INV5 inverts the transmission control signal KDATAB. To generate the transmission control signal KDATA.

As shown in FIG. 7, the off-chip driver 400 includes an NMOS transistor MN11 for pulling up the output node N3 to a power supply voltage level in response to an output signal DOU of the data output buffer 300; The NMOS transistor MN12 pulls down the output node N3 to the ground level in response to the output signal DOD of the data output buffer 300.

As shown in FIG. 8, the self-resetting controller 500 may include a NOR gate NOR1 that performs an NOR operation on the level shifting data DATAA and DATAAB, an output signal of the NOR gate NOR1, and a first control signal MSAENP. NAND gate ND4, which is an AND, and an inverter INV10 that outputs the first enable signal MSAEN by inverting the output signal of the NAND gate ND4, and an output signal of the inverter INV10 by inverting It consists of multi-stage inverters INV11, INV12, and INV13 that output two enable signals KDPRECB.

Referring to the configuration described above with reference to the operation of the semiconductor device for high-speed data output according to the present invention.

Referring to FIG. 5, a cell data reading operation for outputting data stored in a memory cell (not shown) will be briefly described. First, when the first control signal MSAENP is activated to a logic " high " level, The reset controller 500 generates a first enable signal MSAEN of a logic "high" level and supplies it to the main sense amplifier 100, and generates a second enable signal KDPRECB of a logic "low" level. The level shifter 200 and the data output buffer 300 are supplied. Next, when the first enable signal MSAEN is activated with a logic “high” level, the main sense amplifier 100 senses data read from a memory cell (not shown) at a designated address and amplifies to a predetermined level. The resulting sensing data SAS and SASB are output. The sensing data SAS and SASB are signals that maintain a level of about 1V.

In this state, when the second enable signal KDPRECB is activated at a logic "low" level, the level shifter 200 sets the logic level of the sensing data SAS and SASB to a complementary metal oxide silicon (CMOS) level. After converting, the resultant level shifting data DATAA and DATAAB are subjected to a latch latch on the data output buffer 300 and fed back to the reset reset controller 500. The second enable signal KDPRECB is a signal obtained by delaying the first enable signal MSAEN by a predetermined time.

According to an exemplary embodiment of the present invention, the data output buffer 300 serves to patch data latched in a previous cycle in a current cycle, and provides a second enable signal KDPRECB from the self reset controller 500. And, when both the second enable signal KDPRECB and the data fetch signal KDATAP are activated to a logic " high " level, they transmit the latch latched data to the next latch, and then the output enable signal OE Outputs the latched data when activated to a logic "high" level. The output enable signal OE is a signal from the output enable buffer and is set to a logic "high" level in the cell data read operation.

In addition, the data output buffer 300 has a latency and is configured to output latched data after one cycle. However, the data output buffer 300 has a standby time of two or more waiting times and two or more cycles of latched data. It can be configured to output after a cycle. This method of adjusting the data output timing is generally a well known technique.

Next, the off-chip driver 400 is driven by the output signals DOU and DOD of the data output buffer 300 to output the final data to the outside of the chip through the data input / output (I / O) pads.

Meanwhile, as described above, the level shifting data DATAA and DATAAB have different logic levels during the cell data reading operation. When the level shifting data DATAA and DATAAB are fed back to the self reset controller 200, In response, the self reset controller 200 generates the first enable signal MSAEN of logic "low" level and the second enable signal KDPRECB of logic "high" level to generate the main sense amplifier 100 and the level shifter. Supply to 200. Accordingly, the main sense amplifier 100 and the level shifter 200 are disabled, respectively, and the data output buffer 300 is sequentially reset.

Referring to FIG. 6, the operation of the level shifter 200 will be described in more detail. First, since the second enable signal KDPRECB is activated at a logic " low " level during the cell data read operation, the PMOS transistor MP1 is used. Is turned on. The PMOS transistor MP2 and the PMOS transistor MP3 are turned on according to the sensing data SAS and SASB from the main sense amplifier 100. For example, when the sensing data SAS is at a logic "high" level, the PMOS transistor MP2 is turned off while the PMOS transistor MP3 is turned on, while the NMOS transistor MN1 is sequentially turned on, while the NMOS transistor MPN is turned on. The MOS transistor MN2 is turned off, and thus the level shifter 200 converts the sensing data SAS and SASB into a CMOS level, and level shifting the logic " low " level through the output nodes N1 and N2. Generates data DATAB and level shifting data DATAA of logic "high" level, respectively.

On the other hand, as described above, the second enable signal KDPRECB is at a logic " high " level after the level shifting data DATAB is salph latched in the data output buffer 300. FIG. At this time, the NMOS transistors MN3 and MN4 coupled to the output nodes N1 and N2 are turned on, and the potentials of the output nodes N1 and N2 are pulled down to the ground level.

Referring to FIG. 7, the operation of the data output buffer 300 will be described in more detail. The level shifting data DATAA and DATAAB have different logic levels when cell data is read. In this case, the data latched in phase with respect to the level shifting data DATAA and DATAAB is firstly latched in the first latch 301.

On the other hand, the level shifting data DATAA and DATAAB have the same logic " low " level after the level shifting data DATAA and DATAAB are salph latched in the first latch 301. In this case, only the transistors MP4 and MP6 are turned on, and the first latch 301 is subjected to a self reset due to the floating state of the first latch 301.

The latch data DATABB and DATAB, which are latched to the first latch 301, are read from the cell in the current cycle, and the latch data DATABB and DATAB are kept in the latch cycle, and the data patch signal KDATAP and the second enable signal When KDPRECB is both transitioned to a logical "high" level, it is sent to the second latch 302. In other words, when both the patch signal KDATAP and the second enable signal KDPRECB are transitioned to a logic "high" level, the transfer control signal KDATAB is brought to a logic "low" level by the NAND gate ND1, Since the transfer control signal KDATA is at a logic "high" level, the corresponding transistors are turned on, so that the latch data of the first latch 301 is transferred to the second latch 302. The latch data DATAC and DATACB of the first latch 302 are data whose phase is inverted with respect to the latch data DATABB and DATAB of the first latch 301. The latch data DATAC and DATACB are then turned off via a logic combination circuit consisting of the NAND gates ND1 and ND2 and the inverters INV9 and INV10 when the output enable signal OE is activated to a logic "high" level. The chip driver 400 is output.

Referring to FIG. 7, the off-chip driver 400 is driven in response to the output signals DOU and DOD from the data output buffer 300 and transmits final output data to an external data input / output bus. For example, when the output signal DOU is at the logic "high" level, the NMOS transistor MN11 is turned on so that the potential of the output terminal is pulled up to the power supply voltage level. On the other hand, when the output signal DOD is at the logic "high" level, the NMOS transistor is (MN12) is turned on so that the potential at the output stage is pulled down to ground level.

FIG. 9 is a waveform diagram showing simulation results when the supply voltage VDD is set to 3.6 V and the temperature Temp is set to # 10 ° C. for the high speed data output device according to the present invention, and the best model parameter is applied.

According to the embodiment of the present invention, while the transmission control signal KDATA maintains the "logical" high level, only the latch data of the first latch is transferred to the second latch 302 of the next stage in the previous cycle, and the current cycle. In the latch data of the first latch is not transmitted, the latch data DATAB and DATABB of the first latch and the transmission control signal KDATA are not overlapped in the current cycle as shown in FIG.

This invention is not limited to the above-mentioned embodiment, It can change and implement in various ways within the range which does not deviate from the summary.

Therefore, in the present invention, by generating a transmission control signal by properly combining the data patch signal and the level shifter enable signal, the overlap between the latch data and the transmission control signal is prevented not only in the worst condition but also in the best condition, thereby providing stable data output. The effect can be obtained.

Claims (2)

A semiconductor device for a high speed data output having a main sense amplifier for sensing data read from a memory cell and outputting sensing data, and an output driver for outputting data. Level shifting means for level converting sensing data from the main sense amplifier to output level shifting data; A first latch and a second latch, the second latch latching the level shifting data to the first latch, and logically combining the data patch signal and the first enable signal to the third latched data to the first latch. A data output buffering means for latching with two latches and outputting data latched to the second latch through the output driver in response to an output enable signal; And A first and a second enable signal for controlling the main sense amplifier and the level shifting means such that the sensing data is salph reset after being sense latched to the data output buffering means in response to a first control signal and the level shifting data. And self-resetting control means for supplying said second enable signal to said data output buffering means so that data generated in said first latch is transmitted to said second latch. Device. The method of claim 1, wherein the data output buffering means A NAND gate generating a first transmission control signal by performing an AND-OR on the data patch signal and the second enable signal to transfer the data latched to the first latch to the second latch, and the first transmission control And an inverter for inverting the signal to generate a second transmission control signal.