JPH09231771A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the read operation and reduce the power consumption. SOLUTION: The memory device is provided with a detecting circuit 14 which detects, at the read time, a minute potential difference of a pair of selected bit lines SBL1, SBL2 and generates potential difference detection signals BVD, BVD' of an activation level. A sense amplifier 13 is of a type of a flip- flop circuit directly controlled by the BVD. Moreover, the memory device has a selection row connection-controlling circuit 11 which separates the sense amplifier 13 from the pair of selected bit lines when the sense amplifier operates. A word line-driving circuit 7 is directly controlled by the BVD', thereby to speed up a changing timing for a non-selection level of a word line WL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a synchronous type or static type semiconductor memory device which controls the operation of an internal circuit in synchronization with a synchronizing signal.

[0002]

2. Description of the Related Art A synchronous or static semiconductor memory device for controlling the operation of an internal circuit in synchronization with a sync signal is
There are those that use a clock signal from the outside as the synchronization signal, and those that detect changes in the address value of the address signal from the outside to generate a synchronization signal and use this synchronization signal to control the operation of internal circuits. . In these semiconductor memory devices, in order to shorten the read time of the data stored in the memory cell and reduce the power consumption, the data read from the memory cell is sense-amplified, and the sense-amplified data is When a predetermined level is reached, the technique of deactivating the sense amplifier and setting the word line to the non-selected level has been used.

FIG. 5 shows a typical example (first example) of a synchronous or static semiconductor memory device using an external clock signal using such a technique.

This semiconductor memory device includes a plurality of static type memory cells arranged in a matrix in the row and column directions, and a row provided corresponding to each row of the plurality of memory cells and corresponding row at the selection level. A plurality of word lines WL which bring the memory cell of the selected state into a selected state, and a plurality of pairs of first and second bits which are provided corresponding to the respective columns of the plurality of memory cells and which transmit the data of the memory cell of the selected state A memory cell array 1 including lines BL1 and BL2;
A bit line precharge circuit 3 that precharges a plurality of pairs of first and second bit lines BL1 and BL2 to a predetermined level according to a precharge signal PC, and a row address signal ADr when the data read control signal RDC is at an activation level. According to the column address signal ADc, a row decoder 6 and a word line drive circuit 7 which set one of the plurality of word lines to a selection level, and a plurality of pairs of first and second bit lines BL
1, a pair of BL2 is selected (selected bit line SB
L1, SBL2) a column decoder 9 and a column selection circuit 10,
A sense amplifier 13x which is activated in response to the activation level of the data read control signal RDC and amplifies the data transmitted to the selected bit lines SBL1 and SBL2, and two output terminals of the sense amplifier 13x are connected to the data read control signal RD.
When the level of the output signal of the sense amplification output precharge circuit 18 which precharges to a predetermined level when the deactivation level of C and the level of the output signal of the sense amplifier 13x (signal level difference between two output terminals) is larger than a predetermined value. A sense amplification potential difference detection circuit 19 which outputs a sense amplification potential difference detection signal SVDx which becomes an activation level, and a sense signal which becomes an activation level in response to a high level of an external clock signal CK when the read signal RD is an activation level. The data read control circuit 21 that outputs the data read control signal RDC that becomes the inactive level after a predetermined time from the change of the amplified potential difference detection signal SVDx to the inactive level, and the data sense-amplified according to the data read control signal RDC. The data latch output buffer circuit 20 that captures, holds and outputs the clock signal CK In response, the precharge control circuit 2 for generating the precharge signal PC, the row address buffer circuit 4 for supplying the row address signal ADr to the row decoder 6 according to the clock signal CK, and the row decoder 6 according to the clock signal CK are operated. The row decoder control circuit 5 for controlling and the column address signal AD according to the clock signal CK
The column address buffer circuit 8 which takes in c and supplies it to the column decoder 9 is provided.

Note that FIG. 5 shows only the circuit blocks necessary for the data read operation, and the circuit blocks necessary for the data write operation are omitted.

FIG. 6 shows a concrete circuit example of the sense amplifier 13x, the sense amplification potential difference detection circuit 19, the sense amplification output precharge circuit 18, the data read control circuit 21 and the data latch output buffer circuit 20 of this semiconductor memory device. It is a circuit diagram (for example, Japanese Unexamined Patent Publication No. H5-274885).
Reference).

The sense amplifier 13x is composed of two current mirror circuit type operational amplifiers A1 and A2 which share a transistor Q25 for activation control which receives a data read control signal RDC at its gate.
Selected bit line SB when C is at the activation level (high level)
The data levels of L1 and SBL2 are detected and amplified to the power supply potential level and the ground potential level. The sense amplification output precharge circuit 18 includes transistors Q36 and Q37, and precharges the two output terminals of the sense amplifier 13x to the power supply potential level when the data read control signal RDC is at the inactivation level (low level).

The sense amplification potential difference detection circuit 19 includes inverters IV21 and IV22 and a NOR type logic gate G2.
1 and the amplified output SN by the sense amplifier 13x
When the potential difference between SN1 and SN2 (hereinafter referred to as sense amplification outputs SN1 and SN2) reaches a predetermined level (usually an intermediate level between high level and low level, that is, half the power supply potential), the activation level (low level) The level) sense amplified potential difference detection signal SVDx is output. So this circuit
It is an EX-NOR circuit that becomes high level when the levels of two input data are both high level side or both low level side, and becomes low level when one is high level and the other is low level.

The data read control circuit 21 includes a delay element D.
21, NAND type logic gates G22 and G23 and inverters IV27 and IV28, and when the read signal RD is at the activation level (high level), in response to the high level of the clock signal CK, the high level and the sense amplification potential difference detection signal. The data read control signal RDC which becomes low level is generated with a delay of the delay time of the delay element D21 from the change of SVDx to low level.

Next, regarding the operation of this semiconductor memory device,
Description will be made with reference to the timing chart shown in FIG. 7 and FIGS.

First, at time t0, the clock signal C
K is at a high level, the row decoder control signal XE and the precharge signal PC are at a high level, the word line WL is at a low level (non-selection level), and the selected bit lines SBL1 and SBL2 are the same as the data read in the previous cycle. The sense amplification outputs SN1 and SN2 remain, and the power supply potential (Vc
c) Precharged to level. The sense amplification potential difference detection signal SVDx is the sense amplification outputs SN1 and S.
Since both N2 are at a high level (power supply potential level), a high level, the nodes N1 and N2 of the data read control circuit 21 are at a low level and a high level, respectively, in the previous cycle, and the output data read control signal RDC. Is at a low level.

When the clock signal CK changes to the low level at the time t1, first, the precharge signal PC becomes the activation level of the low level, and the bit line precharge circuit 3 causes the plurality of pairs of bit lines BL1 and BL2 to be powered. The column selection circuit 1 is precharged to the potential Vcc level.
The bit line SBL1, SBL2 selected by 0 is also the power supply potential V
Precharged to cc level. Further, the node N2 of the data read control circuit 21 (hereinafter referred to simply as node N2, N2)
The same applies to 1) changes to a low level. Then, the row decoder 6 is inactivated by setting the row decoder control signal XE to the inactivation level (low level). Further, at this time point, the rising of the sense amplification potential difference detection signal SVDx appears after the delay time td of the delay element D21, and the node N1.
Will also be at a high level.

When the clock signal CK changes to a high level at time t2, first, the precharge signal PC becomes a high level (inactive level) and a plurality of pairs of bit lines BL.
The precharge of all 1 and BL2 (including the selected bit lines SBL1 and SBL2) is stopped, and the node N2 becomes high level. When the node N2 changes to a high level, the node N1
Remains high, the data read control signal R
DC becomes a high level activation level (time t3). At this point, the row decoder control signal XE also becomes the active level, the row decoder 6 is activated, and the row address signal A
It decodes Dr and outputs it to the word line drive circuit 7.

In response to the activation level of data read control signal RDC, word line drive circuit 7 is activated at time t4.
As a result, one word line WL becomes the selected level, the memory cell connected to this word line WL is brought into the selected state, and the stored data is read to the bit lines BL1 and BL2.
In addition, the bit line selected by the column selection circuit 10 (data from the memory cell is also transmitted to the selected bit line.
Further, the sense amplifier 13x is also activated in response to the activation level of the data read control signal RDC, and the selected bit line S
The data level of BL1 and SBL2 is amplified.

At time t5, the sense amplification output SN
When one of SN1 and SN2 changes from the high level side to the low level side, the sense amplification potential difference detection signal SVDx changes to the low level, and this change occurs at time t6 when the delay time td of the delay element D21 elapses. At the node N1, the data read control signal RDC is set to a low level inactivation level.

In response to the inactive level of the data read control signal RDC, the sense amplification outputs SN1 and SN2 are precharged to the power supply potential Vcc level, and as a result, the sense amplification potential difference detection signal SVDx goes high at time t7. And changes. At this point, the word line drive circuit 7 sets the word line WL to the non-selection level in response to the data read control signal RDC.

Then, at time t8, the clock signal CK
Becomes a low level, and the operation from the time t1 described above is repeated.

In this semiconductor memory device, the bit lines BL1 and BL2 are provided during the low level period of the clock signal CK.
(Including SBL1 and SBL2) are precharged, and in response to the change of the clock signal CK to the high level, the memory cell is selected and the data from the selected memory cell is sense-amplified. Sense amplification is stopped and memory cell selection is stopped after a predetermined time after the level and low level are determined, so that the data read time can be shortened.
It is possible to shorten the period in which the current flowing in the sense amplifier 13x, which occurs because it is formed of the current mirror circuit type, and reduce the power consumption.

Next, FIG. 8 shows an example (second example) of a semiconductor memory device in which a change in the address value of an address signal from the outside is detected to generate a synchronizing signal, and the synchronizing circuit controls the internal circuit. (See, for example, Japanese Patent Laid-Open No. 1-300493).

This semiconductor memory device is provided with an address change detection circuit 22 which detects a change in the address value of the row address signal ADr and generates a synchronization signal ATD, and the precharge signal PC is supplied in accordance with the synchronization signal ATD. When the bit lines BL1 and BL2 are generated, the bit lines BL1 and BL2 are precharged, and the potential difference between the sense amplification outputs S1 and S2 is detected to generate the sense amplification potential difference detection signal STD. The sense amplification potential difference detection signal STD and the synchronization signal ATD are generated. To generate an enable signal ENA from the row decoder 6y,
The operation of the sense amplifier 13y is controlled.

Since the enable signal generator 23 in this semiconductor memory device (second example) corresponds to the data read control circuit 21 of the first example shown in FIGS. 5 and 6, the address change detection circuit 22 is shown. The basic operation is similar, although there is a difference in that a synchronization signal ATD is generated by this and an internal circuit is controlled by using this synchronization signal ATD, and in details. Therefore, detailed description of the operation of the second example is omitted.

As shown in FIG. 9, the sense amplifier 13y of the semiconductor memory device of the second example has a structure in which three current mirror circuit type operational amplifiers A1 to A3 are combined.

[0023]

In the conventional semiconductor memory device described above, in both the first and second examples, the sense amplification potential difference detection circuits 19 and 19y are set to the normal data "1" level,
Since it is a circuit that performs the EX-NOR and EX-OR operations by detecting the "0" level, the sense amplification output SN1,
If the levels of SN2 / S1 and S2 are not determined, the levels of the sense amplification potential difference detection signals SVDx and STD are not determined,
There is a problem that it is difficult to increase the operating speed because the time until the level is determined becomes long, and the sense amplifiers 13x and 13y are of the current mirror circuit type, so that the operating period is short. However, during that period, the operating current is continuously flowing, which causes the problem of increased power consumption. In addition, since there is no data retention function or data feedback function, the level of the sense amplification output is fixed. Until then, it is necessary to continue supplying the input data to the sense amplifiers 13x and 13y, and it is also difficult to increase the operation speed. Further, after the level of the sense amplification output is fixed, the sense amplification potential difference is increased. Since the level of the detection signal is determined and the word line is set to the non-selection level by this, one level of the bit line is kept at the ground potential (0 V) during this period. Reduced, for precharging the bit lines to the power supply potential, there is a problem that also the power consumption is increased.

An object of the present invention is to provide a semiconductor memory device capable of increasing the operating speed and reducing the power consumption.

[0025]

A semiconductor memory device of the present invention is provided with a plurality of static type memory cells arranged in a matrix in a row direction and a column direction, and corresponding to each row of the plurality of memory cells. A plurality of word lines that select the memory cells of the corresponding row at the selected level and the respective columns of the plurality of memory cells, and are precharged and selected at a predetermined potential at a predetermined timing. A memory cell array including a plurality of pairs of first and second bit lines for transmitting data of a memory cell in a state, and a selected one of the plurality of pairs of first and second bit lines activated at a predetermined timing. A flip-flop circuit type sense amplifier that detects and amplifies the potentials of the first and second bit lines, and one of the selected first and second bit lines An exclusive OR circuit type selection bit line pair potential difference detection circuit for generating a detection signal of an activation level by detecting that the other potential has changed by a minute potential from the precharge potential with respect to the dipotential, In response to the first level of the clock signal, the plurality of pairs of the first and second bit lines, the input / output terminals of the sense amplifier and the input terminal of the selected bit line pair potential difference detection circuit are precharged, and the clock signal In response to the second level, the one of the plurality of word lines is set to the selection level, and the first and second read and selected from the memory cell selected by the word line of the selection level are selected. The potential difference of the data transmitted to the bit line is detected to generate the detection signal of the activation level, and the sense amplifier is activated in response to the activation level of the detection signal. First, disconnecting between the second bit line, and is configured by a word line of the selected level to the non-selected level, which is the selection and Nsu amplifier.

A precharge control circuit for precharging a memory cell array and a plurality of pairs of first and second bit lines of the memory cell array to a predetermined potential for a predetermined period in response to a first level of a clock signal. And a bit line precharge circuit and a row in which a word line of an address designated by a row address signal is set to a selection level in response to a second level of the clock signal and a non-selection level is set in response to an activation level of a detection signal. A decoder control circuit, a row decoder and a word line drive circuit, a column decoder and a column selection circuit for selecting the first and second bit lines of an address designated by a column address signal, and activation when the detection signal is at an activation level. First and second selected by the column decoder and column selection circuit
A sense amplifier that detects and amplifies the potential of the bit line of
A selected bit line pair potential difference detection circuit that generates the detection signal, and a selected column connection that disconnects between the sense amplifier and the selected first and second bit lines in response to an activation level of the detection signal. A control circuit and a sense amplifier precharge circuit for precharging an input / output terminal of the sense amplifier and an input terminal of the selected bit line pair potential difference detection circuit to a predetermined potential for a predetermined period in response to a first level of the clock signal. And is configured.

Further, the selected bit line pair potential difference detection circuit is
First and second inverters, each having a threshold voltage smaller than the precharge potential by a minute potential and receiving corresponding potentials from the first and second bit lines selected at the input terminals, and a first input A first NAND gate having an end connected to the input end of the first inverter and a second input end connected to the output end of the second inverter; and a first input end connected to the input of the second inverter. A second NAND gate connected to a first input terminal and a second input terminal connected to an output terminal of the first inverter; and first and second input terminals connected to the first and second N gates.
An output terminal of the AND gate and a corresponding third NAND gate are connected and configured as a circuit for outputting a detection signal from the output terminal of the third NAND gate, or a selected bit line pair potential difference detection circuit is provided as a first circuit. In place of the second inverter, the first and second input terminals having a threshold voltage smaller than the precharge potential by a minute potential and selected as the first and second input terminals are provided.
Corresponding to the potential from the second bit line, the receiving output end is set to the first
And a fourth NAND gate connected to the second input end of the NAND gate and the second input end of the second NAND gate.

[0028]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing a concrete circuit example of its main part.

The memory cell array 1, precharge control circuit 2, bit line precharge circuit 3, row address buffer circuit 4, row decoder 6, word line drive circuit 7, column address buffer circuit 8, of the first embodiment, The column decoder 9 and the column selection circuit 10 are the same as the first conventional example shown in FIG. 5 except that the detection signals supplied to the word line drive circuit 7 are different (BVD * or RDC). This is the same as the example semiconductor memory device. In the following, description will be given with a focus on parts other than these configurations.

The selected column connection control circuit 11 includes transistors Q4 and Q5, and a selected bit line pair potential difference detection signal BV.
According to the level inversion signal BVD * of D, when the selected bit line pair potential difference detection signal BVD is at the inactivation level (low level), the first and second bit lines (SBL1, SBL2) selected by the column selection circuit 11 are connected. Connected to the input / output terminal of the sense amplifier 13 and the input terminal of the selected bit line pair potential difference detection circuit,
Disconnect at the activation level.

The sense amplifier 13 includes transistors Q9 ...
It is composed of a flip-flop circuit made up of Q14, and is activated and transmitted when the selected bit line pair potential difference detection signal BVD is at the activation level (high level) when the precharge signal PC is at the inactive level (high level). The potentials of the selected bit lines (SBL1, SBL2) are detected and amplified.

The selected bit line pair potential difference detection circuit 14 has a threshold voltage lower by a minute potential than the precharge potential, and the first and second bit lines S selected at the input ends.
First and second inverters IV3, IV4 correspondingly receiving the potentials from BL1, SBL2, a first input terminal connected to the input terminal of the inverter IV3, and a second input terminal connected to the output terminal of the inverter IV4. First NAND gate G
2, a second NAND gate G3 having a first input end connected to the input end of the inverter IV4 and a second input end connected to the output end of the inverter IV3, and first and second input ends being a NAND gate Third connection corresponding to the output terminals of G2 and G3
Of the NAND gate G4 and an inverter IV5 for inverting the level of the output signal of the NAND gate G4. The potentials from the selected first and second bit lines are one precharge potential and the other potential. An exclusive OR circuit type (EX-NOR), which detects that the potential has dropped from the precharge potential by a minute potential and outputs a selected bit line pair potential difference detection signal BVD which becomes an activation level from the output end of the NAND gate G4. Has become. Also, the inverter IV
From the output terminal of 5, the selected bit line pair potential difference detection signal BVD
Level inversion signal BVD * is output.

The sense amplifier precharge circuit 12 is composed of transistors Q6 to Q8 and has a precharge signal PC.
Is at the activation level (low level), the sense amplifier 13
Are precharged to the power supply potential (Vcc) level.

The latch circuit 15 includes a NAND gate G5,
It is a general flip-flop circuit composed of G6 and an inverter IV6, which latches the data amplified by the sense amplifier 13 and latches the latched data via the data output buffer circuit 17 controlled by the data output control circuit 16. Is output to the outside.

The word line drive circuit 7 includes a NAND gate G1 corresponding to each word line WL and an inverter IV1, and the level inversion signal BVD * of the selected bit line pair potential difference detection signal BVD is at a high level (BVD is an inactive level). ), A predetermined word line is set to the selection level in accordance with the decode signal XD from the row decoder 6, and the low level of BVD * (B
The selected word line is also set to the non-selection level in response to VD (activation level).

Next, the operation of the first embodiment will be described with reference to the timing chart shown in FIG.

First, at time t0, the clock signal C
K is at a high level, the row decoder control signal EX and the precharge signal PC are at a high level, the word line WL is at a low level,
The first and second bit lines BL1 and BL2, the selected bit lines SBL1 and SBL2, and the two input / output terminals SN1 and SN2 of the sense amplifier 13 retain the data of the previous cycle as they are, and the selected bit line pair potential difference detection signal. BVD is at a high level (activation level).

When the clock signal CK changes to the low level at the time t1, first, the precharge signal PC becomes the low level activation level, and the bit line precharge circuit 3 causes the plurality of pairs of the first and second bit lines. BL1, B
All L2 are precharged to the power supply potential Vcc level,
Selected bit lines SBL1, SBL2 by the column selection circuit 10
Is naturally precharged to the power supply potential Vcc level.
At the same time, the two input / output terminals SN1 and SN2 of the sense amplifier 13 are also precharged to the power supply potential level. As a result, the selected bit line pair potential difference detection signal BVD becomes a low level inactivation level. Further, row decoder control signal XE attains the inactive level, and row decoder 6 stops the decoding operation of row address signal ADr.

When the clock signal CK changes to a high level at time t2, first, the precharge signal PC becomes a high level (inactivation level), and a plurality of pairs of first and second pairs are provided.
Bit lines BL1, BL2 and selected bit lines SBL1,
Stop precharging of SBL2, and also sense amplifier 1
The precharge of the input / output terminals SN1 and SN2 of 3 is also stopped. Then, at time t3, the row decoder control signal XE attains an activation level, and the row decoder 6 outputs the row address signal ADr.
The decoding operation of is started. At time t4 when the decode signal XD is output by the row decoder 6, the level inversion signal BVD * of the selected bit line potential difference detection signal is at a high level (BVD is a low level deactivation level), so that the row address signal. One word line WL at the address specified by ADr becomes the selection level.

When one word line WL attains a selection level, a plurality of memory cells connected to this word line WL are brought into a selected state, and the data of these memory cells have a plurality of pairs of first and second bit lines BL1. , BL2. At this time, the column selection circuit 10 receives one of the pairs of first and second bit lines BL1 and BL2 according to the column address signal ADc.
A pair is selected (selected bit lines SBL1, SBL
2) The selected bit lines SBL1 and SBL2 are connected to the sense amplifier 13 and the selected bit line pair potential difference detection circuit 14 by the selected column connection control circuit 11.

At time t5, the selected bit line pair potential difference detection circuit 14 detects that the potential of one of the selected bit lines SBL1 and SBL2 has dropped below the threshold voltage of the inverters IV3 and IV4, and is activated. A level (high level) selected bit line pair potential difference detection signal BVD is generated. In response to this, the sense amplifier 1 is activated, and
The potential of one input / output terminal is detected and amplified, and the selected column connection control circuit 11 is connected to the sense amplifier 13 and the selected bit line SB.
The connection between L1 and SBL2 is disconnected to speed up the sense amplification operation of the sense amplifier 13. One of the amplified outputs (SN1, SN2) by the sense amplifier 13 rapidly becomes the ground potential (0 V) (time t6).

Further, the selected bit line pair potential difference detection signal BV
In response to the activation level of D (high level, BVD * is low level), the word line drive circuit 7 sets the selected bit line WL to the non-selected level at time t7. As a result, the memory cell connected to this word line WL is separated from the first and second bit lines BL1 and BL2, and the potential changes of the bit lines BL1 and BL2 due to the storage data of these memory cells are stopped.

When the clock signal CK changes to the low level at time t8, the operation returns to the operation at time t1 and the subsequent operations are repeated.

In this embodiment, the input threshold voltage of the selected bit line pair potential difference detecting circuit 14 (threshold voltage of the inverters IV3 and IV4) is the bit lines BL1 and B.
Since the value is lower than the precharge potential (power supply potential Vcc) of L2, the selected bits SBL1 and SBL2, and the two input / output terminals SN1 and SN2 of the sense amplifier 13, only the stored data of the memory cell in the selected state. As a result, the level of one of the bit lines BL1, BL2 is slightly lowered from the precharge potential, and the selected bit line pair potential difference detection signal BVD becomes the activation level. Therefore, the potential difference detection time of the selected bit lines SBL1 and SBL2 is shortened as compared with the conventional example that cannot be detected unless the "1" level and "0" level of the sense amplification output are determined.

Further, the selected bit line pair potential difference detection signal BV
Sense amplifier 1 activated in response to the activation level of D
Since 3 is a flip-flop circuit type, it has a data holding function and a data feedback function, which enables high-speed sense amplification operation. Further, at the time of the sense amplification, the input / output terminals (SN1, SN2) are selected bit line SBL1. , SBL2
Since they are separated from each other, the influence of the parasitic capacitance of these selected bit lines can be eliminated, and in this respect as well, the high speed sense amplification operation can be promoted. Further, the current flows through the sense amplifier 13 only when the level of the sense amplification output changes, so that the power consumption can be significantly reduced as compared with the current mirror circuit type.

Further, the selected bit line pair potential difference detection signal BV
D and its level inversion signal BVD * are directly applied to the sense amplifier 13, the word line drive circuit 7, and the selected column connection control circuit 11.
Are supplied to the intermediate control circuit (the data read control circuit 21, the enable signal generation unit 2 as in the conventional example).
Since there is no signal transmission time due to 3), it is possible to shorten the time from a selected memory cell being in a selected state to a non-selected state. Further, by shortening this time, the potential change of one of the plurality of pairs of first and second bit lines BL1 and BL2 by the selected memory cell is stopped at a potential considerably higher than the ground potential (0V) level. Therefore, the power required for precharging the bit line can be significantly reduced.

FIG. 4 is a circuit diagram of a selected bit line pair potential difference detection circuit portion according to the second embodiment of the present invention.

The selected bit line pair potential difference detection circuit 14a of the second embodiment is the inverter I of the selected bit line pair potential difference detection circuit 14 of the first embodiment shown in FIG.
Instead of V3 and IV4, the potentials from the first and second bit lines SBL1 and SBL2 selected for the first and second input terminals that have a threshold voltage smaller than the precharge potential by a minute potential are used. And a NAND gate G7 for connecting the receiving output end to the second input end of the NAND gate G2 and the second input end of the NAND gate G3. Other parts are the same as those in the first embodiment. Further, the function of the selected bit line pair potential difference detection circuit 14a,
The operation and the like are the same as those in the first embodiment, and therefore, the operation and the effect of the second embodiment are also the same as those in the first embodiment, so that further description will be omitted.

[0050]

As described above, according to the present invention, in the data read operation, the minute potential difference between the selected bit line pair is detected to directly control the sense amplifier, the word line drive circuit and the like, so that the operation speed is increased. Since the time required to set the word line to the non-selection level is shortened, the change to the ground potential level side of one of the bit line pairs can be stopped at a potential sufficiently higher than the ground potential. The power consumption during bit line precharging can be reduced and the operation speed can be increased. The sense amplifier is a flip-flop circuit type with data retention and feedback functions, and the selected bit line is disconnected during data amplification. Since the configuration is adopted, there is an effect that power consumption can be reduced and operation speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit example of a main part of the embodiment shown in FIG.

FIG. 3 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIGS. 1 and 2.

FIG. 4 is a circuit diagram of a selected bit line pair potential difference detection circuit portion according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a first example of a conventional semiconductor memory device.

FIG. 6 is a circuit diagram showing a specific circuit example of a main part of the semiconductor memory device shown in FIG.

FIG. 7 is a timing chart of signals of respective parts for explaining the operation of the semiconductor memory device shown in FIGS.

FIG. 8 is a block diagram of a second example of a conventional semiconductor memory device.

9 is a circuit diagram showing a specific circuit example of a sense amplifier portion of the semiconductor memory device shown in FIG.

[Explanation of symbols]

 1 memory cell array 2, 2y precharge control circuit 3 bit line precharge circuit 6, 6y row decoder 7 word line drive circuit 9 column decoder 10 column selection circuit 11 selected column connection control circuit 12 sense amplifier precharge circuit 13, 13x, 13y Sense amplifier 14, 14a Selected bit line pair potential difference detection circuit 19, 19y Sense amplification potential difference detection circuit 21 Data read control circuit 22 Address change detection circuit 23 Enable signal generator BL1, BL2 Bit line G1 to G6 NAND gate IV1, IV3 to IV6 Inverter Q1-Q14 Transistors SBL1, SBL2 Selected bit line WL Word line

Claims (4)

[Claims] 1. A plurality of static type memory cells arranged in a matrix in a row direction and a column direction, and memory cells in a row corresponding to each row of the plurality of memory cells at a selection level. A plurality of pairs of word lines that are in a selected state, and a plurality of pairs that are provided corresponding to the respective columns of the plurality of memory cells and that are precharged to a predetermined potential at a predetermined timing and that transmit data of the memory cells in the selected state. The memory cell array including the first and second bit lines and the potential of the selected first and second bit lines of the plurality of pairs of the first and second bit lines which are activated at a predetermined timing are detected. And a flip-flop circuit type sense amplifier that amplifies the same, and one of the selected first and second bit lines has a precharge potential that is different from the precharge potential of the other. An exclusive-OR circuit type selection bit line pair potential difference detection circuit for detecting a change in a minute potential from the potential and generating an activation level detection signal;
In response to the first level of the clock signal, the plurality of pairs of the first and second bit lines, the input / output terminals of the sense amplifier and the input terminal of the selected bit line pair potential difference detection circuit are precharged, and the clock signal In response to the second level, the one of the plurality of word lines is set to the selection level, and the first and second read and selected from the memory cell selected by the word line of the selection level are selected. The potential difference of the data transmitted to the bit line is detected to generate the detection signal of the activation level, the sense amplifier is activated in response to the activation level of the detection signal, and the sense amplifier and the selected one are selected. A semiconductor memory device characterized in that the first and second bit lines are separated from each other and the word line of the selected level is set to a non-selected level. 2. A precharge control circuit for precharging a memory cell array and a plurality of pairs of first and second bit lines of the memory cell array to a predetermined potential for a predetermined period in response to a first level of a clock signal. And a bit line precharge circuit and a row in which a word line of an address designated by a row address signal is set to a selection level in response to a second level of the clock signal and a non-selection level is set in response to an activation level of a detection signal. A decoder control circuit, a row decoder and a word line drive circuit, a column decoder and a column selection circuit for selecting the first and second bit lines of an address designated by a column address signal, and activation when the detection signal is at an activation level. And a sense amplifier for detecting and amplifying the potentials of the first and second bit lines selected by the column decoder and column selection circuit, and generating the detection signal. A selected bit line pair potential difference detection circuit,
A selected column connection control circuit that disconnects the sense amplifier from the selected first and second bit lines in response to the activation level of the detection signal; and a selected column connection control circuit that responds to the first level of the clock signal. 2. The semiconductor memory device according to claim 1, further comprising a sense amplifier precharge circuit for precharging an input / output terminal of the sense amplifier and an input terminal of the selected bit line pair potential difference detection circuit to a predetermined potential for a predetermined period. 3. A selected bit line pair potential difference detection circuit is provided with corresponding potentials from the first and second bit lines selected as input terminals, each having a threshold voltage smaller than the precharge potential by a minute potential. First and second inverters for receiving, and a first NAND gate having a first input terminal connected to an input terminal of the first inverter and a second input terminal connected to an output terminal of the second inverter A second NAND gate having a first input terminal connected to the input terminal of the second inverter and a second input terminal connected to the output terminal of the first inverter, and first and second input terminals The first and second NAs
3. The semiconductor memory device according to claim 1, further comprising a third NAND gate connected to an output terminal of the ND gate, the circuit outputting a detection signal from the output terminal of the third NAND gate. 4. A selected bit line pair potential difference detection circuit comprising:
And instead of the second inverter, corresponding to the potentials from the first and second bit lines selected for the first and second input terminals, which have a threshold voltage smaller than the precharge potential by a minute potential. 4. The semiconductor memory device according to claim 3, further comprising a fourth NAND gate connecting the receiving output end to the second input end of the first NAND gate and the second input end of the second NAND gate.