KR20000045904A - Circuit for enabling memory cell in semiconductor memory cell having rapid driving speed while not performing repairing operation - Google Patents

Abstract

PURPOSE: A circuit for rapidly enabling a memory cell in a semiconductor memory device is provided to rapidly access a normal cell without delay by using the time for substituting a repair circuit in the case of the generation of a defect in a circuit. CONSTITUTION: In the case of not repairing a semiconductor memory device, a delaying unit(100) programs a redundancy address in a redundancy circuit(110) while cutting off the fuse in a fuse box(104). The output signal of the fuse box maintains a high level for delaying an input address signal(Addrn). And, the input address signal is inputted to a first NAND gate(NAND1) by passing through a first inverter(Inv2). Therefore, a decoder driving signal(dec_en) is generated by the first and the second NAND gates and a second inverter(Inv3). And the decoder driving signal is inputted to a normal cell decoder(120) and to a redundancy cell decoder(130). In the case of repairing the memory device, the decoders operates after receiving the redundancy information. Thus, a wrong operation does not occur.

Description

Memory Cell Enable Circuit of Semiconductor Memory Device with Fast Operation Speed in Non-Repair

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, a non-repairing device capable of quickly accessing a normal cell without a delay time when a repair operation is not performed by using a delay time required to replace a repair circuit in the event of a circuit failure. The present invention relates to a memory cell enable circuit of a semiconductor memory device having a high operation speed.

In semiconductor memory devices, redundancy cells of memory are installed for each sub-array block. For example, redundant rows and columns are pre-installed for each 256K cell array. Replace with a redundancy memory cell in columns. The repair circuit of the semiconductor memory device for this purpose performs a programming in the internal circuit that selects a defective memory cell through a test and replaces it with an address signal of a corresponding redundancy cell when the wafer fabrication process is completed, thus corresponding to a defective line in actual use. When the address is inputted, the selection changes to a line of redundancy cells.

This programming method includes an electric fuse that melts and blows a fuse due to overcurrent, a fuse that is blown out by a laser beam, a short circuit by a laser beam, and a program by using an EPROM memory cell. Among these methods, the laser cutting method is widely used because it is simple, reliable, and easy to layout, and polysilicon wiring or metal wiring is used as the fuse material.

1 is a circuit block diagram illustrating an enable circuit of a redundancy cell and a normal cell of a semiconductor memory device according to the prior art. The circuit is a redundancy circuit unit configured to receive an input address signal Addrn to sense the presence / absence of a redundancy address signal. 20, a delay unit 10 that receives the input address signal Addrn and delays it for a predetermined time to generate a drive signal dec_en for enabling the decoder, and an input address signal Addrn and a redundancy circuit ( The normal cell decoder 30 generating the enable signal nor_en of the normal cell in response to the output n_act of the 20 and the driving signal dec_en output from the delay unit 10, and the redundancy circuit 20. And a redundancy cell decoder 40 generating an enable signal red_en of the redundancy cell in response to the signal r_act whose output is inverted through the inverter Inv and the driving signal dec_en.

For reference, the redundancy circuit 20 serves to detect whether the input address signal Addrn is a redundancy address or not, and in most cases, the redundant address signal is programmed using a fuse cutting method using a laser. do.

The enable cells of the redundancy cell and the normal cell of the semiconductor memory device configured as described above are operated as follows.

In the normal circuit operation, when the input address signal Addrn is input, the redundancy circuit 20 determines whether or not the input address signal is a redundancy address. As a result, when the redundancy address signal is set, the n_act signal is set to a high level and r_act. While making the signal low level, if the input address signal is not a redundancy address, the signal is generated at the opposite level. The delay unit 10 generates a decoder driving signal dec_en after a predetermined delay time has elapsed. Accordingly, the normal cell decoder 30 or the redundancy cell decoder 40 is activated to generate the enable signal nor_en of the normal cell and the enable signal red_en of the redundancy cell through the activated decoder.

Meanwhile, a predetermined delay time is required to perform a redundancy operation in the semiconductor memory device, and a predetermined delay time is required to generate driving signals dec_en of the normal cell decoder 30 and the redundancy cell decoder 40. The reason is to operate the driving signal dec_en after the output signals n_act and r_act of the redundancy circuit 20 are generated so that a malfunction does not occur.

However, in the conventional method, since the driving signal for operating the decoder is generated whether or not the circuit is repaired, the same delay time is required even in a chip in which the delay time for generating the decoder driving signal is not repaired. This operation process is a very unnecessary operation on the unrepaired chip, and also causes a decrease in performance and speed of the memory device.

SUMMARY OF THE INVENTION An object of the present invention is to repair a drive signal after a predetermined delay time when a repair is performed according to whether a chip is repaired or not in a device generating a decoder drive signal in order to solve the problems of the prior art. In this case, the present invention provides a semiconductor memory device having a fast memory cell enable rate at the time of non-repair, which improves performance on a chip that is not repaired by generating a driving signal without delay.

1 is a circuit block diagram showing an enable circuit of a redundancy cell and a normal cell of a conventional semiconductor memory device;

2 is a circuit block diagram illustrating an enable circuit of a redundancy cell and a normal cell of a semiconductor memory device having a non-repair fast memory cell enable rate according to the present invention;

* Explanation of symbols for the main parts of the drawings *

100: delay

110: redundancy circuit

120: normal cell decoder

130: redundancy cell decoder

In order to achieve the above object, the present invention provides a redundancy circuit for receiving the input address signal and detecting the presence / absence of the redundancy address signal, a delay unit for receiving the input address signal and generating a decoder driving signal with a predetermined time delay; A normal cell decoder for generating an enable signal of a normal cell in response to an address signal and an output signal of the redundancy circuit and a delay unit, and a redundancy for generating an enable signal of a redundancy cell in response to an output of the redundancy circuit and the drive signal. In a semiconductor memory device having a cell decoder, a delay unit includes a fuse box that detects whether a circuit is repaired or not, a delay unit that receives an input address signal and delays the predetermined time for a predetermined time, an output of the fuse box, and an output to an input address of the delay unit. If the circuit is repaired by logically combining the signals, When the first delay decoder that generates a drive signal and having a time not repair characterized in that it comprises a first delay time than a predetermined time, the rapid generating a drive signal for generating a drive signal decoder having a second delay portion.

In the present invention, the drive signal generator includes a first inverter for inverting the output of the delayer, a first NAND gate that performs an AND logic on the output of the fuse box and the first inverter, an output of the input address signal and the first NAND gate. And a second inverter for inversely multiplying and a second inverter for inverting the output of the second NAND gate.

According to the present invention, in the case of a chip which does not perform a repair operation, the chip cell lineline enable signal is immediately output to perform access to a normal cell by omitting a procedure of determining whether a redundancy address is input, thereby improving chip performance. In addition, the memory cell access speed time due to the repair mode can be increased.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit block diagram illustrating an enable circuit of a redundancy cell and a normal cell of a semiconductor memory device having a non-repair fast memory cell enable rate according to the present invention.

The memory cell enable circuit of the present invention receives a redundancy circuit unit 110 that detects the presence / absence of a redundancy address signal by receiving an input address signal Addrn, and receives the input address signal Addrn to delay a predetermined time or time. A delay unit 100 that generates the decoder driving signal dec_en without a delay, an output n_act of the input address signal and the redundancy circuit 110, and a driving signal dec_en output from the delay unit 100. In response, the normal cell decoder 120 generating the enable signal nor_en of the normal cell, the signal r_act and the driving signal dec_en inverting the output of the redundancy circuit 110 through the inverter Inv4. The redundancy cell decoder 130 generates an enable signal red_en of the redundancy cell in response to the redundancy cell.

In addition, the delay unit 100 of the present invention includes a fuse box 104 that detects whether a circuit is repaired or not, a delay unit 102 that receives an input address signal Addrn and delays the predetermined time, and a fuse box. Logic combination of the output of the 104 and the output to the input address signal Addrn of the delayer 102 generates a decoder drive signal having the first delay time set when the circuit is repaired and the first delay if not repaired. And a drive signal generator 106 for generating a decoder drive signal having a second delay time which is a predetermined time earlier than the time.

In addition, the fuse box 104 is generally the same as a circuit used in DRAM, and includes a fuse connected to a power supply voltage Vcc terminal, a capacitor C1 and a driving transistor connected in parallel to the fuse. Tr and an inverter Inv1 for inverting the signal of the output node a of the fuse.

In addition, the driving signal generator 106 of the present invention performs a negative logic multiplication on the output of the first inverter Inv2 and the output of the fuse box 104 and the first inverter Inv2. A second NAND gate NAND2 that negatively multiplies the outputs of the first NAND gate, the input address signal Addrn, and the first NAND gate NAND1, and an inverting output of the second NAND gate NAND2; It consists of two inverters Inv3.

The operation of the enable circuit of the memory cell of the semiconductor memory device according to the present invention configured as described above is as follows.

In the delay unit 100 of the present invention, since the fuse box 104 for adjusting the delay time is maintained in the initial state when the memory device is not repaired, the signal applied to the output node b of the fuse box 104 is Low level. Then, the first NAND gate NAND1 receives the output of the fuse box 104 and the output of the first inverter Inv2 and outputs a high level signal by performing an AND logic multiplication. The second NAND gate NAND2 outputs the high level signal. The high level of the gate NAND1 is negatively multiplied with the input address signal Addr to output a high level signal. Accordingly, the delay unit 100 inverts the output of the second NAND gate NAND2 through the second inverter Inv3 to generate a decoder driving signal dec_en having a low level.

The redundancy circuit 110 receives the input address signal Addrn to determine whether the redundancy address is a redundancy address. In this case, since the redundancy circuit 110 is a normal cell address signal, the output n_act signal is at a low level, and the inverted r_act signal is at a high level.

The decoder driving signal dec_en generated without the time delay of the input address signal Addrn through the delay unit 100 is input to the normal cell decoder 120 or the redundancy cell decoder 130 and then normal by the n_act signal. The cell decoder 120 is enabled and the redundancy cell decoder 130 is disabled by the r_act signal to generate the enable signal nor_en of the normal cell through the normal cell decoder 120.

Therefore, when the memory device is not repaired, the delay unit 100 of the present invention has a predetermined setting time (hereinafter referred to as a second delay time) through the conventional delay unit 102. On the contrary, in the present invention, the decoder having a delay of the minimum logic operation time (hereinafter referred to as the first delay time) through the driving signal generator 106 directly without passing through the delay unit 102 by the signal of the fuse box 104. The driving signal drv_en is output.

On the other hand, when the semiconductor memory device is not repaired, the delay unit 100 according to the present invention fuses the redundancy circuit 110 with the fuse address of the fuse box 104 to adjust the delay time while programming the redundancy address. To cut. Then, the output signal of the fuse box 104 maintains the high level, and thus the input address signal Addrn is delayed by the predetermined time (second delay time) through the delay unit 102 and the first inverter Inv2. It is input to the first NAND gate (NAND) via). Accordingly, the decoder driving signal dec_en is generated through the first NAND1, the second NAND2, and the second inverter Inv3.

Since the operation is the same as the conventional memory cell enable circuit, the n_act signal output through the redundancy circuit 110 becomes a high level and the inverted r_act signal becomes a low level. The decoder Add signal generates a decoder driving signal dec_en delayed by a predetermined time and is inputted by the n_act signal after the decoder driving signal dec_en is input to the normal cell decoder 120 or the redundancy cell decoder 130. While the normal cell decoder 120 is disabled, the redundancy cell decoder 130 is enabled by the r_act signal to generate the enable signal red_en of the redundancy cell through the redundancy cell decoder 130.

Thus, when the memory device of the present invention is repaired, the decoders 120 and 130 operate after accepting the redundancy information and thus do not cause a malfunction.

Meanwhile, the above-described memory cell enable circuit of the memory device of the present invention can be applied not only to redundancy of row addresses but also to redundancy of column addresses.

As described above, in the case of a chip which does not perform a repair operation, the chip repaired by omitting a procedure of determining whether a redundancy address is input and outputting a normal cell wordline enable signal immediately to perform access to a normal cell is performed. In this case, stable operation (not malfunction) can be performed to increase chip performance, and in a non-repaired chip, memory cell access speed can be increased to provide high performance to a semiconductor memory device.

Claims (2)

A redundancy circuit section for receiving an input address signal and detecting the presence / absence of a redundancy address signal, a delay section for receiving the input address signal and generating a decoder driving signal delaying the input address signal by a predetermined time, and the input address signal and the redundancy circuit A normal cell decoder for generating an enable signal of a normal cell in response to an output and a drive signal of the delay unit, and a redundancy cell decoder for generating an enable signal of a redundancy cell in response to an output of the redundancy circuit and the drive signal; In a memory cell enable circuit of a semiconductor memory device, The delay unit may include a fuse box detecting whether a circuit is repaired or not; A delay unit receiving the input address signal and delaying the input address signal for a predetermined time; And Logically combines the output of the fuse box and the output of the delayer with the input address signal to generate a decoder drive signal having a first delay time set when the circuit is repaired, and a minimum faster than the first delay time if not repaired. And a driving signal generator for generating a decoder driving signal having a second delay time of the semiconductor memory device. The method of claim 1, wherein the driving signal generating unit A first inverter for inverting the output of the delay unit; A first NAND gate negatively multiplying an output of the fuse box and the first inverter; A second NAND gate which negates AND of the input address signal and the output of the first NAND gate; And And a second inverter for inverting the output of the second NAND gate.