KR20000018206U - Repair circuit of memory device - Google Patents

Abstract

The present invention relates to a repair circuit of a memory device, wherein each repair unit for each subarray block of the memory device shares one repair unit for a plurality of subarray blocks, and repairs a plurality of subarray blocks as output values of the repair unit. By further comprising a block selector for selecting a sub-array block so that the overall chip area can be reduced.

Description

Repair circuit of memory device

The present invention relates to a repair circuit of a memory device, and more particularly, a repair of a memory device to reduce the overall redundancy circuit area by sharing a repair unit existing for each sub-array block of each memory device by a predetermined sub-array block. It is about a circuit.

If any one of the many fine cells in the memory element is defective, it cannot be used as a DRAM and thus is treated as defective. However, as the density of DRAM increases, the probability of defects occurring in only a small number of cells is high. However, discarding them as defective products is an inefficient treatment method that lowers the yield. Therefore, in this case, a method of increasing the yield by adopting a redundant memory cell installed in the DRAM in advance is replaced. As redundancy circuits are installed, the area of the chip increases and the number of tests necessary for remedy of defects becomes a problem, but in DRAM, the area of the chip does not increase so much that it is adopted from 64K to 256K DRAM in earnest.

The redundancy circuit of memory cells is installed for each sub-array block, and spare ROW and COLUMN are installed in advance so that defects occur and replace defective memory cells with redundancy memory cells in ROW / COLUMN units. When the wafer processor is terminated, the internal circuit performs programming that selects the defective memory cell through the test and replaces the corresponding address with the address signal of the spare cell. Therefore, when an address corresponding to the defective line is input during actual use, a spare is instead provided. The selection changes to the line. These programming methods include electric fuses that melt and blow fuses due to overcurrent, burned fuses by laser beams, short circuits by laser beams, and programming by EPROM memory cells. Among these methods, a laser cutting method is widely used because of its simple, reliable and easy layout, and polysilicon wiring or metal wiring is used as the fuse material.

1 is a block diagram schematically illustrating a redundancy circuit of a general memory device.

As shown here, the subarray blocks SB1 and SB2 are arranged on the left and right sides, and the repair unit 5 is positioned at the center of each of the subarray blocks SB1 and SB2, and the subarrays are arranged according to the output value of the repair unit 5. The word line selection unit 50 for selecting whether to select the spare word line SWL or the normal word line NWL of the blocks SB1 and SB2 is controlled.

Therefore, when the repair is performed in the repair unit 5, the spare word line SWL is selected, and when the repair is not performed, the normal word line NWL is selected.

FIG. 2 is a circuit diagram illustrating in detail the repair unit of the redundancy circuit of FIG. 1.

As shown here, the operation switch unit 10 precharges the power supply voltage VCC by the complementary precharge signal xdpbb, and between the operation switch unit 10 and the ground via the fuse unit PF. Connected to the address signal ADDR of the defective circuit to turn on the address input unit 20 for detecting the cutting state of the fuse unit PF, and the voltage value of one end of the operation switch unit 20 and the fuse unit PF. And a latch unit 40 for stabilizing the power supply, and an output unit 30 for outputting a stable value by the latch unit 40.

In addition, a word line selector 50 for selecting whether to access the normal cell or the spare cell of the subarray block is connected to the output unit 30.

The word line selector 50 is activated by the positive signal to enable the spare word line SWL and the spare word line boot strapping circuit SPX and the negative signal to enable the normal word line NWL. Is composed of a normal word line boot strapping circuit (NPX).

Referring to the operation of the repair unit made as described above are as follows.

When the complementary precharge signal xdpbb is input at a low potential, the operation switch unit 10 is turned on so that the power supply voltage VCC is applied to the fuse PF. In this state, when the address signal ADDR is input to the address input unit 20, the NMOS transistor of the bit having the high potential value is turned on so that the power supply voltage VCC supplied through the operation switch unit 10 is turned on to supply the NMOS transistor. The pass is formed so that the potential of node 'A' has a low potential. Accordingly, the value of the node 'B' also becomes low potential, and this value is stabilized by the latch unit 40, and then the inverted value is again inverted in the latch unit 40 through the inverter of the output unit 30 to output the normal state. Maintains a low potential.

Then, the low potential value of the output unit 30 is applied to the word line selecting unit 50 to enable the normal word line NWL by the normal word line boot strapping circuit NPX that is activated to the negative signal. Access normal cells.

In such a state, when the fuse of the fuse PF is cut with a laser beam, the current path formed with the address input unit 20 through the fuse switch PF through the operation switch unit 10 is blocked, and thus the node 'A' The potential becomes high potential. Therefore, the node 'B' also becomes a high potential, and this value is inverted by the inverter of the latch unit 40 to turn on the PMOS transistor so that the power supply voltage stabilizes the node 'B' strongly to the high potential. By inverting the value inverted by the latch unit 40 is outputted again.

Then, the high potential value of the output unit 30 is applied to the word line selector 50 to enable the spare word line SWL by the spare word line boot strapping circuit SPX that is activated to the positive signal. The spare cells of the array blocks SB1 and SB2 are operated to access the spare cells.

However, as shown in FIG. 1, in the redundancy circuit, since the repair unit as shown in FIG. 2 must be provided for each subarray block, in case of 16M bit DRAM, 64 subarray blocks (SB1 and SB2) composed of 256Row × 1024Column cells must be provided. 64 repair parts 5 should be provided for the subarray blocks SB1 and SB2. However, since a defect does not actually occur in every cell, when a defect does not occur, there is a problem that the repair unit takes up too much chip area because it is unnecessary.

The present invention was created to solve the above problems, and an object of the present invention is to share a repair unit for each sub-array block adjacent to each other by having a repair unit for each sub-array block in a redundancy circuit of a memory device. The present invention provides a repair circuit for a memory device in which a block selector for selecting a subarray block can be provided to reduce the overall chip area.

1 is a block diagram schematically illustrating a redundancy circuit of a general memory device.

FIG. 2 is a circuit diagram illustrating in detail the repair unit of the redundancy circuit of FIG. 1.

3 is a circuit diagram showing in detail a repair circuit of a memory device according to the present invention.

4 is a block diagram schematically illustrating a redundancy circuit of a memory device employing a repair circuit according to the present invention.

-Explanation of symbols for the main parts of the drawings

10: operation switch unit 20: address input unit

30: output part 40: latch part

50: word line selector 60: block selector

The present invention for achieving the above object in the repair circuit of the memory device having each repair unit for each sub-array block of the memory device, to share one repair unit for a plurality of sub-array blocks, a plurality of output values of the repair unit The apparatus may further include a block selector configured to select the subarray block so as to repair the two subarray blocks.

Referring to the operation of the present invention made as described above are as follows.

When a defect does not occur in the memory cell, the signal output from the repair unit enables the normal word line. The normal word line of the subarray block shared by the block selector enables the normal cell to be accessed. However, when a repair is performed due to a defect, the signal output from the repair unit selects a shared subarray block by the block selector to replace the spare cell with a spare cell to replace the defective normal cell with a spare cell. To work.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as the conventional configuration using the same reference numerals and names.

3 is a circuit diagram illustrating a repair circuit of a memory device according to the present invention.

As shown here, the operation switch unit 10 precharges the power supply voltage VCC by the complementary precharge signal xdpbb, and between the operation switch unit 10 and the ground via the fuse unit PF. Connected to the address signal ADDR of the defective circuit to turn on the address input unit 20 for detecting the cutting state of the fuse unit PF, and the voltage value of one end of the operation switch unit 20 and the fuse unit PF. The latch unit 40 for stabilizing the output, the output unit 30 for outputting the stable value by the latch unit 40, and the sub-array block sharing the output value of the output unit 30 to be selected and outputted. And a block selector 60.

The block selector 60 is connected to a word line selector 50 for selecting whether to access the normal cells or the spare cells of the shared subarray blocks SB1 and SB2, respectively. .

Here, the word line selector 50 is activated by the positive signal to enable the spare word line SWL and the spare word line boot strapping circuit SPX and the negative signal to activate the normal word line NWL. Enabling consists of a normal wordline boot strapping circuit (NPX).

In this embodiment, the block selector 60 is provided so as to share the left and right subarray blocks SB1 and SB2 shown in FIG.

Referring to the operation of the repair unit made as described above are as follows.

When the complementary precharge signal xdpbb is input at a low potential, the operation switch unit 10 is turned on so that the power supply voltage VCC is applied to the fuse part PF. In this state, when the address signal ADDR is input to the address input unit 20, the NMOS transistor of the bit having the high potential value is turned on so that the power supply voltage VCC supplied through the operation switch unit 10 is turned on to supply the NMOS transistor. The pass is formed so that the potential of the node 'C' has a low potential. Therefore, the value of the node 'D' also becomes a low potential, and this value is stabilized by the latch unit 40 and is then inverted and outputted by the inverter 40 of the output unit 30 through the inverter. Maintains a low potential.

Then, the low potential value of the output unit 30 is inputted to the block selector 60, and according to the states of the first and second selected fuses 62 and 63 of the block selector 60, The sub-array blocks SB1 and SB2 are selected. In the normal state, the node 'D' has a low potential regardless of the cutting states of the first and second selected fuses 62 and 64. Will be maintained. Therefore, the word line selection unit 50 uses the normal word line boot strapping circuit NPX to activate the normal word line NWL in the word line selection unit 50 by the low potential value output from the block selection unit 60. It enables to access normal cells of left and right sub-array blocks SB1 and SB2.

In this state, if the fuse of the fuse part PF of the address corresponding to the case where a defect occurs in the memory cell of the right sub-array block SB2 is cut with a laser beam, the fuse part is operated through the operation switch part 10. The current path formed with the address input unit 20 through the PF is cut off so that the potential of the node 'C' becomes high potential. Therefore, the node 'D' also becomes a high potential, and this value is inverted by the inverter of the latch unit 40 to turn on the PMOS transistor so that the power source voltage stabilizes the node 'D' strongly to the high potential, and thus the inverter of the output unit 30. By inverting the value inverted by the latch unit 40 is outputted again.

This high potential value of the output unit 30 is inputted to the block selector 60, and the left and right sub-array blocks according to the states of the first select fuse 62 and the second select fuse 64 of the block selector 60. Since a defect has occurred in the memory cell of the right subarray block SB2, the first subselect block 62 cuts the second subselect block 64 so that the right subarray block SB2 selects a spare cell. ) Is maintained without cutting.

Then, since the first selection fuse 62 has been cut, the node 'E' has a low potential value, is multiplied by a high potential value of the node 'B', and a low potential value is output to the word line selection unit 50. The normal word line NWL is enabled by the normal word line boot strapping circuit NPX which is applied with a potential value to activate the negative signal, thereby allowing the left subarray block SB1 to access the normal cell.

However, since the second selection fuse 64 is not truncated, the node 'F' has a high potential value and is logically multiplied with the high potential value of the node 'B' to output a high potential value, thereby providing a high potential value to the word line selection unit 50. The spare word line SWL is enabled by the spare word line boot strapping circuit WPX which is applied and activated to the positive signal to operate the spare cell of the right subarray block SB2.

4 is a block diagram schematically illustrating a redundancy circuit of a memory device employing a repair circuit according to the present invention.

As shown here, it can be seen that the left and right subarray blocks SB1 and SB2 share one repair unit 5 in the center.

As described above, the present invention allows a repair unit existing in each sub-array block of a memory device to be shared by a predetermined sub-array block, and a sub-array block selection unit selects and repairs a defective sub-array block so that the overall chip area is increased. There is an advantage that can be reduced.

Claims (2)

In the repair circuit of a memory device having each repair unit for each sub-array block of the memory device, A block selector for sharing one repair unit for a plurality of subarray blocks, and selecting a subarray block to repair a plurality of subarray blocks as output values of the repair unit. Repair circuit of a memory device, characterized in that further comprises. The method of claim 1, wherein the block selector The repair circuit of the memory device, wherein the subarray block is selected by the first selection fuse and the second selection fuse.