KR19990002557A - Repair device for semiconductor memory devices - Google Patents

Abstract

The present invention relates to a repair apparatus for electrically repairing an existing fuse-cutting repair using an internal repair address latch signal pad by using a device that can electrically write and erase data, instead of a fuse. The repair fuse box includes a repair address path control means for controlling a repair address by operating on a signal received by a repair address latch signal pad, and a transistor gate potential during the repair address operation by latching an output signal of the repair address path control means. A repair address latch means, a first repair transistor that is turned off to an output signal of the repair address latch means to maintain a potential on a common node, and is connected between a terminal of one side of the first repair transistor and a ground voltage terminal and repaired Turn the dress - and a second transistor being turned on repair.

Description

Repair device for semiconductor memory devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair apparatus for a semiconductor memory device, and in particular, replaces a repair fuse with an element capable of writing and erasing data electrically, and stores a repair address for receiving a repair address latch signal pad that exists only on a wafer. The present invention relates to a repair apparatus that stores a device and repairs a corresponding cell by controlling a transistor when a repair address is received.

If any one of the many fine cells is defective, DRAM (Dynamic Random Access Memory, hereinafter referred to as DRAM) cannot be handled as a defective product. However, as DRAM manufacturing technology improves, there is a high probability that defects will occur only in a small number of cells, but discarding them as defective products is an inefficient treatment method that lowers the yield. Therefore, in this case, a method of increasing the yield by adopting a spare memory cell previously installed in the DRAM is replaced. As the area of the chip increases due to the provision of a spare circuit, the increase in the test required for defect repair is a problem, which has not been practically used in the logic LSI, but the area of the chip is relatively small in DRAM, and thus, it is adopted from 64K to 256K DRAM. .

Redundancy cells of memory are installed by sub-array blocks. Spare rows and spare columns are installed in every 256K cell array to replace defective memory cells with spare memory cells in row / column units. do. When the wafer process is completed, the internal circuit is programmed to select a defective memory cell through a test and replace the corresponding address with the address signal of the spare cell. Therefore, when an address corresponding to the defective line is received in actual use, a spare is provided instead. The selection changes to the line. This program method includes an electric fuse method in which an overcurrent is melted and blown, a method of burning a fuse with a laser beam, a method of shortening a junction with a laser beam, and a program in an EPROM memory cell. Among these methods, the laser cutting method is widely used because of its simple, reliable and easy layout, and polysilicon wiring or metal wiring is used as the fuse material.

1 is a circuit diagram illustrating a repair apparatus according to the prior art, which is a normal operation when a common node is precharged by a Lars signal (/ RAS) and an address is input to discharge the common node. Therefore, a low signal is output to the output terminal of the repair driver.

If the fuse connected to the transistor receiving the specific address is cut off, when the address is received, the common node maintains the precharged high signal as it is, and outputs a high signal to the repair driver output terminal. .

As described above, a repair method is conventionally used in which a repair fuse is formed and a fuse having a repair address is cut by a laser beam.

Therefore, a repair failure may occur due to the cutting of the fuse, a considerable repair time is required, and the repair mask increases the cost of the repair mask. In addition, ESI key and fuse open area used as repair fuse cutting reference coordinates are likely to penetrate moisture and may cause PCT fail.

In addition, the cost of purchasing, maintaining, and repairing the fuse cutting equipment is also burdensome.

Therefore, the present invention was devised to solve the above-mentioned problem, and it is possible to repair the existing fuse cutting method by using an internal repair address latch signal pad instead of the fuse using an element that can write and erase data electrically instead of the fuse. It is an object of the present invention to provide a repair apparatus.

1 is a repair circuit diagram according to the prior art.

2 is a repair circuit diagram according to an embodiment of the present invention.

FIG. 3A is a circuit diagram illustrating an example of the repair address path controller of FIG. 2. FIG.

3B is a circuit diagram illustrating an embodiment of the repair address latch unit of FIG. 3.

* Description of the symbols for the main parts of the drawings *

10: repair fuse box 20: repair address latch unit

30: repair address path control unit 40: precharge unit for repair

50: repair driver

RPAD: Repair Address Latch Signal Pad

xdp: roo decoder precharge signal

The repair apparatus of the present invention for achieving the above object is a repair precharge unit for outputting a power supply voltage by operating a low decoder precharge signal, a repair driver connected to the repair precharge unit output terminal, and the repair A repair fuse box having a plurality of repair fuse boxes connected between an output terminal of the charge unit and the respective address input terminals, wherein the repair fuse box operates on a signal received by the repair address latch signal pad to transmit a repair address; A repair address latch means for latching an output signal of the repair address path control means to control a gate potential of the transistor, and a first repair transistor turned off to an output signal of the repair address latch means to maintain a potential on a common node. And the first Coupled to one terminal of the transistor pair being characterized by a second transistor for receiving a repair repair address.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a repair circuit diagram according to an embodiment of the present invention. The repair precharge unit 40 is operated by a low decoder precharge signal xdp and outputs a power supply voltage to the first node N1. A plurality of repair fuse boxes 10 connected between a first node N1 and a repair address latch signal pad RPAD to receive an address, and a repair driver connected to the first node N1 to output a repair signal. It consists of.

The repair precharge unit 40 includes the first PMOS transistor MP1.

The repair fuse box 10 is turned on to the signal received by the repair address latch signal pad RPAD to transmit a repair address to the repair address latch unit 20, and the repair address path controller 30. The repair address latch unit 20 latches an output signal of the controller 30 to turn off the first repair transistor when a repair address is received, and is turned off to the output signal of the repair address latch unit 20. The first repair transistor maintains a potential on the first node N1, and one terminal is connected to one terminal of the first repair transistor, and a second repair transistor receives a repair address through a gate.

In the repair fuse box 10, the same circuit having such a configuration exists by the number of addresses.

The repair driver 50 includes a first inverter IV1 for inverting a potential on a first node N1, a gate is connected to an output terminal of the first inverter IV1, and a power supply voltage is applied to the first node N1. And a second PMOS transistor MP2 outputting the PMOS transistor MP2 and a second inverter IV2 inverting the output signal of the first inverter IV1 and outputting a repair signal.

FIG. 3A illustrates an embodiment of the repair address path control unit shown in FIG. 2 and has a configuration of controlling a repair address by a transmission gate operated by a signal received by a repair address latch signal pad RPAD. .

Referring to the operation, when the signal received by the repair address latch signal pad RPAD is low, the transmission gate is turned on so that the repair address is input to the repair address latch unit 20 and stored.

This is called a repair mode setting operation, in which a transmission gate is turned on by a low signal received by a repair address latch signal pad RPAD, and a repair address is transferred to the repair address latch unit 20 and stored thereafter. The signal received by the repair address latch signal pad RPAD remains high.

FIG. 3B is a circuit diagram illustrating an example of the repair address latch unit shown in FIG. 2, and is operated by a signal received by a repair address latch signal pad RPAD to output an output signal of the repair address path controller 30. Latch and control the corresponding repair transistor.

The configuration consists of a control inverter, an inverting inverter and a buffer.

In the operation, when the low signal is applied to the first repair address latch signal pad RPAD, the repair address path controller 30 is turned on to receive the repair address. At this time, the control inverter is turned on so that the repair address is inverted, output to the inverting inverter, and the inverted repair address is latched.

This is referred to as a repair mode setting operation as described above.

Since the signal received by the repair address latch signal pad RPAD remains high, the repair address path control unit 30 is turned off so that the repair address cannot be transmitted to the repair address latch unit 20. However, the repair address stored in the repair mode setting operation allows the repair operation to be performed by controlling the corresponding transistor through the turned-on buffer.

Now, a description of the operation of the present invention made up of Figures 2, 3a and 3b will be described in more detail.

The low decoder precharge signal xdp becomes low so that the first node N1 (generally referred to as a common node) is high charged.

If the data of the repair address latch unit 20 that receives AX01 (3) of FIG. 2 is stored low (that is, the inverted value of the repair address is stored during the repair mode setting operation), the repair address latch signal pad RPAD Signals received are high, AX01 (0) is low, AX01 (1) is low, AX01 (2) is low, AX01 (3) is high, AX23 (0: 3) is low, AX45 (0: 3) If this row, AX67 (0: 3) is low, all the AX addresses are low, so all transistors connected to the ground terminal, that is, the second repair transistor, are turned off, and only AX01 (3) is high. For this reason, only the second repair transistor connected thereto is turned on.

However, since the repair address is stored low in the repair address latch section 20 corresponding to AX01 (3), the first repair transistor is turned off and is precharged on the first node N1. The signal remains intact and outputs a high, indicating to the internal address logic that it is a repair address.

Comparing the present invention described so far with the conventional circuit, the conventional circuit is to configure the fuse in polysilicon and to cut the fuse according to the repair address.

The present invention uses a transistor instead of a fuse and uses a device for controlling the gate voltage of the transistor to have the same function as the fuse.

When the repair method according to the present invention described above is implemented in a semiconductor memory device, the repair time can be shortened, the repair yield can be improved, and the moisture penetration factor into the ESI key and the repair fuse open region can be eliminated.

In addition, there is no need for a repair mask and repair cutting equipment, and there is an effect that a repair failure does not occur due to a fuse cutting.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (3)

A repair apparatus for a semiconductor memory device having a function of receiving a plurality of addresses and repairing defective cells, A repair precharge unit operating by a low decoder precharge signal and outputting a power supply voltage; A repair driver connected to the repair precharge unit output terminal; A plurality of repair fuse boxes connected between an output terminal of the repair charge unit and a respective address input terminal; The repair fuse box may include: a repair address path control unit configured to transmit a repair address by operating on a signal received by the repair address latch signal pad; A repair address latch means for latching and controlling an output signal of the repair address path control means; A first repair transistor controlled by an output signal of the repair address latch means to maintain a potential of the repair precharge part output terminal; And a second repair transistor connected to one terminal of the first repair transistor and receiving a repair address. The method of claim 1, The repair address path control means is turned on by a predetermined signal received by the repair address latch signal pad during a repair mode setting operation to transfer a repair address to the repair address control means. A repair apparatus for a semiconductor memory device, which is turned off during other operation to block the repair address. The method of claim 1, The repair address latch means inverts and stores an output signal of the repair address path control means in a repair mode setting operation. The repair apparatus of a semiconductor memory device, wherein the repair is performed by controlling the transistor gate potential during the repair operation.