KR100586068B1 - Repair circuit of a memory device - Google Patents

Abstract

The present invention relates to a repair circuit of a memory device in which a repair circuit having a priority can be repaired again with a new spare cell when a fault occurs in the normal cell and the spare cell is repaired again. A first fuse box 10 and a second fuse box 12 for receiving an address and outputting whether a preset bad address is equal to the input address; When the output value A1 of the first fuse box 10 indicates a bad address, the first spare cell enable signal spr_en1 for replacing the first spare cell 32 is output, and the second fuse box 12 is output. Outputs a second spare cell enable signal spr_en2 for replacing the second spare cell 34 when the output value A2 indicates a bad address, and outputs the first fuse box 10 and the second fuse box 12. The second spare cell enable signal spr_en2 for disabling the first spare cell enable signal spr_en1 and replacing it with the second spare cell 32 when both of the output values A1 and A2 of the reference value indicate a bad address. If the repair by the first fuse box 10 is made of a control block 20 for outputting the same, the same bad address is set in the second fuse box 12 to perform the repair again, thereby improving the reliability of the product. Can be improved.

Dual repair sparecell priority failure

Description

Repair circuit of memory device {REPAIR CIRCUIT OF A MEMORY DEVICE}             

1 is a block diagram illustrating a repair circuit of a conventional memory device.

FIG. 2 is a circuit diagram illustrating a part of the control block of FIG. 1.

3 is a circuit diagram showing a repair circuit of the memory device according to the present invention.

4 is a circuit diagram showing another embodiment of a repair circuit of a memory device according to the present invention.

   -Explanation of symbols for the main parts of the drawings-

10: first fuse box 12: second fuse box

20: control block 32: first spare cell

34: second spare cell

The present invention relates to a repair circuit of a memory device, and more particularly, a new spare cell is again provided by a repair circuit having priority when a fault occurs in the normal cell and the spare cell is defective again. The present invention relates to a repair circuit of a memory device that can be repaired by a memory device.

If any one of the many fine cells in the memory device is defective, it cannot be used as a DRAM and thus is treated as a defective product. However, as the density of DRAM increases, the probability of defects occurring in only a small number of cells is high. However, discarding them as defective products is an inefficient treatment method that lowers the yield. Therefore, in this case, a method of increasing yield by replacing defective cells by using spare memory cells installed in DRAM in advance is adopted.

As the repair circuit that replaces the defective cell with the spare cell increases, the area of the chip and the increase of the test required for the defect repair become a problem. However, since the area of the chip does not increase much in DRAM, it is adopted from 64K to 256K DRAM in earnest. It is becoming.

The repair circuit of the memory cells is installed for each sub-array block, and a spare ROW and a COLUMN are installed in advance so that a defect occurs and a memory cell determined to be defective is replaced with a spare memory cell in ROW / COLUMN units. When the wafer processor is terminated, the internal circuit performs programming that selects the defective memory cell through the test and replaces the corresponding address with the address signal of the spare cell. Therefore, if an address corresponding to the defective line is input during actual use, The selection changes to a spare line.

This programming method includes an electric fuse that melts and blows a fuse due to overcurrent, a blown fuse by a laser beam, a short circuit by a laser beam, and a program by using an EPROM memory cell. Among these methods, the laser cutting method is widely used because of its simple, reliable and easy layout, and polysilicon wiring or metal wiring is used as the fuse material.

1 is a block diagram illustrating a repair circuit of a conventional memory device.

As shown here, a plurality of fuse boxes 10 and 12 which receive the address add_in and compare whether the input address add_in is a bad address or a normal address and output the same are compared with a preset bad address. 14, 16 and a plurality of fuse boxes (10, 12, 14, 16) output value (A1, A2, An-1, An) is received, if any one of the spare cell 30 is selected if the match the bad address It consists of a control block 20 to adjust to.

In the repair circuit, the input address add_in is applied to all the fuse boxes 10, 12, 14, and 16. At this time, each of the fuse boxes 10, 12, 14, and 16 cuts the fuses installed therein, tests the memory cells, and sets a defective address indicating a cell where a defect occurs according to a test result. Therefore, when the address (add_in) input from the outside is the same as the bad address set in the fuse boxes 10, 12, 14, and 16, the signal (A1, A2, An-1, An) indicating that the input address is a bad address. Will print Then, the values (A1, A2, An-1, An) output from the fuse boxes 10, 12, 14, and 16 in the control block 20 receiving the signals A1, A2, An-1, An are When any one of the addresses indicates a defective address, the spare enable signal spr_en is output to designate the spare cell 30.

The fuse boxes 10, 12, 14, and 16 mentioned above serve to distinguish between the normal address and the repair address. When one node of the fuse is precharged to a high potential, it is discharged to a low potential when the normal address comes in. When the repair address comes in, the corresponding fuse is cut in advance, so the discharge pass disappears to maintain the high potential.

That is, the outputs of the fuse boxes maintain the high potential during repair.

FIG. 2 is a circuit diagram illustrating a part of the control block of FIG. 1.

As shown here, (a) is a spare cell when the address (add_in) input by sharing the signals (A1, A2) output from the two fuse boxes match any one of the bad addresses set in the two fuse boxes The spare 30 is configured to output the spare enable signal sp_en to be replaced.

In addition, (b) share the signals A1, A2, A3, A4 output from the four fuse boxes, the spare cell 30 when the input address coincides with any one of the bad addresses set in the four fuse boxes. The spare enable signal (spr_en) is output so that it can be replaced with.

In this way, after testing the memory cell in advance, in order to repair the defective memory cell to the spare cell, an address indicating a defective memory cell is set in the fuse box, and the input address corresponds to a bad address set in the fuse box. If there is a match, the spare cell is repaired.

However, if a defective memory cell is repaired as a spare cell, but the defective spare cell also has a defect, the repair circuit can be repaired again by a repair circuit capable of performing only one repair to one address. It is impossible to do this, and eventually this memory device is judged to be defective and has a problem in that the yield falls.

The present invention was made to solve the above problems, and an object of the present invention is to perform a repair on a defective memory cell by performing a repair once, and then perform a repair on a previously repaired signal. The present invention provides a repair circuit of a memory device capable of performing a plurality of repairs by operating first.

The present invention for realizing the above object comprises a first fuse box and a second fuse box for receiving an address and outputting whether the preset bad address is equal to the input address; Outputting the first spare cell enable signal for replacing the first spare cell when the output value of the first fuse box indicates the bad address, and replacing the second spare cell when the output value of the second fuse box indicates the bad address. Outputs the enable signal to the second spare cell for the purpose of disabling the first spare cell enable signal and replacing the second spare cell when the output values of the first fuse box and the second fuse box both indicate a bad address. And a control block for outputting the second spare cell enable signal.

According to the present invention as described above, when different defective addresses are set in the first fuse box and the second fuse box, the first spare cell enable signal is output when the input address coincides with the defective address set in the first fuse box. When the input address coincides with the bad address set in the second fuse box, the second spare cell enable signal is output. If the same address is set in the first fuse box and the second fuse box, and the input address coincides with the bad address set in the first fuse box and the second fuse box, the first spare cell enable signal is displayed. Enable the second spare cell enable signal to be output, and when the memory cell corresponding to the defective address set in the first fuse box is repaired to the first repair cell, when the first repair cell fails, the second fuse box In addition, it is possible to enable the second repair cell by disabling the first repair cell enable signal for enabling the first repair cell so that the same defective address can be repaired by the second repair cell.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

3 is a circuit diagram showing a repair circuit of the memory device according to the present invention.

As shown here, a test is performed in advance by receiving an address (add_in) to set a bad address indicating a defective cell by cutting a fuse to determine whether the input address (add_in) is a bad address or a normal address. The first fuse box 10 and the second fuse box 12 outputting the same by comparison are installed.

The first spare cell enable signal for receiving the output values of the first fuse box 10 and the second fuse box 12 to enable the first spare cell 32 and the second spare cell 34 ( A control block 20 for outputting spr_en1 and the second spare cell enable signal spr_en2 is provided.

The control block 20 is used when the output value A1 of the first fuse box 10 indicates a bad address when different defective addresses are set in the first fuse box 10 and the second fuse box 12. The second spare cell 34 when the first spare cell enable signal spr_en1 is output for replacing the first spare cell 32 and the output value A2 of the second fuse box 12 indicates a bad address. The second spare cell enable signal spr_en2 for outputting is output.

Meanwhile, the same defective address is set in the first fuse box 10 and the second fuse box 12 so that the output values A1 and A2 of the first fuse box 10 and the second fuse box 12 are both defective addresses. When indicating, the second spare cell enable signal spr_en2 for disabling the first spare cell enable signal spr_en1 and replacing the second spare cell 34 with the second spare cell 34 is output.

That is, the first spare cell enable signal spr_en1 has an output value of the north gate NOR that receives the inverted output / A1 of the first fuse box 10 and the output of the second fuse box 12 as inputs. .

The second spare cell enable signal spr_en2 has a value inverted twice of the output value A2 of the second fuse box 12.

Referring to the operation of the present invention made as described above are as follows.

When different defective addresses are set in the first fuse box 10 and the second fuse box 12, the first fuse when the input address add_in matches the bad address set in the first fuse box 10. The output A1 of the box 10 becomes high potential, and the output A2 of the second fuse box 12 becomes low potential. Therefore, in the control block 20 receiving the output value A1 of the first fuse box 10 and the output value A2 of the second fuse box 12, the inverted output signal of the first fuse box 10 (/ A1) and the output signal A2 of the second fuse box 12 are logically operated by the NOR gate NOR to output the first spare cell enable signal spr_en1 at high potential, and the second spare cell enable signal. Spr_en2 inverts the output signal A2 of the second fuse box 12 twice and outputs the low potential to enable the first spare cell 32.

When the input address add_in coincides with the bad address set in the second fuse box 12, the output A2 of the second fuse box 12 becomes a high potential, and the first fuse box 10 The output A1 becomes low potential. Therefore, in the control block 20 receiving the output value A1 of the first fuse box 10 and the output value A2 of the second fuse box 12, the inverted output signal of the first fuse box 10 (/ A1) and the output signal A2 of the second fuse box 12 are logically operated by the NOR gate NOR to output the first spare cell enable signal sp_en1 at low potential, and the second spare cell enable signal. Spr_en2 inverts the output signal A2 of the second fuse box 12 twice and outputs it at high potential to enable the second spare cell 34.

On the other hand, if a defect occurs in the memory cell indicated by the bad address set in the first fuse box 10 and the repair is performed in the first spare cell 32, but the defect occurs in the first spare cell 32, the second fuse box. In (12), the same address as the bad address set in the first fuse box 10 is set.

When the same bad address is set in the first fuse box 10 and the second fuse box 12, the input address add_in is simultaneously input to the first fuse box 10 and the second fuse box 12. When the first fuse box 12 and the second fuse box 12 both coincide with the bad address, and outputs a high potential value.

Then, in the control block 20 that receives the output value A1 of the first fuse box 10 and the output value A2 of the second fuse box 12, the inverted output signal of the first fuse box 10 (/ A1) and the output signal A2 of the second fuse box 12 are logically operated by the NOR gate NOR, and the first spare cell 32 is output by outputting the first spare cell enable signal spr_en1 at a low potential. The second spare cell enable signal spr_en2 disables the second spare cell 34 by inverting the output signal A2 of the second fuse box 12 at a high potential and disabling it twice.

Therefore, when a defect occurs in the first repaired first spare cell 32, when the second repair is performed at the same address, the first spare cell 32 is disabled and repaired after repairing to the second spare cell 34. When the repair fails, the repair can be performed once again.

4 is a circuit configuration diagram of a NAND gate of a repair circuit of the memory device according to the present invention.

As shown here, the first spare cell enable signal spr_en1 receives the output A1 of the first fuse box 10 and the inverted output (/ A2) of the second fuse box 12 as inputs. It has an inverted output value of (NAND).

The second spare cell enable signal spr_en2 has a value inverted twice of the output value A2 of the second fuse box 12.

Therefore, when the output value A1 of the first fuse box 10 is high potential and the output value A2 of the second fuse box 12 is low potential, the inverted output value of the inverted second fuse box 12 (/ A2). ) And the output value A1 of the first fuse box 10 are logically operated by the NAND gate NAND to output a low potential, and the value is inverted again to output the first spare cell enable signal spr_en1. You have a high potential. The second spare cell enable signal spr_en2 inverts the output signal A2 of the second fuse box 12 twice to output a low potential value. Accordingly, the first spare cell 32 is in an enabled state and the second spare cell 34 is in an disabled state.

In addition, when the output value A1 of the first fuse box 10 is low potential and the output value A2 of the second fuse box 12 is high potential, the inverted output value of the inverted second fuse box 12 (/ A2) And the output value A1 of the first fuse box 10 is logically operated by the NAND gate NAND, and the high potential is output, and the value is inverted again so that the first spare cell enable signal spr_en1 is Will have a low potential. The second spare cell enable signal spr_en2 inverts the output signal A2 of the second fuse box 12 twice to output a high potential value. Thus, the first spare cell 32 is in a disabled state and the second spare cell 34 is in an enabled state.

Meanwhile, when the output value A1 of the first fuse box 10 and the output value A2 of the second fuse box 12 have high potentials, the inverted output value (/ A2) and the first fuse box of the second fuse box 12 are high. Since the output value A1 of (10) is logically operated by the NAND gate NAND and the low potential is output, and the value is inverted and output again, the first spare cell enable signal spr_en1 has a low potential and is One spare cell 32 is to be disabled. In addition, the second spare cell enable signal spr_en2 inverts the output signal A2 of the second fuse box 12 twice to output a high potential value to enable the second spare cell 34.

Therefore, when the repair is performed by the first fuse box 10 and fails, the same defective address may be set in the second fuse box 12 to perform the repair again.

As described above, in the present invention, when a defective cell occurs in the normal cell and the spare cell is repaired, the spare cell can be repaired again with a new spare cell by a repair circuit having priority. There is a growing advantage.

In addition, even if a defect occurs several times, it can be repaired, there is an advantage that can improve the reliability of the product.

Claims (4)

delete A first fuse box and a second fuse box which receive an address and output whether the preset bad address is identical to the input address; Outputs a first spare cell enable signal for replacing the first spare cell when the output value of the first fuse box indicates a bad address; and outputs a first spare cell enable signal for replacing the first spare cell, and outputs a bad address to the second spare cell when the output value of the second fuse box indicates a bad address. Outputs a second spare cell enable signal for replacement, and disables the first spare cell enable signal when both output values of the first fuse box and the second fuse box indicate a bad address. And a control block for outputting a second spare cell enable signal for replacement, And the first spare cell enable signal has an output value of a nor gate receiving an inverted output of the first fuse box and an output of the second fuse box as inputs. A first fuse box and a second fuse box which receive an address and output whether the preset bad address is identical to the input address; Outputs a first spare cell enable signal for replacing the first spare cell when the output value of the first fuse box indicates a bad address; and outputs a first spare cell enable signal for replacing the first spare cell, and outputs a bad address to the second spare cell when the output value of the second fuse box indicates a bad address. Outputs a second spare cell enable signal for replacement, and disables the first spare cell enable signal when both output values of the first fuse box and the second fuse box indicate a bad address. And a control block for outputting a second spare cell enable signal for replacement, And the first spare cell enable signal has an inverted output value of the NAND gate that receives the output of the first fuse box and the inverted output of the second fuse box. The enable signal of claim 2 or 3, wherein the second spare cell is enabled. And a value inverted twice of an output value of the second fuse box.

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