KR20010008437A - Row redundancy circuit of memory device - Google Patents

Abstract

PURPOSE: A row redundancy circuit comprising a control circuit for selecting a normal word line and a redundancy word line without cutting off fuses in the row redundancy circuit is provided. CONSTITUTION: A row redundancy circuit in a semiconductor device includes a control circuit(D) for selecting a row redundancy word line without cutting off fuses by using a test signal when testing the semiconductor device. The control circuit has inverters(15-16) and a NOR gate. The control circuit inputs a test signal(TEST_Redun) and generates the first signal(Eval) and the second signal(Eval_NRE). When the test signal is a logic low, the first and second signals have the same voltage level. When the test signal is a logic high, the second signal becomes a logic low and then a redundancy word line is driven. When the first signal is a logic high and the second signal is a logic low, the redundancy word line only is forcibly driven regardless of a normal word line and a cut-off of the fuses.

Description

Low Redundancy Circuit in Memory Devices

The present invention relates to a low redundancy circuit of a memory device, and more particularly, to enable redundancy word lines to be tested during a probe test of a memory device, thereby checking the operation of the redundancy word lines, and then improving efficiency in replacing the normal word lines. The present invention relates to a low redundancy circuit of a memory device in which a control circuit part is added to maximize.

Since semiconductor devices have a big impact on reliability by each process element in the manufacturing stage, they are adjusted to form desired shapes, doping states, etc. through various experiments and inspections at each stage of the manufacturing process, but very minute errors in the manufacturing process Since each one can greatly affect the operation of the semiconductor device, the manufactured semiconductor device is inspected whether it is manufactured as designed through an inspection step using equipment for testing (probe station, tester, etc.).

In this way, if any defect is found in the inspection step, it is not processed as a DRAM and thus it is treated as a defective product. However, as the density of DRAM increases, the probability of defects occurring in only a small number of cells is high. However, discarding them as defective products is an inefficient treatment method that lowers the yield. Therefore, in this case, a method of increasing the yield by adopting a redundant memory cell installed in the DRAM in advance is replaced.

The redundancy circuit of the memory device is installed for each sub-array block, and a spare ROW and a COLUMN are installed in advance so that a defect occurs and a defective memory cell is replaced with a redundancy memory cell in ROW / COLUMN units. When the wafer processor is terminated, the internal circuit performs programming that selects the defective memory cell through the test and replaces the corresponding address with the address signal of the spare cell. Therefore, when an address corresponding to the defective line is input during actual use, a spare is instead provided. The selection changes to the line. This programming method includes an electric fuse that melts and blows a fuse due to overcurrent, a fuse that is blown out by a laser beam, a short circuit by a laser beam, and a program by using an EPROM memory cell. Among these methods, the method of cutting with a razor is simple and reliable, and the layout is widely used, and polysilicon wiring or metal wiring is used as the fuse material.

1 to 3 are circuit diagrams and timing diagrams showing a low redundancy circuit of a conventional memory device.

The output value "Eval" of FIG. 1 affects the output value "NRE" of FIG. 2. When the redundancy word line is selected after cutting the fuse, the NRE is low potential and the NRE is high potential when the normal word line is selected. When the NRE is at low potential, as shown in FIG. 3, the corresponding redundancy word line is selected from four redundancy word lines RWL <0>, RWL <1>, RWL <2>, and RWL <3> by Bk_SELi. However, as shown in the drawing, when the fuse is not blown, the NRE becomes a high potential, so the NOR gate output value of "ND23" is always low, and the redundancy word lines RW <0>, RWL <1>, and RWL <2 , RWL <3>) are not selected.

Therefore, since the redundancy cell cannot be tested unless the low fuse corresponding to the redundancy address is disconnected, it is not possible to know whether the redundancy cell has failed, and the decrease in yield and test time caused by laser repair due to the redundancy cell failure. The problem is that it brings waste.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a control circuit for selecting and testing normal word lines and redundancy word lines without cutting fuses in a low redundancy circuit of a memory device. In addition, the present invention provides a low redundancy circuit of a memory device.

1 to 3 are circuit diagrams and timing diagrams showing a low redundancy circuit of a conventional memory device.

4 to 7 are circuit diagrams and timing diagrams showing a low redundancy circuit of the memory device according to the present invention.

According to an aspect of the present invention, a low redundancy circuit of a semiconductor device for selecting a low redundancy word line may further include a control circuit configured to select a low redundancy word line without cutting a fuse during a test. It is characterized by.

Therefore, even when the fuse is not cut as the test signal is input during the test, a low redundancy word line can be selected so that the redundancy cell can be tested to replace the stable redundancy cell when a normal cell fails.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

4 to 7 are circuit diagrams and timing diagrams showing a low redundancy circuit of the memory device according to the present invention.

The portion "D" in FIG. 4 is a control circuit unit according to the present invention, and separates the "Eval" signal and the "Eval_NRE" signal so that it is controlled by the "TEST_Redun" signal.

When "TEST_Redun" is at low potential, the NOR gate of NR48 operates as an inverter, so that "Eval" and "Eval_NRE" maintain the same potential. On the other hand, if a high potential is applied to "TEST_Redun" in the test mode, "Eval_NRE" becomes a low potential to force the "NRE" of FIG. 5 to a low potential to drive the redundancy word line.

That is, if "Eval" is high potential and "Eval_NRE" is high potential, it is possible to drive redundancy word lines after normal word line or fuse disconnection, whereas "Eval" is high potential and normal word line if "Eval_NRE" is low potential. Only the redundancy word line can be forcibly driven regardless of the fuse disconnection or the like.

5 is a circuit for selecting a normal word line and a redundancy word line when a row address is input. When "Eval_NRE" is a high potential in a state in which a fuse is not disconnected, the NMOS of "G24" is turned on. When the NMOS transistor is turned on by the corresponding row address value among GLAX01 <0: 3>, GLAX45 <0: 3>, GLAX67 <0: 3>, GLAX8 <0: 1>, and L_BARD01_ij, the NMOS transistor is turned into a high potential state. do.

When "Eval_NRE" becomes high potential to select the redundancy word line while the fuse is blown, the NMOS transistor of "G24" is turned on. When the low address equal to the cut-off address comes in, the fuse is precharged because the fuse is blown. Since no voltage is discharged, the NRE is brought to a low potential to drive the redundancy word line.

Also, if you select the redundancy word line without cutting the fuse, that is, for redundancy low test, if you set "TEST_Redun" to the high potential state, "Eval_NRE" transitions to low potential and the PMOS transistor with "P25" turns on and "G24" By turning off the NMOS transistor, it forces the NRE to a low potential, allowing only the redundancy word line to be selected regardless of the fuse blown or normal row address.

FIG. 6 is a circuit for selecting and driving a corresponding redundancy word line, but part 'B' is a control circuit added in the present invention.

As a control circuit unit according to the present invention, a TEST_NRE <0: 3> signal is input to the NOR gate of "ND23" which receives the conventional NRE <0: 3> and NR45 signals, thereby selecting a redundancy word line without cutting the fuse. RWL <0: 3> can be driven.

In other words, if "TEST_Redun" is high potential and GLAX01 <0: 3> of the redundancy word line row address to be tested is high potential, it becomes high potential in "ND64" and inputs the "ND23" Norgate with low potential value through the inverter. do.

This is because the redundancy word line is driven only when the output of "ND23" is at high potential, but TEST_NRE <0: 3> NRE <0: 3> and NR45 are all at low potential to enter the NOR gate input of "ND23". Because it will print.

The operation of the above control circuit is shown as follows.

TEST_Redun GLAX01 ND64 TEST_NRE 0 0 One 0 0 One One 0 One 0 0 One One One One 0

However, as shown in Table 1, when "TEST_Redun" is high potential and "GLAX01" is low potential, only normal word lines are accessed because "TEST_NRE" becomes high potential.

As described above, the present invention adds a control circuit for accessing the redundancy word line by applying a test signal to the low redundancy circuit of the memory device without cutting the fuse, thereby making it possible to check the error of the redundancy cell early. Yield can be maximized.

In addition, by testing the redundancy cell in advance, there is an advantage in that the reliability of the memory device can be improved by replacing the normal redundancy cell when an error occurs in the normal cell.

Claims (2)

In a low redundancy circuit of a semiconductor device for selecting a low redundancy word line, Control circuit part to select low redundancy word line without cutting fuse with test signal input during test Low redundancy circuit of a semiconductor device, characterized in that further comprises. The method of claim 1, wherein the control circuit unit A low redundancy circuit of a semiconductor device, comprising a test signal, a redundancy word line, a signal for selecting a normal word line, and a row address signal.