KR20000010368A - Repair address detection circuit - Google Patents

Abstract

PURPOSE: A repair address detection circuit is provided to economize the time and expense that is needed to confirm a repaired address in a repair confirming operation of a semiconductor memory device. CONSTITUTION: The repair address detection circuit comprises: a memory cell array(11) driven by outputs of a row decoder(8) and a column decoder(9); a state machine(1) for outputting a command signal after receiving an external signal determining an operation of a DRAM(Dynamic Random Access Memory); a row path block(2) which supplies a timing signal to the row decoder(8) to select at least a word line among the memory cell array; a column path block(3) which supplies a timing signal to the column decoder(9) to select at least a column line among the memory cell array; a first fuse block(4) which determines, by using a fuse, a redundancy address capable of replacing a defective row address(A) cell by a redundancy cell when there is a cell defect in the row address(A); a second fuse block(5) which determines, by using a fuse, a redundancy address capable of replacing a defective column address(A) cell by a redundancy cell when there is a cell defect in the column address(A); a mode register(6) which operates a test mode for testing after manufacture; and a redundancy address detection circuit(7) which stops an input/output operation and outputs a predetermined signal to a data input/output buffer(12) when a repaired address is applied in a row or column active operation of test mode.

Description

Repair address detection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair address detection circuit, and more particularly, to a repair address detection circuit capable of detecting a repaired address of a semiconductor memory device and a repaired address as an electrical signal.

In general, semiconductor devices are fabricated to test for defects in a circuit. In particular, when a fault occurs in a circuit, a spare redundancy cell made in advance is used to replace (repair) the defective cell.

That is, when a redundant add program device is programmed in an operation of cutting by a laser, it is necessary to determine whether a redundant operation has been performed for a certain address in the process of product development and analysis. do.

In a conventional test method for detecting a repaired address in a test process for such a semiconductor device, a worker directly checks whether a repair fuse is blown. In this case, it is possible to check in the wafer state, but not in the package state. In addition, when checking in a wafer state, it takes a lot of time to check the repaired address, resulting in a large cost loss.

Accordingly, an object of the present invention is to provide a repair address detection circuit that can solve the above-mentioned disadvantages by configuring a redundancy address detection circuit inside the device to confirm the repaired address of the semiconductor memory device.

The repair address detection circuit according to the present invention for achieving the above object is a memory cell array driven according to the output of the row decoder output and the column decoder supplied through the input and output gates, and an external signal for determining the operation of the DRAM as an input. A state machine that outputs a command signal, a low pass block that provides a timing signal to the row decoder to select at least one word line in the memory cell array, and at least one column in the memory cell array A column pass block for providing a timing signal to the column decoder, a first fuse block for determining a redundancy address that can be prepared by selecting a fuse so as to replace a redundancy cell when one row address cell fails; If any column address cell fails Performs a second fuse block for determining a redundancy address from which a fuse can be prepared and selected for replacement with a redundancy cell, and a test mode designated to perform post-manufacturing inspection to perform a purpose other than the normal operation of the DRAM. And a redundancy address detecting circuit for stopping an input / output operation and outputting a predetermined signal to a data input / output buffer when a repaired address is applied during a row or column active operation in the test mode.

1 is a repair address detection circuit diagram in accordance with the present invention.

FIG. 2 is a detailed circuit diagram of the redundancy address detection circuit of FIG. 1. FIG.

<Explanation of symbols for the main parts of the drawings>

1: address input buffer 2: pre-decoder

3: repair address selection circuit 11 and 14: fuse circuit

12, 15 and 13, 16: First and second drive

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a repair address detection circuit diagram according to the present invention.

The memory cell array 11 driven in accordance with the output of the row decoder 8 and the output of the column decoder 9 supplied through the input / output gate 10 and an external signal for determining the operation of the DRAM are input. A state path 1 for outputting a command signal and a low path for providing a timing signal to the row decoder 8 for selecting at least one word line in the memory cell array 11. Block 2 and column path block 3 for providing a timing signal to the column decoder 9 for selecting at least one column in the memory cell array 11. And a first fuse block 4 for determining a redundancy address in which a fuse can be prepared and selected so that a row cell A can be replaced by a redundancy cell when one of the row address A cells fails, and either column address A If a cell fails A second fuse block 5 for determining a redundancy address that can be prepared by selecting a fuse to be replaced with a dungeon cell, and designated to perform post-manufacturing inspection to perform a predetermined purpose rather than a normal operation of the DRAM. A mode register 6 that performs a test mode, and when a repaired address is applied during a low or column active operation during the test mode, stops the input / output operation and outputs a signal to the data input / output buffer 12. It is composed of a redundancy address detection circuit 7.

The word line Row constituting the memory cell array 11 is composed of two parts. One is a normal word line, and the selected operation is performed using a row address signal input during normal operation. The other is a redundancy word line. When the address input at the input of a specific address is a predetermined address (address programmed in a fuse block), the normal word line is not selected when a specific address is input in a low cycle operation. Instead, the redundancy word line is selected.

In addition, the first and second fuse blocks 4 and 5 program data necessary for the redundancy operation according to the input of the address A. FIG. In the low pass operation, when the output signal of the low pass block 2 is in the first state (Normal mode), the normal low decoder 8 is operated. When the output signal of the low pass block 2 is in the second state (Redundant mode), the normal row decoder 8 is not operated, and the redundancy address detection circuit 7 is operated.

2 is a redundancy address detection circuit diagram 11 for outputting an output signal of a fuse block, which is a redundant device according to the present invention, to a normal data bus line 21 for transferring data of a memory element during normal operation. First and second redundancy data bus lines 22 and 23 for transferring data of a fuse block, which is a redundant address storage device, and a data output for externally outputting data of the memory device during a normal read operation. A first switching means 25 connected between the circuit 24, the normal data line 21 and the data output circuit 24 and turned on in the normal operation of the test mode detection circuit 28, A logic means 26 for inputting data of the first and second fuse blocks 4 and 5 and an output terminal of the logic means 26 and a data output circuit 24 and connected to the test mode detection circuit 28; According to the output of Consists of a second switching means 27 are the same.

As described above, the redundancy address detection circuit of the present invention outputs specific data through the output circuit 24 when a redundant address is input during a specific test mode operation, thereby identifying whether the input address signal is a redundant address signal. In other words, it can determine whether it is a normal address signal from outside.

As described above, according to the present invention, by configuring a redundancy address detecting circuit inside the device to confirm the repaired address of the semiconductor memory device, it is possible to shorten the time taken to confirm the repaired address, thereby reducing the cost loss. There is an excellent effect that can be done.

Claims (2)

A memory cell array driven according to an output of a column decoder supplied through a row decoder output and an input / output gate; A state machine for outputting a command signal by inputting an external signal for determining the operation of the DRAM; A low pass block providing a timing signal to said row decoder for selecting at least one word line in said memory cell array; A column pass block for providing a timing signal to the column decoder to select at least one column in the memory cell array; A first fuse block for determining a redundancy address in which a fuse can be prepared and selected so that a row address cell can be replaced with a redundancy cell in case of failure; A second fuse block for determining a redundancy address in which a fuse can be prepared and selected so as to replace a redundancy cell when a column address cell fails; A mode register for performing a test mode for specifying post-manufacture inspection to perform a purpose other than the normal operation of the DRAM, And a redundancy address detecting circuit for stopping an input / output operation and outputting a signal to a data input / output buffer when a repaired address is applied during a row or column active operation in the test mode. The method of claim 1, The redundancy address detection circuit includes a normal data bus line which transfers data of a memory device during normal operation; First and second redundancy data bus lines for transferring data of a fuse block which is a redundant address storage device; A data output circuit which outputs data of the memory device to an external device during a normal read operation; First switching means connected between said normal data line and a data output circuit and turned on during normal operation of a test mode detection circuit; Logic means operated during a specific operation and inputting data of the first and second fuse blocks; And a second switching means connected between an output terminal of the logic means and a data output circuit and driven according to the output of the test mode detection circuit.