KR100605496B1 - Apparatus and method for generating raw redundant enable signal in semiconductor memory apparatus - Google Patents

Abstract

The present invention relates to a low redundancy enable signal generation circuit and method of a semiconductor memory device, and more particularly, to an apparatus for generating a repair signal when a defective low cell array of a normal memory block is replaced with a low redundancy block. Signal generation means, a test enable signal generation means for outputting a test enable signal for a multi-row address disturb test operation in response to a plurality of mode register set addresses and a mode register set pulse signal, and externally applied in a normal operation mode When the decoded row address signal is an address signal of a low redundancy block, the decoded row address signal is activated in response to a repair signal and a low redundancy word line enable signal applied externally, and in a multi row address disturb test operation mode, a test enable signal is activated. In response to the call and low redundancy wordline enable signal, the low redundancy in is deactivated when the decoded row address signal is the address signal of the normal block and is activated when the decoded row address signal is the address signal of the low redundancy block. A low redundancy enable means for generating an enable signal is provided. Therefore, in the present invention, since the multi-row address disturb test can be performed regardless of the redundancy method and the repair, the test cost can be reduced.

Description

Low redundancy enable signal generation circuit and method of semiconductor memory device {APPARATUS AND METHOD FOR GENERATING RAW REDUNDANT ENABLE SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS}

1 is a diagram illustrating a low redundancy enable signal generation circuit of a conventional semiconductor memory device.

2 is a timing diagram for explaining a multi-row address disturb test operation of a conventional semiconductor memory device.

3 is a circuit diagram showing the configuration of a low redundancy enable signal generation circuit of a semiconductor memory device according to the present invention;

4 is a diagram showing a circuit configuration of a register of a test enable signal generating means according to the present invention;

5 is a diagram showing a circuit configuration of an output control means of the test enable signal generating means according to the present invention;

6 is a timing diagram for explaining a multi-row address disturb test operation of a semiconductor memory device according to the present invention;

<Description of the symbols for the main parts of the drawings>

10: repair signal generating means 12, 30: low redundancy enable stage

20: test enable signal generating means 22: register

22a: input latch 22b: output latch

24: output control means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low redundancy enable signal generation circuit and a method of a semiconductor memory device. In particular, a low redundancy that enables a multi row address disturb (MRAD) test operation regardless of a method or repair of low redundancy is possible. An enable signal generation circuit and method are disclosed.

Recently, the capacity of semiconductor memory devices has been rapidly increasing. As the storage capacity of the semiconductor memory device increases, it is inevitable to increase the test time required to test it. As a result, productivity problems are on the rise.

Therefore, with the high integration of semiconductor memory devices, all products currently in mass production are trying to reduce the test time by reducing test items or reducing refresh cycles. However, since such test items are directly related to the reliability of the product, there is a limit to elimination and reduction of test time.

Most of the DRAM test time takes most of the time to test the defects inside the cell in order to ensure the reliability of the product. In other words, the disturb test items and burn-in account for most of the DRAM test.

Multi row address disturb (MRAD) that can apply stress while simultaneously activating multiple word lines by using the function of SDRAM in order to shorten the disturb test item and burn-in time to improve the productivity of DRAM. Address Disturb) has been developed, and multi-row address disturbances are now being applied to increase productivity, including reducing test lead times.

However, most of the multi-row address disturbance tests are applied only to pre-laser tests, and the block redundancy structure used in most devices makes it impossible to test multi-row address disturbances in the package stage after laser repair, so the actual package test time at the back end is not possible. The effects on reduction and burn-in have not been substantially seen.

Therefore, to implement multi-row address disturbances at the package level, each block must have a separate redundancy cell. However, most products at present have a block redundancy structure to increase redundancy efficiency. In this case, when redundancy in another block is used to replace a defective cell, the block signal is changed so that a plurality of word lines previously activated by multi-row address disturb are disabled.

1 shows a conventional low redundancy enable signal generation circuit. The conventional circuit comprises a repair signal generating means 10 and a low redundancy enable means 12. The repair signal generating means 10 cuts the fuse F when the cell array of the normal memory block is replaced with the cell array of the low redundancy block. The repair signal generating means 10 generates a repair signal as a repair signal. . The low redundancy enable means 12 generates a low redundancy enable signal PRENi by combining the decoded row address signal DRA234, the low redundancy word line enable signal PRTR, and the repair signal.

Therefore, in the case of performing the multi-row address disturb test in the conventional semiconductor memory device generating the low redundancy enable signal as described above, as shown in FIG. 2, the moment when the sequentially activated word line is replaced with the repair cell word line The redundancy cell is accessed and the previously active word line is disabled. Therefore, multi-row address disturbances are not possible when all chips are repaired, such as packages.

An object of the present invention is to solve the problems of the prior art by deactivating the low redundancy enable signal during the multi-row address disturb test operation can be applied to the multi-row address disturb test regardless of redundancy or repair It is an object of the present invention to provide a low redundancy enable signal generation circuit and method for a semiconductor memory device that can reduce cost.

In order to achieve the above object of the present invention, the apparatus of the present invention includes a repair signal generating means for generating a repair signal when a defective low cell array of a normal memory block is replaced with a low redundancy block, and a plurality of mode register set addresses; A test enable signal generating means for outputting a test enable signal for a multi-row address disturb test operation in response to a mode register set pulse signal, and a decoded row address signal applied externally in a normal operation mode to an address of a low redundancy block; The signal is activated in response to the repair signal and the low redundancy word line enable signal applied from the outside, and in the multi-row address disturb test operation mode, the signal is activated in response to the test enable signal and the low redundancy word line enable signal. And a low redundancy enable means for generating a low redundancy enable signal that is deactivated when the loaded row address signal is an address signal of a normal block and is activated when the decoded row address signal is an address signal of a low redundancy block. It features.

The method of the present invention is a semiconductor memory device that performs a multi-row address disturb test operation, the method comprising: generating a repair signal when a defective low cell array of a normal memory block is replaced with a low redundancy block; Generating an activated low redundancy enable signal in response to an externally applied low redundancy word line enable signal and a repair signal when the applied decoded row address signal is an address signal of a low redundancy block, the plurality of mode registers Outputting a test enable signal for a multi-row address disturb test operation in response to a set address and a mode register set pulse signal, wherein the row address signal decoded in the multi-row address disturb test operation mode is an address of a normal block; Generating a deactivated low redundancy enable signal in response to a test enable signal and a low redundancy word line enable signal in the case of a signal; and in the multi-row address disturb test operation mode, the decoded low address signal is a low redundancy block. And generating an activated low redundancy enable signal in response to the test enable signal and the low redundancy word line enable signal in the case of an address signal.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

3 shows a configuration of a low redundancy enable signal generation circuit of a semiconductor memory device according to the present invention. In FIG. 3, the low redundancy enable signal generation circuit includes a repair signal generation means 10, a test enable signal generation means 20, and a low redundancy enable means 30.

The repair signal generating means 10 includes a plurality of fuses F, NAND gates NAND1 and NAND2, a NOR gate NOR1, and an inverter INV1. Therefore, when the defective cell of the normal memory block and the normal cell of the redundancy block are replaced, the fuse F is blown, and a high signal is input to the inputs of the NAND gates NAND1 and NAND2. Therefore, when all the fuses F are blown, the repair signal is output in the low state, and in all other cases, the repair signal is output in the high state.

The test enable signal generating means 20 includes a mode register set address (MRA2B, MRA7B, MRA8B) and a row address strobe (RAS: ROW ADDRESS STROBE) signal to set the mode register in response to WCBR (WE, CAS Before RAS). The test enable signal PMRAD is generated in response to the mode register set pulse signal PMRSP generated when the signal is enabled. Therefore, when the WCBR is set, which is the mode register setting timing, the signal of the mode register set address MRA2B for enabling the test enable signal PMRAD is latched. Therefore, the test enable signal PMRAD is generated by the given specific mode register set addresses MRA2B, MRA7B, and MRA8B. In the present invention, it is assumed that the mode register set address MRA7B is in a low state, the mode register set address MRA8B is in a high state, and the mode register set address MRA2B is in a low state in a multi-row address disturb test mode.

The low redundancy enable means 30 includes a NOR gate NOR2, NAND gates NAND3 and NAND4, and an inverter INV2. Accordingly, the low redundancy enable means 30 inputs a repair signal, a test enable signal PMRAD, a decoded row address signal DRA234, and a low redundancy word line enable signal PRTR to provide a low redundancy enable signal ( PRENi).

Fig. 4 shows a circuit configuration of a register of the test enable signal generating means according to the present invention. The register 22 includes an input latch 22a and an output latch 22b.

The input latch 22a includes a transfer gate TG1, inverters INV3 to INV6, and a PMOS transistor M1. The transfer gate TG1 is switched in response to the mode register set pulse signal PMRSP to provide the mode register set address MRA2B to a latch circuit composed of inverters INV4 and INV5. The PMOS transistor M1 initially resets the latch circuit to the power supply voltage VCC in response to the power supply voltage high state VCCH.

The output latch 22b includes a transfer gate TG2, inverters INV7 to INV9, and a PMOS transistor M2. The transfer gate TG2 is switched in response to the first test mode signal MRSTEST to provide a signal latched to the input latch 22a to a latch circuit composed of inverters INV8 and INV9. The PMOS transistor M2 activates the latch circuit reset to the power supply voltage VCC in response to the second test mode signal MRSET.

5 shows a circuit configuration of the output control means of the test enable signal generating means according to the present invention. The output control means 24 includes NAND gates NAND5 and NAND6, NOR gate NOR3, and inverters INV10 to INV12.

The output control means 24 inputs the mode register set addresses MRA7B and MRA8B to generate first and second test mode signals MRSTEST and MRSET according to the test mode, respectively. Therefore, in the multi-row address disturb test mode, the mode register set address MRA7B is input in the low state and the mode register set address MRA8B is in the high state, so both the first and second test mode signals MRSTEST and MRSET are high. Is output.

Therefore, in the multi-row address disturb test mode, the mode register set address MRA2B latched in the input latch 22a is inverted and latched in the high state, and the first test mode signal MRSTEST and the second test mode signal MRSET are inverted. ) Are all output in a high state, so the low state signal provided from the input latch 22a is latched as a high state signal in the output latch 22b. Therefore, the test enable signal PMRAD is provided to the low redundancy enable means 30 in the high state.

A multi-row address disturb test operation of the semiconductor memory device according to the present invention will be described with reference to FIG. 6.

The mode register set pulse signal PMRSP is activated in a high state in synchronization with the active tip of the row address strobe signal RAS. The signal of the mode register set address MRA2B is latched in the input latch 22a of the register 22 in response to the mode register set pulse signal PMRSP signal.

Therefore, the internal multi-word line activation control signal, that is, the test enable signal PMRAD is generated by the given specific mode register set address MRS2B.

The first test mode signal MRSTEST, which is a control signal of the transfer gate TG2 in the output latch 22b of the register 22, and the second test mode signal MRSET, which is a signal for activating the latch circuit, are multi-row address disturbed. This signal is for controlling the mode register set address only in the test mode. The test mode is determined by the combination of the mode register set address (MRA7B, MRA8B) states which are the test mode addresses and the mode register set address (MRA2B).

Therefore, in the present invention, when the test enable signal PMRAD is set in the mode register, the corresponding mode register set address MRA2B is latched, and the output latch 22b is generated to be generated only when the corresponding mode register set addresses MRA7B and MRA8B are input. To control.

When the test enable signal PMRAD is enabled in a high state, the low redundancy enable signal PRENi is always set low regardless of whether the fuse is cut and repaired for the low address of the bad word line. Throw it away. That is, the low redundancy word line is blocked from being activated during the multi-row address disturb test operation so that only the word line of the normal memory block is activated.

Therefore, even when redundancy is used, such as a package, only the word line of the normal block is always enabled without enabling the word line of the redundancy block.

When the multi-row address disturb test operation on the normal block is completed as described above, in order to perform the multi-row address disturb test on the redundancy block, the low redundancy word line enable signal (PRTR) is enabled through the mode register set operation. The input of (NAND3) becomes high, which causes the output of NAND gate (NAND3) to low, resulting in a low redundancy enable signal PREN. That is, multi-row address disturb is possible for the low redundancy word line.

When the multi-row address disturbance is not used, when the fuse is blown for the bad addresses, the NAND gates NAND1 and NAND2 inputs are both high, and the output of the NOR gate NOR1 becomes high. Therefore, since both inputs of the NOR gate NOR2 are in the low state, the input of the NAND gate NAND4 is in the low state, and the low redundancy enable signal PREN is in the high state. Therefore, in normal operation, the word line of the low redundancy cell replaced with the defective cell can be driven.

As described above, in the present invention, in the case of the product using block redundancy during the multi-row address disturb test operation, after the bad word line repair, since the block information is changed and all the word lines that are being disturbed are disabled, the disassembly is impossible after the repair. By interlocking the row redundancy word line in conjunction with the row address disturb test operation, multi-word line disturb can be performed without limitation of redundancy or repair. Therefore, even in the case of repaired and packaged products, multi-row address disturbance test can be used regardless of repairing when multi-row address disturb is applied, so that it can be replaced by shorter test time and burn-in test. Therefore, the test cost can be reduced, and the productivity can be improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (3)

Repair signal generating means for generating a repair signal when the defective low cell array of the normal memory block is replaced with a low redundancy block; Test enable signal generating means for outputting a test enable signal for a multi-row address disturb test operation in response to a plurality of mode register set addresses and a mode register set pulse signal; And In the normal operation mode, when the externally applied decoded row address signal is an address signal of a low redundancy block, it is activated in response to the repair signal and the low redundancy word line enable signal applied externally. In the mode, in response to the test enable signal and the low redundancy word line enable signal, the decoded row address signal is deactivated when the normal block is an address signal, and the decoded row address signal is the address signal of the low redundancy block. And a low redundancy enable means for generating a low redundancy enable signal that is activated when the low redundancy enable signal is generated. The method of claim 1, wherein the test enable signal generating means Output control means for generating an output enable signal in response to a predetermined mode register address specifying a multi-row address disturb test mode among the plurality of mode register addresses; And When a mode register is set, a register for latching a specific mode register set address among the plurality of mode register set addresses, and outputting the latched signal as a test enable signal for a multi-row address disturb test operation in response to the output enable signal. And a low redundancy enable signal generation circuit of the semiconductor memory device. A semiconductor memory device that performs a multi-row address disturb test operation, Generating a repair signal when the defective low cell array of the normal memory block is replaced with a low redundancy block; When the decoded row address signal applied externally in the normal operation is the address signal of the low redundancy block, an externally applied low redundancy word line enable signal and an activated low redundancy enable signal are generated in response to the repair signal. Doing; Outputting a test enable signal for a multi-row address disturb test operation in response to the plurality of mode register set addresses and the mode register set pulse signal; In the multi-row address disturb test operation mode, when the decoded row address signal is an address signal of a normal block, an inactive low redundancy enable signal is generated in response to the test enable signal and the low redundancy word line enable signal. step; And In the multi-row address disturb test operation mode, when the decoded row address signal is an address signal of a low redundancy block, an activated low redundancy enable signal is generated in response to the test enable signal and the low redundancy word line enable signal. And a low redundancy enable signal generation method of a semiconductor memory device.

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