KR100833592B1 - Semiconductor memory device and the method of refresh for semiconductor memory - Google Patents

Abstract

A semiconductor memory device and a refresh method of a semiconductor memory are provided to reduce test time by testing failures of a normal cell and a redundant cell at the same time, by refreshing a normal word line and a redundancy word line sequentially. A refresh counter outputs a refresh address and a first control signal by a refresh signal. A first selection signal generation part(120) outputs a first selection signal controlling to select a refresh word line in correspondence to the enable of the refresh signal. A second selection signal generation part(140) outputs a second selection signal controlling to select an active word line in correspondence to the disable of the refresh signal. An output part(160) outputs a third selection signal enabling one of a normal word line and a redundancy word line by the first and the second selection signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device and a method of refreshing a semiconductor memory,

1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention;

2 is a circuit diagram showing a refresh counter that outputs a redundancy word line refresh input signal FLAG;

3 is a circuit diagram showing a reset signal (RESET) generator of FIG. 2;

4A is a redundancy word line active operation waveform diagram of a semiconductor memory device according to the present invention;

FIG. 4B is a waveform diagram of a redundancy word line refresh operation of the semiconductor memory device according to the present invention; FIG.

4C is a waveform diagram of a normal word line active operation of a semiconductor memory device according to the present invention;

4D is a waveform diagram of a normal word line refresh operation of the semiconductor memory device according to the present invention;

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a method of refreshing a semiconductor memory.

Generally, a semiconductor memory device uses a repair method in which a normal cell and a redundant cell are provided in a semiconductor memory device in order to improve the yield, and a normal cell in which a failure occurs is found through a test to replace the redundant cell with a redundant cell.

In a conventional semiconductor memory device, when a defective normal cell is found by performing a read or write operation by enabling a normal word line, a normal word line in which a corresponding normal cell exists is replaced with a redundancy word line, And performs a read or write operation to test whether there is a defect. This test is repeated until all cells are confirmed to be operating normally.

However, in the conventional semiconductor memory device, it is difficult to confirm whether the redundancy word line is defective before the repair operation. Therefore, there is a problem that the repair efficiency is lowered when there is a defect in the replaced redundancy word line.

In order to improve this, there is a problem in that when the redundancy word line is independently tested by combining the test mode after the normal cell test, the test time is increased due to the time for reading or writing the redundant cell.

In addition, since the conventional semiconductor memory device performs the test through the active operation, there is a problem that it is difficult to perform an appropriate test for randomly performing the active operation and the refresh operation.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device and a semiconductor memory refreshing method for sequentially refreshing a normal word line and a redundancy word line, thereby simultaneously testing the defects of the normal cell and the redundant cell, thereby reducing the test time.

It is another object of the present invention to provide a semiconductor memory device that provides an optimal test environment for testing active operation and refresh operation arbitrarily performed on a normal word line and a redundancy word line.

It is still another object of the present invention to improve the repair efficiency by replacing a normal cell in which a failure has occurred through a normal redundancy cell.

According to an aspect of the present invention, there is provided a semiconductor memory device including: a refresh counter that outputs a refresh address and a first control signal in response to a refresh signal; A first selection signal generator for outputting a first selection signal for controlling the selection of the refresh word line in response to the activation of the refresh signal; A second selection signal generator for outputting a second selection signal for controlling selection of an active word line in response to deactivation of the refresh signal; And an output unit for outputting a third selection signal for activating either the normal word line or the redundancy word line by the first and second selection signals.

Wherein the refresh counter includes a plurality of address counters for outputting the refresh address and control signal corresponding to each bit of the sub-word line and block selection and main word line address when the refresh signal is activated; A flag counter for outputting the first control signal in synchronization with a control signal output from an address counter corresponding to the most significant bit of the main word line; And a reset signal generator for outputting a reset signal for resetting the plurality of address counters and the flag counter.

And the flag counter outputs the first control signal activated in synchronization with the polling edge of the control signal.

Wherein the reset signal generation unit generates a reset signal when the first control signal and the test mode signal are activated, the rising of the control signal output from the address counter corresponding to the least significant bit of the main word line, And outputs the reset signal in synchronization with the polling of the control signals output from the address counter.

Wherein the reset signal generator comprises: a first NAND gate receiving the first control signal and a control signal output from an address counter corresponding to the least significant bit of the main word line; A second NAND gate for inverting control signals provided from address counters corresponding to the sub-word line address and receiving the inverted control signals; A third NAND gate receiving the inverted control signals from the address counters corresponding to the block selection address; A first No Gate for receiving the outputs of the first through third NAND gates; A second No Gate for receiving a signal obtained by inverting a test mode signal and a signal obtained by inverting an output of the first NOR gate; And an inverter for inverting an output of the second Noah gate and outputting the inverted output as the reset signal.

Wherein the first selection signal generator is connected between a power supply voltage and an output node and initializes the output node when the test mode signal is inactivated; A pull-up unit connected between the power supply voltage and the output node to supply a power supply voltage to the output node when the precharge signal is activated; A pull down unit coupled between the output node and a ground voltage to supply a ground voltage to the output node when the test mode signal, the refresh signal, and the first control signal are activated; And a latch unit latching and inverting the signal of the output node and outputting the inverted signal as the first selection signal.

Preferably, the precharge signal is a signal that is automatically activated after a predetermined time after completion of refreshing.

The pull-up unit includes a PMOS transistor connected between the power supply voltage and the output node and responsive to the precharge signal applied to the gate.

The pull-down section includes NMOS transistors connected in series between the output node and the ground voltage, and responsive to the test mode signal, the refresh signal, and the first control signal applied to the respective gates.

The initialization unit includes a PMOS transistor connected between the power supply voltage and the output node and responsive to the test mode signal applied to the gate.

Wherein the second selection signal generator comprises: a NAND gate that combines the inverted refresh signal with an active word line selection signal; And an inverter for inverting an output of the NAND gate and outputting the inverted signal as the second selection signal.

The active word line select signal is preferably a signal for selecting a word line to be activated in synchronization with an active signal when a test mode signal is activated.

Wherein the output unit comprises: a No gate receiving the first and second selection signals; And an inverter for inverting the output of the Noah gate and outputting the inverted output as the third selection signal.

Another semiconductor memory device for achieving the object of the present invention includes: a refresh counter for outputting a refresh address and a first control signal in response to a refresh signal; And a refresh selection signal generator for outputting a refresh selection signal for activating a normal word line and a redundancy word line in response to the first control signal, wherein the refresh counter includes a subword line address, a block selection address, A plurality of address counters for outputting a refresh address and a control signal respectively corresponding to addresses; A flag counter for outputting the first control signal in synchronization with polling of a control signal output from an address counter corresponding to the most significant bit of the main word line address; And a reset signal regenerator for outputting a reset signal for resetting the address counters and the flag counter.

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The first control signal is preferably a signal that is activated while the refresh counter counts the redundancy word line address.

Wherein the reset signal generation unit generates a reset signal when the first control signal and the test mode signal are activated, the rising of the control signal output from the address counter corresponding to the least significant bit of the main word line, And outputs the reset signal in synchronization with the polling of the control signals output from the address counter.

Wherein the refresh selection signal generator comprises: an initialization unit connected between a power supply voltage and an output node to initialize the output node when the test mode signal is inactivated; A pull-up unit connected between the power supply voltage and the output node to supply a power supply voltage to the output node when the precharge signal is activated; A pull down unit coupled between the output node and a ground voltage to supply a ground voltage to the output node when the test mode signal, the refresh signal, and the first control signal are activated; And a latch unit latching and inverting a signal of the output node and outputting the inverted signal as the refresh selection signal.

Preferably, the precharge signal is a signal that is automatically activated after a predetermined time after completion of refreshing.

And the pull-down section includes NMOS transistors controlled by the test mode signal, the refresh signal, and the first control signal applied to each gate in series between the output node and the ground voltage.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a first selection signal generator for outputting a first selection signal for selecting a refresh word line to be activated by a refresh signal; A second selection signal generator for outputting a second selection signal for selecting an active word line to be activated by an active signal; And an output unit for outputting an output signal for activating either the normal word line or the redundancy word line by the first and second selection signals, wherein the first selection signal generation unit generates the normal word Line and the redundancy word line are sequentially activated.

Preferably, the counter flag signal is a signal activated during the counting of the redundancy word line address in the refresh counter.

Wherein the first selection signal generator is connected between a power supply voltage and an output node and initializes the output node when the test mode signal is inactivated; A pull-up unit connected between the power supply voltage and the output node to supply a power supply voltage to the output node when the precharge signal is activated; A pull down unit coupled between the output node and a ground voltage to supply a ground voltage to the output node when the test mode signal, the refresh signal, and the counter flag signal are activated; And a latch unit latching and inverting the signal of the output node and outputting the inverted signal as the first selection signal.

And the first selection signal generator outputs a first selection signal for activating the redundancy word line while the refresh signal and the flag signal are activated in a test mode.

The second selection signal generation unit may include an active word line selection signal that is synchronized with the active signal and has active word line information, and a control signal that is activated while the refresh signal is activated and controls the output of the active word line selection signal NAND gate; And an inverter for inverting an output of the NAND gate and outputting the inverted signal as the second selection signal.

And the output unit outputs the output signal for activating the redundancy word line when at least one of the first and second selection signals is activated.

According to another aspect of the present invention, there is provided a method of refreshing a semiconductor memory, the method comprising: a first step of outputting a first selection signal for selectively controlling a refresh operation for a normal word line or a redundancy word line in response to activation of a refresh signal; ; A second step of outputting a second selection signal for selectively performing an active control on a normal word line or a redundancy word line in response to deactivation of a refresh signal; And a third step of outputting a third selection signal reflecting a state in which at least one of the first selection signal and the second selection signal is enabled.

Outputting the first selection signal in response to a selection signal for a normal word line or a redundancy word line; And latching the first selection signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides a semiconductor memory device and a semiconductor memory refresh method for sequentially refreshing a normal word line and a redundancy word line in response to a redundancy word line refresh entry signal provided in a refresh counter to simultaneously test a normal word line and a redundancy word line Thereby reducing the test time and improving the repair efficiency. A preferred embodiment thereof is shown in Fig.

1, the semiconductor memory device according to the present invention includes a refresh selection signal generator 120 for outputting a refresh selection signal XRED_REF, an active selection signal generator 140 for outputting an active selection signal XRED_NOR, and a redundancy selection signal XRED_ON And an output unit 160 for outputting the output signal.

Here, the refresh selection signal XRED_REF is a signal activated to a high level when refreshing the redundancy word line, the active selection signal XRED_NOR is a signal activated to a high level when the redundancy word line is active, and the redundancy selection signal XRED_ON is a refresh selection signal XRED_REF or the active selection signal XRED_NOR to a high level when it is outputted as a high level to activate the redundancy word line. That is, when the redundancy selection signal XRED_ON is output as a high level, the redundancy word line is activated, and when the redundancy selection signal XRED_ON is outputted as a low level, the normal word line is activated.

The refresh selection signal generation section 120 includes a pull-up section 122, a pull-down section 124, an initialization section 126 and a latch section 128. The refresh selection signal generation section 120 includes a precharge signal SENSEDLY, a refresh signal REF, a redundancy word line refresh entry The output of the refresh selection signal XRED_REF is determined by the signal FLAG and the test mode signal TM.

Here, the precharge signal SENSEDLY is a signal that is written to the cell or is automatically activated to a low level after completion of the refresh, and the refresh signal REF is activated to a high level by the refresh command and is inactivated when the precharge signal SENSEDLY is activated Signal, and the test mode signal TM is a signal that is activated to a high level in the test mode.

The redundancy word line refresh input signal FLAG is a signal which counts the last normal word line address by the refresh counter, is activated at a high level, counts the last redundancy word line address, and is deactivated at a low level.

The pull-up unit 122 may include a PMOS transistor P1 connected between the power supply voltage VDD and the node ND and supplying the power supply voltage VDD to the node ND in response to a pre-charge signal SENSEDLY applied to the gate.

The pull-down unit 124 is connected in series between the node ND and the ground voltage VSS and outputs a ground voltage VSS to the node ND in response to the refresh signal REF applied to each gate, the redundancy word line refresh input signal FLAG, and the test mode signal TM And NMOS transistors N1, N2, and N3 for supplying the NMOS transistors N1, N2, and N3.

The initialization unit 126 may be composed of a PMOS transistor P2 which is connected between the power supply voltage VDD and the node ND and which initializes the node ND to the power supply voltage VDD level in response to the test mode signal TM applied to the gate.

The latch unit 128 may be composed of inverters INV1 and INV2 that latch the output of the node ND and output the refresh selection signal XRED_REF.

The active selection signal generating unit 140 includes an inverter (not shown) for inverting the output of the inverted refresh signal REFB and the NAND gate NAND receiving the bank address signal BA <0> and the NAND gate NAND to output the active selection signal XRED_NOR INV3).

Here, the inverted refresh signal REFB is a signal activated to a low level during the activation of the refresh signal REF, and the bank address signal BA < 0 > distinguishes the normal word line active from the redundancy word line active by the active signal in the test mode Signal. That is, the bank address signal BA < 0 > is activated to the high level in the redundancy word line active state and deactivated to the low level in the normal word line active state.

The output unit 160 includes an inverter INV4 for outputting the redundancy selection signal XRED_ON by inverting the outputs of the NOR gate NOR and the NOR gate NOR receiving the refresh selection signal XRED_REF and the active selection signal XRED_NOR .

As described above, the semiconductor memory device performs the refresh operation by selectively activating the normal word line and the redundancy word line in response to the redundancy word line refresh input signal FLAG provided in the refresh counter.

FIG. 2 illustrates a refresh counter for generating refresh addresses RA0 to RA11 for one bank of 4M. The refresh counter includes twelve address counters 22 connected in series, a flag counter 24, and a reset signal generator 26 .

Here, RA2, RA1 and RA0 are sub word line addresses, RA9, RA10 and RA11 are block selection addresses, and RA3 to RA8 are main word line addresses.

Each address counter 22 may be constituted by a flip-flop and receives the reset signal RESET and the control signals R0 to R11 output from the previous address counter to output the refresh addresses RA0 to RA11.

The flag counter 24 may be constituted by a flip-flop and receives the reset signal RESET and the control signal R8 and outputs the redundancy word line refresh input signal FLAG at a high level in synchronization with the polling edge of the control signal R8.

The reset signal generator 26 receives the test mode signal TM, the redundancy word line refresh input signal FLAG, and the control signals R2, R1, R0, R9, R10, R11, and R3 and outputs a reset signal RESET.

3, the reset signal generator 26 includes a NAND gate NOR2, NOR3, and inverters INV5 to INV13. The control signal generator 32 includes NAND gates NAND2 to NAND4, NOR2 and NOR3, and inverters INV5 to INV13.

The NAND gate NAND2 NANDs the redundancy word line refresh input signal FLAG and the control signal R3 and the NAND gate NAND3 outputs the control signals R11, R10, and R9 inverted by the inverters INV5, INV6, And the NAND gate NAND4 NANDs the inverted control signals R0, R1, and R2 by the inverters INV8, INV9, and INV10.

The NOR gate NOR2 combines the output of the NOR gate NOR2 inverted by the inverter INV11 with the output of the inverter INV12 And the test mode signal TM inverted by the test mode signal TM is coupled to the NOR circuit.

The inverter INV13 inverts the output of the NOR gate NOR3 and outputs a reset signal RESET.

2, the address counter 22 sequentially counts the sub-word line addresses RA2, RA1, and RA0, and then sequentially counts the block selection addresses RA9, RA10, and RA11 And counts the next main word line addresses RA3 to RA8. This corresponds to the normal word line refresh address.

The flag counter 24 counts the main word line address RA8 and outputs the redundancy word line refresh input signal FLAG at a high level in synchronization with the polling edge of the control signal R8.

Next, the address counter 22 sequentially counts the sub word line addresses RA2, RA1, and RA0, and then sequentially counts the block selection addresses RA9, RA10, and RA11. Normally, since the redundancy word lines are arranged one for each block unit, they do not need the main word line addresses RA3 to RA8, which corresponds to the redundancy refresh addresses.

When the test mode signal TM and the redundancy word line refresh input signal FLAG are at the high level and the control signals R2, R1, R0, R9, R10, and R11 are polled and the control signal R3 is synchronized with the rising, Activate RESET low.

The address counter 22 and the flag counter 24 are reset by the reset signal RESET. That is, the redundancy word line refresh input signal FLAG is activated after the last normal word line refresh address is counted and remains active while the redundancy word line refresh address is counted.

The semiconductor memory device of the present invention performs an active operation and a refresh operation randomly for the normal word line and the redundancy word line to check for defects. In other words, non-word line refresh, redundancy word line refresh, normal word line active, and redundancy word line active are performed randomly to check for defects.

Referring to FIG. 4A, in the redundancy word line active operation, the refresh selection signal XRED_REF is outputted as a low level because the refresh signal REF is at the low level, and the inverted refresh signal REFB and the bank address signal BA & The signal XRED_NOR is output at a high level. Therefore, the redundancy selection signal XRED_ON is output as a high level to activate the redundancy word line.

Referring to FIG. 4B, in the redundancy word line refresh operation, since the refresh signal REF and the redundancy word line refresh input signal FLAG are at a high level, the refresh selection signal XRED_REF is outputted at a high level. Therefore, the redundancy selection signal XRED_ON is output as a high level to activate the redundancy word line.

At this time, the inverted refresh signal REFB is activated to the low level during the period in which the refresh signal REF is activated and the precharge signal SENSEDLY is activated, thereby preventing the active operation of the bank active signal BA < 0 > .

Referring to FIG. 4C, in the normal word line active operation, the refresh selection signal XRED_REF is output as a low level because the refresh signal REF is at a low level, and the active selection signal XRED_NOR is at a low level . Therefore, the redundancy selection signal XRED_ON is output as a low level to activate the normal word line.

4D, in the normal refresh operation, the refresh signal REF is output as a high level, but since the redundancy word line refresh input signal FLAG is at a low level, the refresh selection signal XRED_REF is outputted as a low level, and the bank address signal BA & The active selection signal XRED_NOR is output at a low level. Therefore, the redundancy selection signal XRED_ON is output as a low level to activate the normal word line.

At this time, while the refresh signal REF is activated, the inverted refresh signal REFB is activated to the low level to block the output of the bank active signal BA < 0 >, thereby preventing the active operation and performing the refresh operation.

As described above, the semiconductor memory device of the present invention sequentially refreshes the normal word line and the redundancy word line, and conducts the active operation at random, thereby simultaneously testing the defects of the normal cell and the redundant cell. As a result, the test time is reduced and the repair efficiency is improved by replacing the bad normal word line with the normal redundancy word line.

Therefore, according to the present invention, there is an effect of reducing the test time by providing the semiconductor memory device that sequentially refreshes the normal word line and the redundancy word line.

In addition, according to the present invention, it is possible to provide an optimum test environment by providing a semiconductor memory device capable of performing an arbitrary test of refresh and active for a normal word line and a redundancy word line.

In addition, according to the present invention, repairing efficiency is improved by replacing a normal cell in which a failure occurs through the above test with a normal redundancy cell.

Claims (28)

A refresh counter for outputting a refresh address and a first control signal in response to a refresh signal; A first selection signal generator for outputting a first selection signal for controlling the selection of the refresh word line in response to the activation of the refresh signal; A second selection signal generator for outputting a second selection signal for controlling selection of an active word line in response to deactivation of the refresh signal; And An output unit for outputting a third selection signal for activating either the normal word line or the redundancy word line by the first and second selection signals; And a semiconductor memory device. The method according to claim 1, The refresh counter A plurality of address counters for outputting the refresh address and control signal corresponding to each bit of the sub-word line, block selection and main word line address when the refresh signal is activated; A flag counter for outputting the first control signal in synchronization with a control signal output from an address counter corresponding to the most significant bit of the main word line; And A reset signal generator for outputting a reset signal for resetting the plurality of address counters and the flag counter; And a semiconductor memory device. 3. The method of claim 2, Wherein the flag counter outputs the first control signal activated in synchronization with the polling edge of the control signal. 3. The method of claim 2, The reset signal generator The control signal output from the address counter corresponding to the least significant bit of the main word line and the rising edge of the control signal output from the address counter corresponding to the sub word line and the block selecting address when the first control signal and the test mode signal are activated And outputs the reset signal in synchronization with the polling of the control signals. 3. The method of claim 2, The reset signal generator A first NAND gate receiving the first control signal and a control signal output from an address counter corresponding to the least significant bit of the main word line; A second NAND gate for inverting control signals provided from address counters corresponding to the sub-word line address and receiving the inverted control signals; A third NAND gate receiving the inverted control signals from the address counters corresponding to the block selection address; A first No Gate for receiving the outputs of the first through third NAND gates; A second No Gate for receiving a signal obtained by inverting a test mode signal and a signal obtained by inverting an output of the first NOR gate; And And an inverter for inverting the output of the second Noah gate and outputting the inverted output as the reset signal. The method according to claim 1, The first selection signal generator An initialization unit coupled between the power supply voltage and the output node to initialize the output node when the test mode signal is inactive; A pull-up unit connected between the power supply voltage and the output node to supply a power supply voltage to the output node when the precharge signal is activated; A pull down unit coupled between the output node and a ground voltage to supply a ground voltage to the output node when the test mode signal, the refresh signal, and the first control signal are activated; And A latch for latching and inverting a signal of the output node and outputting the inverted signal as the first selection signal; And a semiconductor memory device. The method according to claim 6, Wherein the precharge signal is a signal that is automatically activated after a predetermined time after the refresh is completed. The method according to claim 6, Wherein the pull-up section comprises a PMOS transistor connected between the power supply voltage and the output node and responsive to the precharge signal applied to the gate. The method according to claim 6, Wherein the pull-down section includes NMOS transistors serially connected between the output node and the ground voltage, and responsive to the test mode signal, the refresh signal, and the first control signal applied to the gate, Device. The method according to claim 6, Wherein the initialization unit comprises a PMOS transistor connected between the power supply voltage and the output node and responsive to the test mode signal applied to the gate. The method according to claim 1, The second selection signal generator A NAND gate that combines the inverted refresh signal with an active word line select signal; And An inverter for inverting an output of the NAND gate and outputting the second selection signal; And a semiconductor memory device. 12. The method of claim 11, Wherein the active word line select signal is a signal for selecting a word line to be activated in synchronization with an active signal when the test mode signal is activated. The method according to claim 1, The output A No Gate receiving the first and second selection signals; And An inverter for inverting the output of the Noah gate to output the third selection signal; And a semiconductor memory device. delete A refresh counter for outputting a refresh address and a first control signal in response to a refresh signal; And And a refresh selection signal generator for outputting a refresh selection signal for activating a normal word line and a redundancy word line in response to the first control signal, Wherein the refresh counter comprises: a plurality of address counters for outputting control signals and refresh addresses respectively corresponding to a sub-word line address, a block select address and a main word line address; A flag counter for outputting the first control signal in synchronization with polling of a control signal output from an address counter corresponding to the most significant bit of the main word line address; And A reset signal generator for outputting a reset signal for resetting the address counters and the flag counter; And a semiconductor memory device. 16. The method of claim 15, Wherein the first control signal is a signal that is activated while the refresh counter counts the redundancy word line address. 16. The method of claim 15, Wherein the reset signal generation unit generates a reset signal when the first control signal and the test mode signal are activated, the rising of the control signal output from the address counter corresponding to the least significant bit of the main word line, And outputs the reset signal in synchronization with the polling of the control signals output from the address counter. 16. The method of claim 15, The refresh selection signal generation unit An initialization unit coupled between the power supply voltage and the output node to initialize the output node when the test mode signal is inactive; A pull-up unit connected between the power supply voltage and the output node to supply a power supply voltage to the output node when the precharge signal is activated; A pull down unit coupled between the output node and a ground voltage to supply a ground voltage to the output node when the test mode signal, the refresh signal, and the first control signal are activated; And A latch for latching and inverting a signal of the output node and outputting the signal as the refresh selection signal; And a semiconductor memory device. 19. The method of claim 18, Wherein the precharge signal is a signal that is automatically activated after a predetermined time after the refresh is completed. 19. The method of claim 18, Wherein the pull-down section includes NMOS transistors controlled by the test mode signal, the refresh signal, and the first control signal applied to each gate in series between the output node and the ground voltage. . A first selection signal generator for outputting a first selection signal for selecting a refresh word line to be activated by a refresh signal; A second selection signal generator for outputting a second selection signal for selecting an active word line to be activated by an active signal; And An output unit for outputting an output signal for activating either the normal word line or the redundancy word line by the first and second selection signals; Wherein the first selection signal generator sequentially activates the normal word line and the redundancy word line in accordance with the counter flag signal. 22. The method of claim 21, Wherein the counter flag signal is a signal that is activated while the redundancy word line address is counted in the refresh counter. 22. The method of claim 21, The first selection signal generator An initialization unit coupled between the power supply voltage and the output node to initialize the output node when the test mode signal is inactive; A pull-up unit connected between the power supply voltage and the output node to supply a power supply voltage to the output node when the precharge signal is activated; A pull down unit coupled between the output node and a ground voltage to supply a ground voltage to the output node when the test mode signal, the refresh signal, and the counter flag signal are activated; And A latch for latching and inverting a signal of the output node and outputting the inverted signal as the first selection signal; And a semiconductor memory device. 22. The method of claim 21, The first selection signal generator And outputs a first selection signal for activating the redundancy word line while the refresh signal and the counter flag signal are activated in a test mode. 22. The method of claim 21, The second selection signal generator An active word line select signal synchronized with the active signal and having active word line information, a NAND gate activated while the refresh signal is activated, and receiving a control signal for controlling the output of the active word line select signal; And An inverter for inverting an output of the NAND gate and outputting the second selection signal; And a semiconductor memory device. 22. The method of claim 21, And the output section outputs the output signal for activating the redundancy word line when at least one of the first and second selection signals is activated. A first step of outputting a first selection signal for selectively performing control of refresh for a normal word line or a redundancy word line in response to activation of a refresh signal; A second step of outputting a second selection signal for selectively performing an active control on a normal word line or a redundancy word line in response to deactivation of a refresh signal; And A third step of outputting a third selection signal reflecting a state in which at least one of the first selection signal and the second selection signal is enabled; And refreshing the semiconductor memory. 28. The method of claim 27, The first step Outputting the precharged output node in response to a selection signal for a normal word line or a redundancy word line; And Latching the first selection signal; And refreshing the semiconductor memory.

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