KR100652796B1 - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to increase amplification efficiency of a bit line sense amplifier, by preventing overlapping between a discharge operation period and an over-driving operation period. In a semiconductor memory device comprising a plurality of banks, a normal-driving driving part drives a pull-up voltage line of a bit line sense amplifier with a normal driving voltage. An over-driving driving part drives the pull-up voltage line of the bit line sense amplifier with an over-driving voltage. A discharge driving part drops the normal-driving voltage level increased by the over-driving driving down to a reference normal driving voltage level through discharge. A level detection part drives the discharge driving part by comparing the normal driving voltage with a reference voltage. A level detection part enable signal generation part outputs an enable signal of the level detection part to prevent the overlap between the over-driving period and the discharge period in response to an assembly signal of the bank over-driving signals.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

1 is a circuit diagram showing a drive driver of a pull-up and pull-down power line for driving a general bit line sense amplifier.

Fig. 2 is a graph showing the potential difference between bit line pairs (bit lines and bit line bars) when the bit line sense amplifiers are driven.

FIG. 3 is a circuit diagram illustrating a circuit including a level detector for discharging a core voltage whose voltage level rises due to an overdriving operation of a bit line sense amplifier.

4 is a circuit diagram illustrating the level detector 301 of FIG. 3.

5 is a circuit diagram illustrating a level detector enable signal generator that generates the level detector enable signal of FIG.

6A and 6B are timing diagrams of the level detector enable signal generator of FIG. 3.

7 is a circuit diagram illustrating a level detector enable signal generator according to an exemplary embodiment of the present invention.

8 is a timing diagram of a level detector enable signal generator of FIG. 7; FIG.

Explanation of symbols on the main parts of the drawings

701: overdriving signal combination circuit

703: delay circuit

705: output circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a level detector enable signal generation circuit of a semiconductor memory device.

The bit line detection amplifier of a semiconductor memory device is a circuit provided to amplify data input from a memory cell or a segment input / output line to a bit line. The bit line detection amplifier is grounded to a pair of bit lines to detect a potential difference between the pair of bit lines, and the core Pull-up and pull-down power lines are used to amplify to voltage and ground voltages.

However, the core voltage applied to the pull-up power line has a limitation in sensing efficiency and capability. Currently, an external power supply voltage is applied to the pull-up power line for a predetermined time.

As described above, performing the amplification operation by applying an external power supply voltage to the pull-up power supply line is referred to as an overdriving operation of the sense amplifier.

When the overdriving operation is completed, the core voltage is applied to the pull-up power line.

At this time, current flows in the core voltage due to the external power supply voltage applied to the pull-up power supply line, thereby increasing the voltage level of the core voltage.

1 is a circuit diagram illustrating a driving driver of pull-up and pull-down power lines for driving a general bit line sense amplifier.

Referring to FIG. 1, a driving driver of a pull-up and pull-down power line includes a pull-up power line driver 101 for applying a core voltage VCORE to a pull-up power line rto and a ground voltage VSS to a pull-down power line sb. ) Is provided as a pull-down power line driver 103 for applying a pre-charge voltage VBLP to a pull-up power line rto and a pull-down power line rto and a pull-down power line sb.

Briefly describing the operation, first, the precharge voltage VBLP is applied to the pull-up and pull-down power lines rto and sb by the bit line equalizer enable signal bleq of which the logic level is high, and the pull-up enable signal ( sap) and the pulldown enable signal san are kept at a logic level low.

At this time, when the internal read signal is input, the bit line equalizer enable signal bleq transitions to a logic level low, and the pull-up enable signal sap and the pull-down enable signal san transition to a logic level high.

Therefore, the core voltage VCORE is applied to the pull-up power supply line rto, and the ground voltage VSS is applied to the pull-down power supply line sb.

In other words, charge sharing is performed on the bit line pairs (bit lines and bit line bars) to amplify the data causing the potential difference between the bit line pairs to the core voltage VCORE and the ground voltage VSS.

However, if only the core voltage VCORE is used in a DRAM where the operating voltage decreases, it is difficult to amplify the data of many cells in a short time.

In order to solve this problem, the pull-up power supply line rto of the bit line sense amplifier may be connected to a voltage higher than the core voltage VCORE for a predetermined period of time at the beginning of operation of the bit line sense amplifier immediately after the charge sharing between the memory cell and the bit line. In general, a bit line sense amplifier overdriving method driven by an external power supply voltage (VDD) is adopted.

2 is a graph showing the potential difference between a pair of bit lines (bit line and bit line bar) when the bit line sense amplifier is driven.

Referring to FIG. 2, a bit line and a bit line bar charge shaded from a memory cell by a word line enable signal WL maintain a slight potential difference. At this time, when the bit line sense amplifier of FIG. 1 is driven, the potential is shifted to the bit line as the core voltage and the bit line bar to the ground voltage. When the overdriving operation of driving the pull-up power line rto with an external power supply voltage that is higher than the core voltage is performed, the bit line rises to a voltage level higher than the core voltage.

Subsequently, after the overdriving operation is completed, the core voltage is applied to the pull-up power line rto again.

At this time, the core voltage is caused to enter the current due to the external power supply voltage applied to the pull-up power supply line (rto), thereby increasing the voltage level of the core voltage.

In order to drop the voltage level of the elevated core voltage to the reference core voltage, the semiconductor memory device is provided with a level detector for discharge.

3 is a circuit diagram illustrating a circuit including a level detector for discharging a core voltage whose voltage level rises due to an overdriving operation of a bit line sense amplifier.

Referring to FIG. 3, an overdriving driver 303, a level detector 301, and a discharge driver 305 are provided. First, the overdriving driver 303 is turned on by an overdriving signal saovb. The transistor P1 raises the voltage level of the core voltage VCORE, which is the voltage level of the pull-up power supply line of the bit line sense amplifier, to the voltage level of the external power supply voltage VDD.

The level detector 301 is driven by the level detector enable signal DET_EN, and the half-core voltage HALF_VCORE, which is 1/2 of the elevated core voltage VCORE, and the reference voltage, which is 1/2 of the reference core voltage. The discharge signal dis_chg is output when the half-core voltage HALF_VCORE is higher than the reference voltage VREFC by comparing the VREFC.

Subsequently, the discharge driver 305 drops the voltage level of the core voltage VCORE raised by the NMOS transistor N1 turned on by the discharge signal dis_chg to the reference core voltage level through discharge.

4 is a circuit diagram illustrating the level detector 301 of FIG. 3.

Referring to FIG. 4, the level detector 301 outputs a discharge signal dis_chg using the output signal of the comparator 401 and the comparator 401 driven by the level detector enable signal DET_EN as an input. The output unit 403 is provided.

Referring to the brief operation, first, the comparator 401 is driven by the first NMOS transistor N1 turned on by the level detector enable signal DET_EN. In addition, the half-core voltage HALF_VCORE, which is a half voltage level of the elevated core voltage due to the overdriving operation of the bit line sense amplifier, is input to the second NMOS transistor N2, and at the same time, half of the reference core voltage. The reference voltage VREFC which is a voltage level is input to the third NMOS transistor N3.

At this time, since the voltage level of the half-core voltage HALF_VCORE is higher than the voltage level of the reference voltage VREFC, more current flows in the second NMOS transistor N2 so that the output A of the comparator 401 is at a logic level. Goes low.

Subsequently, the output unit 403 turns on the PMOS transistor P1 by the output signal of the logic level low of the comparator 401 to output the discharge signal dis_chg having the logic level high.

5 is a circuit diagram illustrating a level detector enable signal generator that generates the level detector enable signal of FIG. 3.

Referring to FIG. 5, a bank-by-bank structure representing a general 4-bank structure is performed by combining bitline sense amplifier overdriving signals (ovdb0, ovdb1, ovdb2, and ovdb3) to perform an overdriving operation with each bank as one overdriving driving signal. The overdriving signal combination circuit 501 is used.

The overdriving signal combination circuit 501 is configured to overdrive the first overdriving signal ovdb0 for overdriving the bit line sense amplifier of the first bank and the second overdriving signal ovdb1 for overdriving the bitline sense amplifier of the second bank. A third overdriving signal ovdb2 for overdriving the first NAND gate NAND1 and a bit line sense amplifier of the third bank and a fourth overdriving signal for overdriving the bit line sense amplifier of the fourth bank. The output signal of the second NAND gate NAND2 and the first NAND gate NAND1 and the output signal of the second NAND gate NAND2 are input as (ovdb3) to output the overdriving combined signal ovdb_all. The first NOR gate NOR1 may be implemented.

The delay circuit 503 outputs a signal delayed by a delay including delay information by inputting the overdriving combined signal ovdb_all or the overdriving signals ovdb0, ovdb1, ovdb2, and ovdb3 for each bank.

The delay circuit 503 is configured to delay the overdrive combination signal ovdb_all or the overdriving signals ovdb0, ovdb1, ovdb2, and ovdb3 for each bank, and a first delay for inverting the output signal of the first delay. A third NAND gate NAND3 that receives an inverter INV1, an overdriving combination signal ovdb_all, or an output signal of an overdriving signal ovdb0, ovdb1, ovdb2, ovdb3 for each bank and the first inverter INV1, and The output signal of the third NAND gate NAND3 is inverted to correspond to the overdriving delay combination signal ovdb_allp corresponding to the overdriving combination signal ovdb_all or the overdriving signals ovdb0, ovdb1, ovdb2, and ovdb3 for each bank. The second inverter INV2 outputs the overdriving delay signal ovdbp.

Next, an output circuit 505 for outputting the level detection part enable signal DET_EN by inputting the overdriving delay combination signal ovdb_allp or the overdriving delay signal ovdbp (hereinafter referred to as an input signal of an output circuit).

The output circuit 505 may include a second delay delay_r1 for delaying an input signal of the output circuit, a third inverter INV3 for inverting the output signal of the second delay delay_r1, an input signal of the output circuit, and a fourth inverter ( A second NOR gate NOR2 having the output signal of INV4 as an input, a third delay delay_r2 delaying the output signal of the second NOR gate NOR2, and an inverting output signal of the third delay delay_r2 5 The fourth delay delaying the output signal of the third NOR gate NOR3 and the third NOR gate NOR3 that input the input signal of the inverter INV5, the output circuit and the output signal of the fourth inverter INV4 ( delay_r3), the fifth inverter INV5 for inverting the output signal of the fourth delay delay_r3, the fourth NOR gate NOR4 for inputting the output signal of the output circuit and the output signal of the fifth inverter INV5, and the fifth inverter INV5. 4 The level detector enable signal DE by inverting the output signal of the NOR gate NOR4. The sixth inverter INV6 output to T_EN may be implemented.

6A and 6B are timing diagrams of the level detector enable signal generator of FIG. 3.

6A is a timing diagram illustrating an overdriving operation and a discharge operation of bit line sense amplifiers of a first bank and a second bank in a general 4-bank structure. The first bank and the second bank share one level detector. To perform the discharge operation.

When the active signal ACT BANK0 of the first bank is input in synchronization with the external clock CLK, the first overdriving signal ovdb0 is activated to a logic level low so that the sense amplifier of the first bank performs an overdriving operation. .

Subsequently, the first overdriving signal ovdb0 is output as the first overdriving delay signal ovdbp0 via the delay circuit of FIG. 5.

The first overdriving delay signal ovdbp0 is activated through the output circuit of FIG. 5 and the first level detector enable signal DET_EN0 is activated at a logic level high corresponding to the rising edge of the first overdriving delay signal ovdbp0. Is generated.

However, when the active signal ACT BANK1 of the second bank is input while the first level detector enable signal DET_EN0 is activated, the detection amplifier overdriving operation of the second bank and the first and second banks are performed. It can be seen that a section A in which the discharge operation of the level detection unit shared by each other is simultaneously performed.

Similarly, in FIG. 6B, the logic corresponding to the activation interval of the overdriving combination signal ovdb_all generated through FIG. 5 to the second logic level row and the activation of the overdriving combination signal ovdb_all to the first logic level row is similarly described. It can be seen that the activation periods of the level detector enable signal DET_EN1 activated at the level high overlap (B). 6B shows that four banks operate by sharing one level detector.

As described above, the overdriving operation is insignificant because the discharge operation section and the overdriving operation section overlap, and thus, the amplification efficiency of the bit line sense amplifier decreases.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor memory device that increases the amplification efficiency of the bit line sense amplifier by preventing the discharge operation section and the overdriving operation section from overlapping each other. For that purpose.

According to an aspect of the present invention for achieving the above technical problem, the discharge operation period and the overdriving period of the level detector for lowering the elevated core voltage to the reference core voltage level due to the overdriving operation of the bit line sense amplifier In order to solve the problem that the overdriving operation is meaningless due to overlapping operation sections, a level detector enable signal is generated to disable the discharge operation during the overdriving operation period by using an overdriving signal that enables the overdriving driver. A semiconductor memory device is provided.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

7 is a circuit diagram illustrating a level detector enable signal generator according to an exemplary embodiment of the present invention. The level detector is configured to perform a discharge operation by sharing all four banks.

First, referring to FIG. 7, the level detector enable signal generator deactivates the level detector enable signal DET_EN_all during an overdriving operation in order to prevent the overdriving operation section and the discharge operation section from overlapping each other. 4 bank structure-Overdriving signal combination circuit 701 that combines bitline sense amplifier overdriving signals (ovdb0, ovdb1, ovdb2, ovdb3) to perform overdriving operation with each overdriving drive signal. A delay circuit 703 and an overdriving signal combination circuit 701 for outputting a signal delayed by a delay including delay information by inputting the overdriving combination signal ovdb_all which is an output signal of the overdriving signal combination circuit 701. Overdriving combination signal (ovdb_all), which is an output signal of The ice-separation delayed combined signal (ovdb_allp) as input and having an output circuit 705 for outputting an enable signal (DET_EN) level detection.

The overdriving signal combination circuit 701 is configured to overdrive the first overdriving signal ovdb0 for overdriving the bitline sense amplifier of the first bank and the second overdriving signal ovdb1 for overdriving the bitline sense amplifier of the second bank. A third overdriving signal ovdb2 for overdriving the first NAND gate NAND1 and a bit line sense amplifier of the third bank and a fourth overdriving signal for overdriving the bit line sense amplifier of the fourth bank. The output signal of the second NAND gate NAND2 and the first NAND gate NAND1 and the output signal of the second NAND gate NAND2 are input as (ovdb3) to output the overdriving combined signal ovdb_all. The first NOR gate NOR1 may be implemented.

The delay circuit 703 may include a first delay for delaying the overdriving combination signal ovdb_all, a first inverter INV1 for inverting an output signal of the first delay, an overdriving combination signal ovdb_all, and a first delay. 1 The overdrive delay combination signal ovdb_allp corresponding to the overdriving combination signal ovdb_all by inverting the output signals of the third NAND gate NAND3 and the third NAND gate NAND3 that take the output signal of the inverter INV1 as an input. ) May be implemented as a second inverter INV2.

Also, the output circuit 705 may include a second delay delay_r1 for delaying the overdriving combination signal ovdb_all, a third inverter INV3 for inverting the output signal of the second delay delay_r1, and an overdriving combination signal ovdb_all. ) And the third delay (delay_r2) and the third delay (delay_r2) of delaying the output signal of the second NOR gate (NOR2), the second NOR gate (NOR2) to the output signal of the fourth inverter (INV4) Output of the third NOR gate NOR3 and the third NOR gate NOR3 that input the fifth inverter INV5 for inverting the output signal, the overdriving combined signal ovdb_all, and the output signal of the fourth inverter INV4. Input the fourth delay (delay_r3) for delaying the signal, the fifth inverter (INV5) for inverting the output signal of the fourth delay (delay_r3), the overdriving combined signal (ovdb_all), and the output signal for the fifth inverter (INV5). Fourth NOR gate NOR4 and overdriving signal combination circuit 701 In the case of overdriving operation, the output signal of the sixth inverter INV6 and the sixth inverter INV6 and the output signal of the fourth NOR gate NOR4 are inverted. The fifth NOR gate NOR5 outputting the deactivated level detector enable signal DET_EN_all may be implemented.

8 is a timing diagram of a level detector enable signal generator of FIG. 7.

Referring to FIG. 8, a timing diagram illustrating an overdriving operation and a discharge operation of bit line sense amplifiers of a first bank and a second bank in a general 4-bank structure, in which four banks share one level detector and display a discharge. Perform a charge operation.

When the active signal ACT BANK0 of the first bank is input in synchronization with the external clock CLK and then the active signal ACT BANK1 of the second bank is input, the first overdriving signal ovdb0 and the second overdriving signal. The ovdb1 is activated, and the overdriving combined signal ovdb_all is output through the overdriving signal combining circuit of FIG. 7.

By the first activation of the overdriving combination signal ovdb_all, the first bank performs an overdriving operation. When the overdriving operation is completed, the level detector enable signal DET_EN_all is activated to generate the core voltage that has risen due to the overdriving operation. Drop the voltage level.

When the overdriving combination signal ovdb_all is activated for the second time while the level detector enable signal DET_EN_all is activated, the level detection unit enable signal is generated by the overdriving combination signal ovdb_all in the output circuit of FIG. 7. (DET_EN_all) transitions to a logic level low. That is, when the overdriving combination signal ovdb_all is activated, the level detector enable signal DET_EN_all is deactivated.

As described above, in order to solve the problem of overlapping of the conventional overdriving operation section and the discharge operation section so that the overdriving operation is meaningless, the present invention relates to an activation section of the overdriving combination signal ovdb_all, which is an overdriving operation signal. The deactivation period of the corresponding level detector enable signal DET_EN_all is generated so that the discharge operation is not performed during the overdriving operation of the detection amplifier.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, since the type and arrangement of the logic used in the above-described embodiment is implemented as an example in which both the input signal and the output signal are high active signals, the implementation of the logic may also change when the active polarity of the signal is changed. There is no such embodiment, because the number of cases is too large, and the change in the embodiment is a matter that can be easily technically inferred by those skilled in the art of the present invention belongs directly to each case I will not mention it.

In addition, in the above-described embodiment, the level detector enable signal has been described as an example of implementing a plurality of logic circuits, but this is also merely one implementation.

As described above, the present invention solves the problem that the overdriving operation is meaningless because the overdriving operation section and the discharge signal generator operation section overlap.

Therefore, the overdriving operation of the bit line sense amplifier can be performed, thereby increasing the sensing efficiency of the sense amplifier.

Claims (5)

In a semiconductor memory device having a plurality of banks, A normal driving driver for driving the pull-up power supply line of the bit line sense amplifier to a normal driving voltage; An overdriving driver for driving a pull-up power line of the bit line sense amplifier to an overdriving voltage; A discharge driver for dropping the normal driving voltage having the voltage level increased due to the overdriving driving to a reference normal driving voltage level through discharge; And A level detector configured to drive the discharge driver by comparing the normal driving voltage with a reference voltage; A level detector enable signal generator configured to output an enable signal of the level detector so that the overdriving section and the discharge section do not overlap in response to a combination of the plurality of bank overdriving signals Semiconductor memory device comprising a. The method of claim 1, The level detector enable signal generator, A first delay unit configured to delay and output an enable signal of the overdriving driver; A second delay unit delaying and outputting an output signal of the first delay unit; And And an output unit configured to combine the output signal of the first delay unit and the output signal of the second delay unit to output an enable signal of the discharge driver. The method of claim 2, The first delay unit, A delay delaying an enable signal of the overdriving driver; A first inverter for inverting the output signal of the delay; A NAND gate as an input of an enable signal of the overdriving driver and an output signal of a first inverter; And a second inverter for inverting the output signal of the NAND gate. The method of claim 2, The second delay unit, A first delay delaying an output signal of the first delay unit; A first inverter for inverting the output signal of the first delay; A first NOR gate configured to receive an output signal of the first delay unit and an output signal of the first inverter; A second delay delaying an output signal of the first NOR gate; A second inverter for inverting the output signal of the second delay; A second NOR gate configured to receive an output signal of the first delay unit and an output signal of the second inverter; A third delay delaying an output signal of the second NOR gate; A third inverter for inverting the output signal of the third delay; And And a third NOR gate configured to receive an output signal of the first delay unit and an output signal of the third inverter. The method of claim 2, The output unit, An inverter for inverting an enable signal of the overdriving driver; And And a NOR gate configured to output an enable signal of the discharge driver by inputting an output signal of the second delay unit and an output signal of the inverter.

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