KR20100028823A - Circuit and method for generation internal voltage - Google Patents

Abstract

PURPOSE: An internal voltage generation circuit and a method for controlling the same are provided to control the operation power of a chip by combining a bank address signal and a pulse signal. CONSTITUTION: An internal voltage drivers(60 to 68) generate each bank enable voltage to memory which are divided in two or more areas. An internal control unit(70) generates a bank enable signal by combining a pulse signal generated with a write/read command and a bank address signal. The bank enable signal controls the internal voltage drivers based on the operational area of the memory. The internal voltage control unit includes a first decoding unit, a second decoding unit, a delay unit and a pulse generation unit. The first decoding unit combines the bank address signal and the reverse signal of the bank address signal to decode. The second decoding unit combines the pulse signal and the output signal of the first decoding unit to decode. The delay unit delays the output signal of the second decoding unit. The pulse generation unit generates the bank enable signal.

Description

Internal voltage generation circuit and control method {CIRCUIT AND METHOD FOR GENERATION INTERNAL VOLTAGE}

The present invention relates to a circuit design in a semiconductor memory device, and more particularly, to an internal voltage generation circuit and a control method for generating a core voltage used as an internal power supply.

The semiconductor memory device is used in various fields, but one of them is used to store various kinds of data. Since such semiconductor memory devices are used in various portable devices, including desktop computers and notebook computers, large capacity, high speed, small size, and low power are required.

As a method for designing a semiconductor memory device according to the low power, a technology for minimizing current consumption in a core area of a memory has been proposed. The core region is composed of a memory cell, a bit line, and a word line, and is designed according to an extremely fine design rule. Therefore, in order to design a semiconductor memory device that is extremely fine and high frequency operation, the power supply voltage is basically low.

On the other hand, the semiconductor memory device generates and uses power of a required size inside the device using an external power supply voltage of a predetermined value or less. Among them, in the case of a memory device using a bit line sensing amplifier such as DRAM, a core voltage Vcore is used to detect cell data. When a word line is activated, data of a plurality of memory cells connected to the word line is transferred to the bit line, and the bit line sense amplifier senses and amplifies the voltage difference between the pair of bit lines. When these thousands of bitline sense amplifiers operate at the same time, they use pull-up power lines and consume large amounts of current from the core voltage stages used. Therefore, in the memory device, the internal voltage generator is controlled on / off according to a required area and a required operation to effectively adjust power.

1 is a block diagram of a conventional internal voltage generation circuit. The driver (VCORE_STBDRV: 10) is a driver that is always in an operating state regardless of the operating state of the memory or the use area of the core voltage. Therefore, the driver 10 receives a constant bias voltage at all times without controlling the enable signal.

And a core voltage driver VCORE_ACTDRV for generating the core voltage required by the bank. In the illustrated example, four banks and a core voltage driver for generating a core voltage used in each bank are described.

The drivers 12 to 18 for generating the core voltage of each bank are input with an active bank control signal ACT_BK. The active bank control signal is input to an enable signal input terminal and performs a function of controlling on / off operation of each driver.

The active bank control signal ACT_BK input to each of the drivers is generated in accordance with a required area and a required operation in the core voltage control unit VCORE_CTRL: 20.

2 shows a detailed configuration diagram of the core voltage control unit 20. The control signal RACT is used when the active command enters the bank and becomes a high signal when the precharge command is entered.

In the example shown in FIG. 3, the operation waveform diagram when the active signal and the precharge signal enter the bank <0> is explained. That is, the control signal RACT <0> becomes high by the active 0 command and then transitions to the low state by the precharge 0 command. Accordingly, the control signal RACT <0> rises immediately when the control signal RACT <0> rises using the constant delay 26, and the active bank control signal ACT_BK <0> is generated when the control signal RACT <0> rises.

4 illustrates a control signal waveform according to a memory operation when a conventional internal voltage controller is used. The active bank control signal is enabled in the high state according to the active signal of each bank, and the high level is maintained until the precharge command is issued.

However, when the write operation is performed to the bank 0 by the write command signal WT0, the power consumption period is only a hatched area. That is, as the active bank signal is enabled by the active command, unnecessary power consumption is generated in the internal voltage generator.

Similarly, in the case of performing the control of bank 2 to bank 4, the active bank signal is enabled by the active command and power consumption occurs. However, the section in which power is consumed by the command operation by the actual command command is described above. As you can see, this is just a few areas.

As described above, in the conventional internal voltage generation circuit, although the importance of power is very important in designing a memory and the market demand for a memory that consumes less power is increasing, in the internal voltage generation circuit that generates the core voltage, There is a problem in that the power consumption by the standby current is unnecessarily large.

Accordingly, an object of the present invention is to provide an internal voltage generation circuit and a control method capable of minimizing power consumption due to standby current.

An internal voltage generation circuit according to the present invention for achieving the above object, the internal voltage driver for generating a respective bank using voltage for the area (bank) of two or more divided memory; And an internal voltage controller configured to generate a bank enable signal for controlling the internal voltage driver according to an operation period of a memory by combining a bank address signal and a pulse signal generated by a write / read command.

In addition, the internal voltage generation method according to the present invention generates a bank enable signal by arithmetic combination of a bank address signal and a pulse signal generated by a write / read command, and generates an inverse signal of the bank address signal and the bank address signal. A first step of combining and decoding; A second step of combining and decoding the pulse signal generated when a write / read command is applied and the decoding signal; A third step of delaying the decoded signal of the second step for a predetermined time; And a fourth step of generating a bank enable signal using the delayed signal.

The present invention is characterized in that a bank enable signal is generated by a combination of a bank address signal and a pulse signal generated by a write / read command. According to this aspect, the present invention can control the internal voltage generating circuit to operate only in a required region and a required section, thereby minimizing unnecessary power consumption and efficiently controlling the operating power of the entire chip.

Hereinafter, an internal voltage generation circuit and a control method according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of an internal voltage generation circuit according to an embodiment of the present invention.

The internal voltage generating circuit according to the present invention shown in Fig. 2 is a driver which is always in operation regardless of the operation state of the memory or the use area of the core voltage, and is always operated under a constant bias voltage without controlling the enable signal (VCORE_STBDRV). : 60).

In addition, the present invention includes a core voltage driver (VCORE_ACTDRV) for generating the core voltage required by the bank. In the illustrated example, four banks and a core voltage driver for generating a core voltage used in each bank are separately disposed. The number of banks and the configuration of the core voltage driver to be in common charge for all banks or to be independently managed may be designed differently depending on the characteristics of use.

The active bank control signal ACT_BK is input to the drivers 62 to 68 for generating the core voltage of each bank. The active bank control signal is input to an enable signal input terminal and performs a function of controlling on / off operation of each driver.

The active bank control signal ACT_BK input to each of the drivers is generated in accordance with a required area and a necessary operation in the core voltage control unit VCORE_CTRL: 70. The core voltage controller 70 according to the present invention uses the YBST signal which always generates a high pulse signal when the write / lead command is applied to the corresponding bank, and uses the bank address information to actually consume the core voltage in the corresponding region. Only the interval is configured to generate a bank enable signal for enabling the core voltage driver.

That is, according to the above structure, the internal voltage generation circuit of the present invention is composed of a driver 60 which is always largely in a driving state, and core voltage drivers 62 to 68 which operate in accordance with a required area and a required operation.

The core voltage control unit 70, in setting the operation period of the core voltage drivers 62 to 68, has a YBST signal that always generates a high pulse signal when a write / read command is applied to the corresponding bank, The bank enable signal is generated using the bank address information to enable the core voltage driver only in a section in which the core voltage is actually consumed in the corresponding area.

Accordingly, the core voltage drivers 62 to 68 operate on / off by the bank enable signal generated only in the section in which the core voltage controller 70 consumes the actual core voltage, thereby controlling core voltage generation to be used in the bank.

Next, an operation process of how the core voltage controller is configured to control the generation of a bank enable signal only in a section consuming an actual core voltage will be described.

6 is a detailed block diagram of the core voltage controller 70 according to the embodiment of the present invention.

The core voltage control part 70 of the present invention is controlled by the control signal YBST signal which is a high pulse signal which always occurs the same when the bank address BK <0: 1> and the write / lead (WT / RD) command are applied. .

That is, the inverter 74 converts a bank address <0> signal, a signal in which the bank address <0> signal is inverted by the inverter 72, a bank address <1> signal, and the bank address <1> signal. And NAND gates 78 to 84 that combine and decode the inverted signals.

Noah gates 86 to 92 for combining the output signals of the NAND gates 78 to 84, the signal inverted by the inverter 76, and the inverters 94 to 100 for inverting the output of the NOR gate. ), Delay units 102 to 108 for delaying the output of the inverters 94 to 100 for a predetermined time.

The NAND gate 110 generating a bank enable signal EN_BK in which a pulse width is extended by a delay time of the delay unit by combining the output signals of the inverters 94 to 100 and the output signals of the delay units 102 to 108. 116).

According to the above configuration, the core voltage controller according to the embodiment of the present invention operates as follows.

7 shows an output waveform diagram of a signal input to the core voltage controller and an output signal of the present invention.

That is, the core voltage controller of the present invention decodes the bank address signals BK <0> and BK <1> by the combination of the inverters 72, 74 and the NAND gates 78 to 84, and then reverses the level signals of the YBST signals. And NOR 86 to 92, the output signal of the NAND gate is generated to generate a bank enable signal EN_BK in which the pulse width is extended by a predetermined delay time.

Therefore, as shown in FIG. 7, the banks 0 to 3 are sequentially activated, and when the write command WT is applied, the YBST signal generated by the write command WT is extended by a predetermined delay time. Only when the bank is written to the bank enable signal EN_BK is generated.

8 shows a waveform diagram of a control signal according to a memory operation when the internal voltage generation circuit according to the present invention is applied to a memory device.

When banks 0 to 3 are sequentially activated and a write WT command is sequentially applied, the YBST signal generated by the write WT command is extended by a predetermined delay time to generate a bank enable signal. It can be seen that the generated bank enable signal is generated only in a power consumption period by an actual light.

Therefore, the bank enable signal EN_BK0 for controlling the bank 0 is generated by extending the YBST signal generated when the write signal WT0 enters by a predetermined delay time between the active signal ACT0 and the precharge signal PCG0.

Similarly, the bank enable signal EN_BK1 for controlling the bank 1 is generated by extending the YBST signal generated when the write signal WT1 enters by a predetermined delay time between the active signal ACT1 and the precharge signal PCG1.

The bank enable signals EN_BK2 and EN_BK3 for controlling the banks 2 and 3 are input to the active signals ACT2 and ACT3 successively, and in the section where the write signals WT2 and WT3 are applied before the precharge signals PCG2 and PCG3. It is generated by applying a bank address signal to the YBST signal. Of course, even in this case, the bank address signals EN_BK2 and EN_BK3 are generated only in the power consumption period by the actual write.

9 shows a detailed view of a core voltage driver according to an embodiment of the present invention.

As shown, the core voltage drivers 62 to 68 of the present invention have a feedback voltage and a reference voltage VREFC (one of the target core voltages) composed of a half core voltage that is half level of the core voltage terminal potential. / 2 level; 0.75V) differential comparison unit, amplifying unit for generating and outputting the amplified core voltage in response to the output signal of the comparison unit, and voltage distribution of the output core voltage, monitoring the output core voltage In order to provide a feedback voltage generating unit for generating a feedback voltage which is 1/2 level of the core voltage terminal potential. And a control switching unit for controlling the operation of the comparison unit is included.

The core voltage driver configured as described above supplies the bank enable signal EN_BK generated by the core voltage controller 70 to the gate terminal of the NMOS transistor N3 constituting the control switching unit, and compares the result by the control switching unit. The negative operating point is controlled to be determined.

When the bank enable signal is applied to the NMOS transistor N3 and is in the turn-on state, the NMOS transistor N1 is turned on by the reference voltage VREFC so that the transistor N1 and the transistor N2 are turned on. The drain voltage is lowered. In other words, the potential of the node A is lowered. The low level signal is applied to the gate terminal of the PMOS transistor P3 operated by the voltage applied to the node A, and the core voltage VCORE output as the transistor P3 is turned on becomes high.

When the core voltage VCORE is raised, the feedback voltage is also raised while turning on the transistor N2. When the transistor N2 is turned on, the potential of the node B is lowered and the gate terminal voltages of the PMOS transistors P1 and P2 are lowered. When the gate terminal voltages of the PMOS transistors P1 and P2 are lowered, the potential of the node A is gradually increased while being turned on. In other words, the gate voltage of the transistor P3 is gradually raised. This operation is performed until the feedback voltage and the reference voltage VREFC are equal.

The above-described preferred embodiment of the present invention is disclosed for the purpose of illustration, and may be applied to the case where the operation state of the core voltage driver is controlled to be performed only in a required region and a required operating period. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

For example, the embodiment of the present invention has described an internal voltage generation circuit in which a core voltage is generated. However, the present invention is not limited thereto, and the present invention may be equally applicable to other internal power sources (eg, ferry voltage VPERI) that need to drive a separate voltage generator by consuming power during read / write operations.

In addition, although the embodiment of the present invention describes the light WT process, the present invention may be similarly applied to the read RD process.

1 is a block diagram of a conventional internal voltage generation circuit,

2 is a detailed configuration diagram of a core voltage controller shown in a conventional internal voltage generation circuit;

3 is an operation waveform diagram when an active signal and a precharge signal enter a bank <0> in a conventional internal voltage generation circuit;

4 is a waveform diagram of a control signal according to a memory operation when using a conventional internal voltage controller;

5 is a block diagram of an internal voltage generation circuit according to an embodiment of the present invention;

6 is a detailed configuration diagram of a core voltage controller according to an embodiment of the present invention;

7 is an output waveform diagram of a signal input to the core voltage controller and an output signal of the present invention;

8 is a waveform diagram of a control signal according to a memory operation when the internal voltage generation circuit according to the present invention is applied to a memory device;

9 is a detailed view of a core voltage driver according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

60: driver 62 ~ 68: core voltage driver

70: core voltage control unit

Claims (12)

An internal voltage driver for generating respective bank use voltages for two or more divided areas of the memory; And an internal voltage controller configured to combine a bank address signal and a pulse signal generated by a write / read command to generate a bank enable signal for controlling the internal voltage driver according to an operation period of a memory. Generating circuit. The method of claim 1, The internal voltage controller may include: a first decoding unit configured to decode a combination of a bank address signal and an inverse signal of the bank address signal; A second decoding unit for combining and decoding a pulse signal generated when a write / read command is applied and an output signal of the first decoding unit; A delay unit for delaying the output signal of the second decoding unit for a predetermined time; And a pulse generator for generating a bank enable signal by using the output signal of the delay unit. The method of claim 2, And the first decoding unit comprises a combination of an inverter and a NAND gate. The method of claim 3, wherein And the second decoding unit is configured of a noar gate. The method of claim 1, The internal voltage driver is provided separately for each bank. The method of claim 5, wherein The internal voltage driver may include a comparison unit configured to differentially compare a reference voltage and a feedback voltage; Amplifying means for amplifying and outputting an external power supply voltage based on the signal output from the comparing unit; And And a control switching unit configured to control an operation of the comparator according to a bank enable signal generated by the internal voltage controller. The method of claim 1, The internal voltage is a core voltage. The method of claim 7, wherein And an operation period of a memory for controlling the generation of a bank enable signal in the internal voltage control unit is a read / write operation period. And generating a bank enable signal by arithmetic combination of a bank address signal and a pulse signal generated by a write / lead command. The method of claim 9, A first step of combining and decoding a bank address signal and an inverse signal of the bank address signal; A second step of combining and decoding the pulse signal generated when a write / read command is applied and the decoding signal; A third step of delaying the decoded signal of the second step for a predetermined time; And a fourth step of generating a bank enable signal by using the delayed signal. The method of claim 10, The internal voltage is a core voltage. The method of claim 11, And an operation period of a memory for controlling the generation of the bank enable signal is a read / write operation period.

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