KR100336370B1 - Roo-Repair Circuit Using Roo-Decoder - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low repair circuit of a semiconductor memory device. In particular, since a low repair circuit exists in a low decoder, a low address signal is inputted, decoded, and output as a normal word line so that a repair circuit is not required. A row decoding unit 10; A low repair word line driver 20 for repairing by turning on the repair word line RWLi; And generate a signal for repair at a next stage of the row decoding unit 10 that decodes the input row address. The row repair word line driver 20 according to the output decoded by the row decoding unit 10. It relates to a low repair circuit using a low decoder comprising a repair signal generator 30 for generating a normal low disable signal (nrd) for driving ().

Description

Roo Repair Circuit Using Roo Decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low-order repair circuit using a low-order decoder, and more particularly, to a semiconductor memory device in which a low-order repair circuit is not required because a low-order repair circuit exists in the low-order decoder.

In general, if any one of a number of fine cells is defective, it cannot be used as a DRAM and is treated as a defective product.

However, as the density of DRAM increases, there is a high probability that defects will occur only in a small number of cells, but discarding it as a defective product is an inefficient treatment method that lowers the yield of good products.

Therefore, in this case, a redundancy circuit is adopted to increase the yield by replacing defective cells by using spare memory cells installed in the DRAM in advance.

The redundancy circuit replaces a word line to which a defective cell is connected with an extra redundancy word line when a defect occurs in any cell in the cell array. When an address is applied into the device, the normal path for selecting the defective cell is broken, and instead, the redundancy circuit operates to enable the word line to which the repaired cell is connected, thereby providing a redundancy operation.

FIG. 1 is a general low-repair circuit diagram using a conventional technology, as shown in FIG. 1, which is implemented as a circuit block in which a repair fuse 1 for repair is added, thereby operating a low decoder. It is moving regardless.

In order to overcome the problem of operating regardless of the ROH decoder, an operation such as operating a normal ROH disable signal (normal row disable hereinafter nrd), which is an output of the ROH repair circuit, on a signal for turning on the ROH decoder is operated. It was also.

FIG. 2 is a low repair word line driving circuit diagram of FIG. 1, and when a normal low disable signal nrd, which is an output of the low repair circuit, is input, the low repair word line is driven.

In addition, as shown in FIG. 3, the address signals gxa234 <0: 7> and gxa567 <0: 7> applied to the row decoder circuit block must also be applied to the block for the row repair of FIG. 1.

Therefore, the size of the row address predecoder driving stage increases due to the above problem, and there are also problems such as speed delay due to many nodes.

In the circuit design, two blocks exist separately, which causes problems such as unnecessary bus line increase and unnecessary chip area consumption.

That is, the conventional low repair structure has to use a separate address detection circuit for generating signals by receiving the eight inputs, so that the overall structure is complicated, which causes a large area in circuit design.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and provides a low repair circuit using a low decoder that does not require a repair circuit because the circuit for the low repair exists in the low decoder. Its purpose is to.

1 is a typical row repair circuit diagram,

FIG. 2 is a row repair wordline driving circuit diagram for FIG. 1;

3 is a typical row decoder circuit diagram;

4 is a low repair circuit using a low decoder according to the present invention;

5 is a configuration diagram of a row decoder array to which the present invention is applied.

<Explanation of symbols for the main parts of the drawings>

10: Roo decoding unit 20: Roo repair word line driver

30: repair signal generator

In order to achieve the above object, the low repair circuit of the present invention includes a first fuse FUSE_1, and decodes the low address signal to normalize the decoded signal according to the cutting state of the first fuse FUSE_1. A row decoding unit 10 outputting a word line; A low repair word line driver 20 driving the repair word line corresponding to the normal word line in the repair state; A first charging means (32), a second switching means (34), and a third switching means (36), and a precharge means (38) comprising a second fuse (FUSE_2), repairing a row address signal. By the precharge signal of the precharge means 38 according to the cutting state of the second fuse FUSE_2 corresponding to whether or not the switching operation of the first, second, and third switching means 32, 34, 36 is performed. By the repair signal generator 30 is determined, in the normal state in which the first fuse FUSE_1 and the second fuse FUSE_2 are connected, the row decoding unit 10 decodes the row address signal to the normal word line. And a signal decoded by the row decoding unit 10 in the repair state in which the first fuse FUSE_1 and the second fuse FUSE_2 are cut through the first and second switching means 32 and 34. Output to the row decoding unit 10 to clear the normal word line, and the first and third switching means 32, Output to the row word line driver 20 via 36 to control the driving of the row repair word line.

Also, a plurality of row decoders 100 including a row decoding unit 10 and a repair signal generation unit 30 are provided, and a plurality of row decoders are provided via the first switching means 32 and the third switching means 36. The signal decoded by the row decoding unit 10 is input to the single row repair word line driver 20 so that the single row repair word line driver 20 is commonly used by the plurality of row decoders 100. It is characterized by.

The operation principle according to the present invention will be described in detail as follows.

Repairing is performed by adding a circuit for repairing after the NAND gate NAND10 of the row decoding unit 10.

At this time, the repair method,

First, the first fuse FUSE_1 of the row decoding unit 10 is shorted, and then the second fuse FUSE_2 of the repair signal generator 30 is shorted.

Then, the output of the NAND gate NAND10 of the row decoding unit 10 receiving the address signal is transmitted to node 2 Node_2 of the repair signal generator 30 through node 1 Node_1, which is a node. The normal word line WLi of the row decoding unit 10 is cleared through 3 Node_3.

At this time, the normal low disable signal nrd, which receives the signal of the node 2 (Node_2) from the repair signal generator 30, drives the repair word line driver 20 to repair the repair word line RWLi. It will be repaired while turning on.

Thus, the problems presented above

1. Normal word line is not cleared after Loo Repair

2. To solve this problem, the signal (nrd) is loaded into the row decoder address.

3. Address Predecoder Drive Stage Increase Problem

4. Speed delay problem due to many nodes

5. Busline increase problem between ROH decoder block and ROH repair block

6. If the present invention is not used, it is possible to solve the problem of unnecessary consumption of chip area generated by dividing a block into two places.

As described in detail above, the present invention solves the problem of size delay in speed delay and address predecoder driving related to the address node by making a circuit for repairing at the next stage of the NAND gate for selecting the address of the loo decoder. By designing the block and the row repair block in one place, unnecessary bus line increase and chip area are eliminated.

In addition, the problem that the loo decoder and the loo repair circuit moves independently of each other, after the loo repair, only the loo repair word line is turned on and the normal word line is turned off.

Claims (2)

A row decoder having a first fuse and decoding the row address signal to output the decoded signal to a normal word line according to a cutting state of the first fuse; A row repair word line driver configured to drive a repair word line corresponding to the normal word line in a repair state; A precharge means including a first switching means, a second switching means, and a third switching means, and a second fuse, and according to a cutting state of the second fuse corresponding to whether to repair the row address signal. And a repair signal generator for determining the switching operation of the first, second, and third switching means by the precharge signal of the precharge means. In the normal state in which the first fuse and the second fuse are connected, the row decoder decodes the row address signal and outputs the row address signal to the normal word line. In the repair state in which the first fuse and the second fuse are cut, a signal decoded by the row decoding unit is output to the row decoding unit via the first and second switching means to clear the normal word line. And a row repair circuit output to the row repair word line driver through the first and third switching means to control driving of the row repair word line. The method of claim 1, A plurality of row decoders including the row decoding unit and the repair signal generator, Signals decoded by the plurality of row decoding units via the first switching means and the third switching means are input to the single row repair word line driver, and the single row repair word line driver A low repair circuit, which is commonly used by a low decoder.