KR0170705B1 - Redundancy decoder of semiconductor device - Google Patents

Abstract

Disclosed is a redundancy decoder circuit of a semiconductor device capable of significantly reducing a layout area.

In the redundancy decoder circuit of a semiconductor device provided with a fuse,

A redundancy decoder front end of a redundancy decoder that generates a word line enable signal of a redundancy cell by inputting an address of a defective cell and a predetermined delay means shared by a plurality of the redundancy decoders and connected fewer times than the front end of the redundancy decoder. It provides a redundancy decoder circuit of a semiconductor device, characterized in that consisting of.

Even if there are N front ends of the redundancy decoder, the rear end of the redundancy decoder which is the predetermined delay means may be smaller than N, so that at least one head may be configured.

Therefore, according to the present invention, the N redundant decoder circuits are connected to the rear end of the redundant decoder, which can be shared and used by only at least one, even if there are fewer than N in front of the N redundant decoders, thereby significantly reducing the layout area compared to the conventional redundant decoder circuits. A redundancy decoder circuit of a semiconductor device can be obtained which can be reduced.

Description

Redundancy Decoder of Semiconductor Devices

1 shows a block diagram of a redundancy decoder of the prior art.

2 and 3 show circuit diagrams of the first and second decoders of the prior art, respectively.

4 shows a block diagram of the redundancy decoder of the present invention.

5 shows a circuit diagram of a second decoder of the present invention.

TECHNICAL FIELD The present invention relates to semiconductor memory integrated circuits, and more particularly, to a redundancy decoder.

As semiconductor devices become more integrated, the number of redundancy cells that replace defective cells is increasing to improve the problem of cost increase. Yield must be guaranteed to reduce costs, and in particular, a redundancy role is essential to improve yield.

In general, a semiconductor memory cell array is composed of a normal cell array and a redundant cell array. When a defect occurs in a normal cell, the semiconductor memory cell array is replaced with a redundant cell. The alternative method replaces the defective cell by receiving the address information of the defective cell and enabling the word line of the redundant cell to output the redundancy decoder to drive the redundant cell. To replace a defective cell, a redundancy decoder having an electrical fuse is used to drive the redundancy cell by converting a signal generated by cutting the fuse into a signal having an appropriate delay to display address information of the defective cell. In this way, in order to secure timing margin between the regular decoder signal and the redundancy decoder signal, a delay means in the redundancy decoder is indispensable.

Therefore, in a typical case, a redundancy decoder comprising a first decoder having an electrical fuse and a second decoder having a predetermined delay means is used to drive one redundancy word line or a redundancy column.

1 shows a block diagram of a redundancy decoder of the prior art. Reference numeral 11 denotes a first address buffer, 13 denotes a first decoder, 15 denotes a second decoder, 21 denotes an Nth address buffer, 23 denotes a first decoder, and 25 denotes a second decoder. The conventional redundancy decoder combines an electrical fuse and uses a method in which its output drives a redundancy word line or a redundancy column through a predetermined delay means. Such a prior art redundancy decoder is composed of N first decoders and N second decoders, so that the layout area occupied by the entire redundancy decoder is rather large.

2 and 3 show a circuit diagram of each of the first and second decoders of the prior art. In Fig. 2, reference numerals 31 and 41 denote transfer gates, 33 and 43 in buffers, 32 and 34 and 42 and 44 electrical fuses, 35 and 45 NAND gates, 46 NOR gates and 47 inverters. 51, 52, 53, and 54 in FIG. 3 denote inverters of delay means, 55 denote NOR gates, and 56 denote inverters.

Specifically, the configuration and detailed operation are as follows. The first decoder needs address information of the defective cell in order to drive the redundancy cell. The first decoder outputs REPiB and REPi signals by inputting RAi, which is one output of each address buffer. The second decoder receives the REPiB as an input and generates a redundancy main word line signal RMWLi via delay means. That is, in the configuration in which N redundancy word lines and redundancy columns are mounted, N first decoders and N second decoders are configured.

Such a conventional configuration method requires N second decoders as well as N first decoders, so that the overall layout area of the redundancy decoder is somewhat larger.

Accordingly, an object of the present invention is to overcome the above problems, and even in a structure having a plurality of redundancy word lines and redundancy columns, a semiconductor device capable of remarkably reducing the layout area by using one of the above-described predetermined delay means in common. It is to provide a redundancy decoder circuit.

The present invention to achieve the above object,

In the redundancy decoder circuit of a semiconductor device provided with a fuse,

N bits of redundancy cell by logically combining the N first decoders for generating the word line enable signal of the redundancy cell with the address of the defective cell as input and the N redundancy cell enable signals generated at the first decoders. A redundancy decoder circuit of a semiconductor device is provided, comprising a second decoder for decoding an address.

The second decoder,

A first NAND gate for inverting and ORing the N redundancy cell enable signals, a first inverter for inputting the first NAND gate output, a delayer for inputting the first inverter output for a predetermined time delay, and the first A first NOR gate for inverting and ORing the output of the inverter and the output of the delayer, and the N inverted cell enable signals, which are inverted, respectively, and N inverted ANDs for the output of the first NOR gate, respectively; N second inverters each inputting and inverting each of the outputs of the N second NAND gates, and N third inverters each inputting and inverting the outputs of the N second inverters, respectively. It is characterized by consisting of inverters.

Therefore, according to the present invention, the redundancy decoder circuit can reduce the area of the second decoder by using only one delayer for delaying each of the N redundant cell enable signals output from the N first decoders. The redundancy decoder circuit of the semiconductor device can be obtained which can significantly reduce the layout area compared with the redundancy decoder circuit.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

4 shows a block diagram of the redundancy decoder of the present invention. Reference numeral 61 denotes a first address butter, 63 denotes a first decoder, 71 denotes an Nth address buffer, 73 denotes a first decoder, and 75 denotes a second decoder. As shown in the figure, in a semiconductor device equipped with a redundancy decoder, one second decoder is formed at the rear of the N first decoders to provide a conventional redundancy decoder circuit comprising N first decoders and N second decoders. In comparison, a redundancy decoder circuit of a semiconductor device capable of significantly reducing a layout area can be obtained. Accordingly, the present invention minimizes signal-bushing in configuring a redundancy decoder circuit that drives a redundancy cell by inputting address information of the defective cell when a defective cell occurs in a regular cell array. It relates to a redundancy decoder.

5 shows a circuit diagram of a second decoder that can be shared and used in the present invention. Reference numeral 81 is a first NAND gate, 82 is a first inverter, 83, 84, 85, 86 is an inverter used as a predetermined delay means, 87 is a first NOR gate, 88, 92 is a second NAND gate, 89, 93 denotes a second inverter, and 90 and 94 denote a third inverter.

The circuit connection relationship of the second decoder according to the present invention is as follows. A first NAND gate 81 for inverting and ORing N input redundancy cell enable signals output from the N first decoders, a first inverter 82 for inputting a first NAND gate output, and a first inverter A delay configured by a predetermined number of inverters 83, 84, 85, and 86 for inputting an output and delaying a predetermined time; a first NOR gate 87 for inverting and ORing the output of the first inverter and the output of the delay; N second NAND gates 88 and 92 which respectively input the inverted N redundancy cell enable signals and input and output the outputs of the first NOR gate, respectively, to each of the N second gates. N second inverters 89 and 93 for inputting and inverting the outputs of the NAND gates respectively and N third inverters 90 and 94 for inputting and inverting the outputs of the N second inverters, respectively. do.

A detailed operation will be described with reference to the drawings. The second decoder of the present invention has REPiB and REPi, which are outputs of the N first decoders (FIG. 2) as inputs, and has a retarder composed of inverters 83, 84, 85, 86 and 87, and redundancy of N. Outputs the main word line signal, RMWLi. Specifically, the signal of the node 'A' passing through the delay unit composed of inverters 83, 84, 85, 86, and 87 and the respective REPi signals are inputted by inputting the respective REPiB signals generated by the N first decoders. Combined, each RMWLi signal is output. For example, if the electrical fuse of the first first decoder is blown and REPiB1 and REPi1 are enabled as 'low' and 'high', then node 'A' remains 'high'. In addition, since the value of REPi other than REPi1 is 'low', only RMWLi1 is selected, not other RMWLi. As described above, since the delay decoder is commonly used in the second decoder including the delay unit, the layout area of the second decoder may be significantly reduced.

Accordingly, according to the present invention, a semiconductor device equipped with a redundancy decoder may be used in common in a second decoder including a delay unit for delaying N redundant cell enable signals output from N first decoders. As a result, the redundancy decoder circuit of the semiconductor device can be obtained which can significantly reduce the layout area compared with the redundancy decoder circuit constituting the N second decoders using N delay units.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (2)

A redundancy decoder circuit of a semiconductor device, comprising: N first decoders for inputting a N-bit defective cell address and generating N redundancy cell enable signals corresponding to each bit of the N-bit defective cell address; And a second decoder for logically combining the N redundancy cell enable signals generated in the first decoders to decode an N bit redundant cell address. 2. The apparatus of claim 1, wherein the second decoder comprises: a first NAND gate for inverting and ORing the N redundant cell enable signals; A first inverter inputting and inverting the first NAND gate output; A delay unit configured to delay the predetermined time by inputting the first inverter output; A first NOR gate inverting and ORing the output of the first inverter and the output of the delayer; N second NAND gates that respectively input the inverted N redundancy cell enable signals and inversely AND the input of the output of the first NOR gate; N second inverters for inputting and inverting outputs of the N second NAND gates, respectively; And N third inverters which respectively input and invert the outputs of the N second inverters.