KR20000045669A - Contact structure of semiconductor device - Google Patents

Contact structure of semiconductor device Download PDF

Info

Publication number
KR20000045669A
KR20000045669A KR1019980062237A KR19980062237A KR20000045669A KR 20000045669 A KR20000045669 A KR 20000045669A KR 1019980062237 A KR1019980062237 A KR 1019980062237A KR 19980062237 A KR19980062237 A KR 19980062237A KR 20000045669 A KR20000045669 A KR 20000045669A
Authority
KR
South Korea
Prior art keywords
insulating layer
contact
layer
interlayer insulating
patterned
Prior art date
Application number
KR1019980062237A
Other languages
Korean (ko)
Inventor
양해완
Original Assignee
김영환
현대반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체 주식회사 filed Critical 김영환
Priority to KR1019980062237A priority Critical patent/KR20000045669A/en
Publication of KR20000045669A publication Critical patent/KR20000045669A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A contact structure of a semiconductor device is to prevent the reliability of a semiconductor device to be lowered due to the misalignment of a contact for electrically connecting lower interconnection and upper interconnection. CONSTITUTION: A contact structure of a semiconductor device comprises: a first insulating layer formed on a semiconductor substrate; an etch stopper(13) which is patterned wider than the contact area on the first insulating layer and for stopping the first insulating layer from being etched upon etching a first interlayer insulating layer formed on the first insulating layer; a second insulating layer formed on the first insulating layer and the etch stopper, for preventing the etch stopper from being short; a first and second lower interconnection(15A,15B) which is patterned apart on the second insulating layer; a second interlayer insulating layer(16) formed on the first and second lower interconnection and the second insulating layer; a contact(17) formed in a part of the second interlayer insulating layer and the first lower interconnection or the etch stopper; and an upper interconnection(18) which is patterned on the second interlayer insulating layer and in contact with the contact.

Description

반도체소자의 콘택 구조Contact structure of semiconductor device

본 발명은 반도체소자의 콘택 구조에 관한 것으로, 특히 하부배선과 상부배선을 접속시키는 콘택의 오정렬(misalign)로 인한 반도체소자의 신뢰성 저하를 효과적으로 방지하여 고집적화를 구현하기에 적당하도록 한 반도체소자의 콘택 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact structure of a semiconductor device. In particular, a contact of a semiconductor device suitable for implementing high integration by effectively preventing a decrease in reliability of the semiconductor device due to misalignment of a contact connecting the lower wiring and the upper wiring. It's about structure.

종래 반도체소자의 콘택 구조를 도면을 참조하여 상세히 설명하면 다음과 같다.A contact structure of a conventional semiconductor device will be described in detail with reference to the accompanying drawings.

도1a는 종래 반도체소자의 콘택 구조를 보인 평면도이고, 도1b는 도1a의 X-X선 단면도로서, 이에 도시한 바와같이 반도체기판(1)의 상부에 형성된 절연막(2)과; 상기 절연막(2)의 상부에 패터닝된 하부배선(3A,3B)과; 상기 하부배선(3A,3B) 및 노출된 절연막(2)의 상부에 형성된 층간절연막(4)과; 상기 층간절연막(4)의 상부에 패터닝된 상부배선(5)과; 상기 상부배선(5)과 하부배선(3A)을 접속시키는 콘택(6)으로 이루어진다.FIG. 1A is a plan view showing a contact structure of a conventional semiconductor device, and FIG. 1B is a cross-sectional view taken along line X-X of FIG. 1A, as shown therein; Lower wirings 3A and 3B patterned on the insulating film 2; An interlayer insulating film 4 formed on the lower wirings 3A and 3B and the exposed insulating film 2; An upper wiring 5 patterned on the interlayer insulating film 4; It consists of a contact 6 which connects the upper wiring 5 and the lower wiring 3A.

도면에서 나타난 바와같이 하부배선(3A)의 콘택(6)과 접촉되는 영역을 넓게 형성하는 이유는 콘택(6)과 하부배선(3A)의 중첩영역을 여유있게 확보하기 위해서이다.As shown in the figure, the reason for forming a wide area in contact with the contact 6 of the lower wiring 3A is to ensure a sufficient overlapping area between the contact 6 and the lower wiring 3A.

즉, 하부배선(3A)이 충분히 넓게 형성되지 않으면, 도2의 단면도에 도시한 바와같이 콘택(6)과 하부배선(3A)의 중첩영역이 오정렬되어 층간절연막(4)을 식각하여 콘택홀을 형성할 때, 절연막(2)의 일부가 식각되어 반도체기판(1)이 노출되며, 이와같은 상태에서 콘택홀에 도전성물질을 채워 콘택(6)을 형성하면 상부배선(5), 하부배선(3A) 및 반도체기판(1)의 단락이 발생한다.That is, if the lower wiring 3A is not wide enough, as shown in the cross-sectional view of FIG. 2, the overlapping region of the contact 6 and the lower wiring 3A is misaligned, and the interlayer insulating film 4 is etched to etch the contact hole. When forming, part of the insulating film 2 is etched to expose the semiconductor substrate 1, and in this state, when the contact 6 is formed by filling a conductive material in the contact hole, the upper wiring 5 and the lower wiring 3A. ) And the semiconductor substrate 1 occur.

상술한 바와같이 종래 반도체소자의 콘택 구조는 콘택의 오정렬로 인해 상부배선, 하부배선 및 반도체기판이 단락되는 것을 방지하기 위하여 하부배선의 콘택과 접촉되는 영역을 넓게 형성함에 따라 하부배선의 레이아웃(layout) 면적이 증가하여 고집적회로의 설계에 적절치 못한 문제점이 있었다.As described above, the contact structure of the conventional semiconductor device has a layout of the lower wiring by forming a wide area in contact with the contact of the lower wiring to prevent the upper wiring, the lower wiring and the semiconductor substrate from being shorted due to the misalignment of the contacts. ) As the area is increased, there is a problem that is not suitable for the design of the high integrated circuit.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 콘택의 오정렬로 인한 상부배선, 하부배선 및 반도체기판의 단락을 효과적으로 방지하여 고집적화를 구현할 수 있는 반도체소자의 콘택 구조를 제공하는데 있다.The present invention has been made to solve the conventional problems as described above, an object of the present invention is to provide a highly integrated semiconductor device that can effectively prevent the short circuit of the upper wiring, the lower wiring and the semiconductor substrate due to the misalignment of the contact To provide a contact structure.

도1a은 종래 반도체소자의 콘택 구조를 보인 평면도.1A is a plan view showing a contact structure of a conventional semiconductor device.

도1b는 도1a의 X-X선 단면도.FIG. 1B is a cross-sectional view taken along the line X-X of FIG. 1A. FIG.

도2는 도1b에 있어서, 오정렬된 콘택 구조를 보인 단면도.FIG. 2 is a sectional view of FIG. 1B showing a misaligned contact structure. FIG.

도3a는 본 발명의 일 실시예에 따른 평면도.Figure 3a is a plan view according to an embodiment of the present invention.

도3b는 도3a의 Y-Y선 단면도.3B is a cross-sectional view taken along the line Y-Y in FIG. 3A.

도4는 도3b에 있어서, 오정렬된 콘택 구조를 보인 단면도.FIG. 4 is a cross-sectional view showing the misaligned contact structure in FIG. 3B; FIG.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

11:반도체기판 12,14:절연막11: semiconductor substrate 12, 14: insulating film

13:식각차단막 15A,15B:하부배선13: Etch barrier 15A, 15B: Lower wiring

16:층간절연막 17:콘택16: Interlayer insulating film 17: Contact

18:상부배선18: upper wiring

상기한 바와같은 본 발명의 목적을 달성하기 위한 콘택 구조의 바람직한 일 실시예는 반도체기판의 상부에 형성된 제1절연막과; 상기 제1절연막의 상부에 콘택이 형성될 면적보다 넓게 패터닝되어 후속 콘택형성을 위해 층간절연막을 식각할 때, 하부의 제1절연막이 식각되는 것을 차단하는 식각차단막과; 상기 제1절연막 및 식각차단막의 상부에 형성되어 식각차단막과 상부에 형성되는 제2하부배선의 단락을 방지하는 제2절연막과; 상기 제2절연막의 상부에 서로 이격되어 패터닝된 제1,제2하부배선과; 상기 제1,제2하부배선 및 제2절연막의 상부에 형성된 층간절연막과; 상기 층간절연막의 일부에 형성되어 제1하부배선 또는 제1하부배선 및 식각차단막과 접속되는 콘택과; 상기 층간절연막의 상부에 패터닝되어 콘택과 접촉되는 상부배선을 구비하여 구성되는 것을 특징으로 한다.A preferred embodiment of the contact structure for achieving the object of the present invention as described above comprises a first insulating film formed on the semiconductor substrate; An etch barrier layer which is patterned wider than an area where a contact is to be formed on the first insulating layer to block etching of the lower first insulating layer when the interlayer insulating layer is etched for subsequent contact formation; A second insulating layer formed on the first insulating layer and the etch blocking layer to prevent a short circuit between the etch blocking layer and the second lower wiring formed thereon; First and second lower interconnections spaced apart from each other and patterned on the second insulating layer; An interlayer insulating layer formed on the first and second lower interconnections and the second insulating layer; A contact formed on a portion of the interlayer insulating film and connected to a first lower wiring or a first lower wiring and an etch barrier film; And an upper wiring patterned on the interlayer insulating layer and in contact with the contact.

상기한 바와같은 본 발명에 의한 반도체소자 콘택 구조의 바람직한 일 실시예를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the semiconductor device contact structure according to the present invention as described above will be described in detail with reference to the accompanying drawings.

도3a는 본 발명의 일 실시예에 따른 반도체소자의 콘택을 보인 평면도이고, 도3b는 도3a의 Y-Y선 단면도로서, 이에 도시한 바와같이 반도체기판(11)의 상부에 형성된 절연막(12)과; 상기 절연막(12)의 상부에 콘택(17)이 형성될 면적보다 넓게 패터닝되어 후속 콘택(17)형성을 위해 층간절연막(16)을 식각할 때, 하부의 절연막(12)이 식각되는 것을 차단하는 식각차단막(13)과; 상기 절연막(12) 및 식각차단막(13)의 상부에 형성되어 식각차단막(13)과 상부에 형성되는 하부배선(15B)의 단락을 방지하는 절연막(14)과; 상기 절연막(14)의 상부에 서로 이격되어 패터닝된 하부배선(15A,15B)과; 상기 하부배선(15A,15B) 및 절연막(14)의 상부에 형성된 층간절연막(16)과; 상기 층간절연막(16)의 일부에 형성되어 하부배선(15A) 또는 하부배선(15A) 및 식각차단막(13)과 접속되는 콘택(17)과; 상기 층간절연막(16)의 상부에 패터닝되어 콘택(17)과 접촉되는 상부배선(18)으로 구성된다.3A is a plan view showing a contact of a semiconductor device according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line YY of FIG. 3A. As shown therein, an insulating film 12 formed on an upper portion of the semiconductor substrate 11 is formed. ; When the interlayer insulating layer 16 is etched to form the contact 17 on the upper portion of the insulating layer 12 to form a subsequent contact 17, the lower insulating layer 12 is blocked. An etch barrier film 13; An insulating film 14 formed on the insulating film 12 and the etch blocking film 13 to prevent a short circuit between the etch blocking film 13 and the lower wiring 15B formed thereon; Lower interconnections 15A and 15B spaced apart from each other and patterned on the insulating layer 14; An interlayer insulating film 16 formed on the lower wirings 15A and 15B and the insulating film 14; A contact 17 formed on a portion of the interlayer insulating film 16 and connected to the lower wiring 15A or the lower wiring 15A and the etch barrier film 13; The upper wiring 18 is patterned on the interlayer insulating layer 16 to be in contact with the contact 17.

도면에서 나타난 바와같이 본 발명에서는 하부배선(15A)의 하부에 콘택(17)이 형성될 면적보다 넓게 식각차단막(13)을 패터닝하여 하부배선(15A)의 콘택(17)과 접촉되는 영역을 최소화할 수 있게 되며, 식각차단막(13)의 상부에 절연막(14)을 형성하여 식각차단막(13)과 하부배선(15B)의 단락을 방지한다.As shown in the figure, in the present invention, the etch barrier layer 13 is patterned wider than the area where the contact 17 is to be formed under the lower wiring 15A, thereby minimizing the area in contact with the contact 17 of the lower wiring 15A. The insulating film 14 may be formed on the etch stop layer 13 to prevent a short circuit between the etch stop layer 13 and the lower wiring 15B.

이와같이 하부배선(15A)이 충분히 넓게 형성되지 않아 도4의 단면도에 도시한 바와같이 콘택(17)과 하부배선(15A)의 중첩영역에 오정렬이 발생되면, 층간절연막(16)을 식각하여 콘택홀을 형성할 때, 절연막(14)의 일부가 식각되지만 식각차단막(13)이 하부의 절연막(12) 및 반도체기판(11)의 식각을 차단하여 하부배선(15A)과 반도체기판(11)의 단락을 방지할 수 있게 되며, 아울러 절연막(14)을 통해 식각차단막(13)과 하부배선(15B)의 단락을 방지한다.If the lower interconnection 15A is not formed wide enough to cause misalignment in the overlapping region of the contact 17 and the lower interconnection 15A as shown in the cross-sectional view of FIG. 4, the interlayer insulating layer 16 is etched to etch the contact hole. When forming a portion of the insulating film 14, a portion of the insulating film 14 is etched, but the etch blocking film 13 blocks the etching of the lower insulating film 12 and the semiconductor substrate 11 to short-circuit the lower wiring 15A and the semiconductor substrate 11. It is possible to prevent, and also prevent the short circuit between the etch blocking film 13 and the lower wiring 15B through the insulating film (14).

한편, 상기 식각차단막(13)은 층간절연막(16) 및 절연막(14)과의 식각선택비가 우수한 재료를 선택하여 형성하여야 하며, 상기 층간절연막(16) 및 절연막(14)이 산화막으로 형성되는 경우에 일예로 폴리실리콘을 증착하여 패터닝하는 것이 바람직하다.Meanwhile, the etch barrier layer 13 should be formed by selecting a material having an excellent etching selectivity with respect to the interlayer insulating layer 16 and the insulating layer 14, and wherein the interlayer insulating layer 16 and the insulating layer 14 are formed of an oxide layer. For example, it is preferable to deposit and pattern polysilicon.

또한, 상기 하부배선(15A,15B)과 상부배선(18)이 알루미늄층으로 형성되는 경우에는 고온공정을 통해 형성되는 폴리실리콘은 적합하지 않으며, 저온공정을 통해 형성되는 물질로 텅스텐을 증착하여 패터닝하는 것이 바람직하다.In addition, when the lower interconnections 15A and 15B and the upper interconnection 18 are formed of an aluminum layer, polysilicon formed through a high temperature process is not suitable and is patterned by depositing tungsten with a material formed through a low temperature process. It is desirable to.

상기한 바와같은 본 발명에 의한 반도체소자의 콘택 구조는 콘택의 오정렬로 인한 상부배선, 하부배선 및 반도체기판의 단락을 식각차단막을 통해 방지하여 콘택과 하부배선이 중첩되는 영역을 최소화할 수 있게 되므로, 하부배선의 레이아웃 면적을 최소화하여 소자의 고집적화를 이룰수 있는 효과가 있다.The contact structure of the semiconductor device according to the present invention as described above can prevent the short circuit of the upper wiring, the lower wiring and the semiconductor substrate due to the misalignment of the contact through the etch barrier layer to minimize the area where the contact and the lower wiring overlaps In addition, it is possible to achieve high integration of the device by minimizing the layout area of the lower wiring.

Claims (4)

반도체기판의 상부에 형성된 제1절연막과; 상기 제1절연막의 상부에 콘택이 형성될 면적보다 넓게 패터닝되어 후속 콘택형성을 위해 층간절연막을 식각할 때, 하부의 제1절연막이 식각되는 것을 차단하는 식각차단막과; 상기 제1절연막 및 식각차단막의 상부에 형성되어 식각차단막과 상부에 형성되는 제2하부배선의 단락을 방지하는 제2절연막과; 상기 제2절연막의 상부에 서로 이격되어 패터닝된 제1,제2하부배선과; 상기 제1,제2하부배선 및 제2절연막의 상부에 형성된 층간절연막과; 상기 층간절연막의 일부에 형성되어 제1하부배선 또는 제1하부배선 및 식각차단막과 접속되는 콘택과; 상기 층간절연막의 상부에 패터닝되어 콘택과 접촉되는 상부배선을 구비하여 구성되는 것을 특징으로 하는 반도체소자의 콘택 구조.A first insulating film formed on the semiconductor substrate; An etch barrier layer which is patterned wider than an area where a contact is to be formed on the first insulating layer to block etching of the lower first insulating layer when the interlayer insulating layer is etched for subsequent contact formation; A second insulating layer formed on the first insulating layer and the etch blocking layer to prevent a short circuit between the etch blocking layer and the second lower wiring formed thereon; First and second lower interconnections spaced apart from each other and patterned on the second insulating layer; An interlayer insulating layer formed on the first and second lower interconnections and the second insulating layer; A contact formed on a portion of the interlayer insulating film and connected to a first lower wiring or a first lower wiring and an etch barrier film; And an upper wiring patterned on the interlayer insulating layer and in contact with the contact. 제 1항에 있어서, 상기 식각차단막은 제2절연막 및 층간절연막과 식각선택비가 우수한 재료로 형성된 것을 특징으로 하는 반도체소자의 콘택 구조.The contact structure of claim 1, wherein the etch stop layer is formed of a material having excellent etching selectivity with the second insulating layer and the interlayer insulating layer. 제 1항 또는 제 2항에 있어서, 상기 식각차단막은 폴리실리콘으로 형성된 것을 특징으로 하는 반도체소자의 콘택 구조.The contact structure of claim 1 or 2, wherein the etch stop layer is formed of polysilicon. 제 1항 또는 제 2항에 있어서, 상기 식각차단막은 텅스텐으로 형성된 것을 특징으로 하는 반도체소자의 콘택 구조.The contact structure of claim 1 or 2, wherein the etch stop layer is formed of tungsten.
KR1019980062237A 1998-12-30 1998-12-30 Contact structure of semiconductor device KR20000045669A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980062237A KR20000045669A (en) 1998-12-30 1998-12-30 Contact structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980062237A KR20000045669A (en) 1998-12-30 1998-12-30 Contact structure of semiconductor device

Publications (1)

Publication Number Publication Date
KR20000045669A true KR20000045669A (en) 2000-07-25

Family

ID=19568923

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980062237A KR20000045669A (en) 1998-12-30 1998-12-30 Contact structure of semiconductor device

Country Status (1)

Country Link
KR (1) KR20000045669A (en)

Similar Documents

Publication Publication Date Title
US4656732A (en) Integrated circuit fabrication process
US5243220A (en) Semiconductor device having miniaturized contact electrode and wiring structure
US4670091A (en) Process for forming vias on integrated circuits
US5798568A (en) Semiconductor component with multi-level interconnect system and method of manufacture
US4436582A (en) Multilevel metallization process for integrated circuits
US7205637B2 (en) Semiconductor device with a multilevel interconnection connected to a guard ring and alignment mark
US6251790B1 (en) Method for fabricating contacts in a semiconductor device
KR100215847B1 (en) Metal interconnector of semiconductor device and process for forming the same
KR0169713B1 (en) Method for producing self-aligned contacts between vertically separated wiring layers on an integrated circuit
US5924006A (en) Trench surrounded metal pattern
KR20000045669A (en) Contact structure of semiconductor device
US6445071B1 (en) Semiconductor device having an improved multi-layer interconnection structure and manufacturing method thereof
US6472697B2 (en) Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
US5425982A (en) Multi-layer wiring structure for semiconductor device and method of making the same
JP3517523B2 (en) Semiconductor device and manufacturing method thereof
KR100340858B1 (en) Method for fabricating metal interconnection of semiconductor device
KR20010070150A (en) Semiconductor device and method of manufacturing the same
KR100679941B1 (en) Method for fabricating contacts of semiconductor device
KR100252914B1 (en) Structure of semiconductor device and method for fabricating the same
KR100398584B1 (en) Method for manufacturing semiconductor device
KR100300075B1 (en) Wire structure of semiconductor device
KR0172725B1 (en) Multi-layer metal wire forming method of semiconductor device
KR100340857B1 (en) Method for fabricating multi metal interconnection of semiconductor device
KR100447982B1 (en) Method for forming metal interconnection of semiconductor device using buffer layer
KR20030015703A (en) Structure Of Dielectric Layer In Multilevel Interconnection And Method Of Forming The Same

Legal Events

Date Code Title Description
N231 Notification of change of applicant
WITN Withdrawal due to no request for examination