KR20000045286A - Semiconductor ic of soi structure and fabrication method of the same - Google Patents
Semiconductor ic of soi structure and fabrication method of the same Download PDFInfo
- Publication number
- KR20000045286A KR20000045286A KR1019980061844A KR19980061844A KR20000045286A KR 20000045286 A KR20000045286 A KR 20000045286A KR 1019980061844 A KR1019980061844 A KR 1019980061844A KR 19980061844 A KR19980061844 A KR 19980061844A KR 20000045286 A KR20000045286 A KR 20000045286A
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- source
- well
- region
- electrode
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 239000010410 layer Substances 0.000 claims abstract description 71
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 239000012212 insulator Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 에스오아이(silicon on insulator, 이하 SOI)구조의 반도체 집적회로 및 그 제조방법에 관한 것으로, 보다 구체적으로는 반도체 소자에 발생되는 열을 용이하게 방출시킬 수 있는 SOI 구조의 반도체 집적회로 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor integrated circuit having a silicon on insulator (SOI) structure and a manufacturing method thereof, and more particularly to a semiconductor integrated circuit having an SOI structure capable of easily dissipating heat generated in a semiconductor device; It relates to a manufacturing method.
반도체 집적회로, 특히 CMOS-LSI는 고속화와 집적도의 향상이 지속적으로 요구되고 있다.Semiconductor integrated circuits, in particular CMOS-LSI, are constantly required to increase in speed and density.
현재까지의 성능 향상은 주로 스케일링(scaling)으로 달성할 수 있었다. 서브 마이크론까지는 일정의 전원 전압로 스케일링을 이룰수 있었기 때문에 동작 속도도 큰폭으로 향상시키는 것이 가능하였다. 그러나, 서브 마이크론 이하에서는 전원 전압도 저하되기 때문에, 단순 스케일링 만으로는 속도의 향상을 달성할 수 없다.So far, performance gains have been achieved primarily by scaling. Up to submicrons could be scaled to a constant power supply voltage, which significantly improved the operating speed. However, below the submicron, the power supply voltage is also lowered, so that the improvement in speed cannot be achieved by simple scaling alone.
이에따라, 이러한 문제점을 해결하기 위하여 새로운 기술의 개발이 계속되고 있으며, 그 중 하나로 절연체층 상에 반도체 소자를 형성하는 반도체층이 형성된 즉, SOI 구조가 제안되었다.Accordingly, in order to solve such a problem, development of a new technology is continued, and one of them has been proposed a SOI structure in which a semiconductor layer for forming a semiconductor device is formed on an insulator layer.
도 1은 종래 기술에 다른 SOI 구조의 반도체 집적 회로의 일예를 나타낸 단면도이다.1 is a cross-sectional view showing an example of a semiconductor integrated circuit having an SOI structure according to the prior art.
종래에는 도 1에 도시된 바와 같이, 실리콘 기판(1) 상에 매몰 산화막(2)과 반도체층(3)이 순차적으로 적층된다. 이 반도체층(3)의 소정 부분에는 필드 산화막(4)이 형성되어, 액티브 영역이 한정된다. 액티브 영역의 소정 부분에는 게이트 절연막(5) 및 게이트 전극(6)이 배치되고, 게이트 전극(6) 양측의 액티브 영역에는 고농도 불순물이 이온 주입되어, 소오스, 드레인 영역(7a,7b)이 형성된다. 그리고, 소오스 영역(7a) 또는 드레인 영역(7b)의 일측에는 반도체층(3)의 플로팅을 방지하기 위하여, 기판 콘택부(8)가 배치된다.In the related art, as shown in FIG. 1, the buried oxide film 2 and the semiconductor layer 3 are sequentially stacked on the silicon substrate 1. A field oxide film 4 is formed in a predetermined portion of the semiconductor layer 3 to define an active region. A gate insulating film 5 and a gate electrode 6 are disposed in a predetermined portion of the active region, and highly-concentrated impurities are ion-implanted in the active regions on both sides of the gate electrode 6 to form source and drain regions 7a and 7b. . In order to prevent the semiconductor layer 3 from floating on one side of the source region 7a or the drain region 7b, the substrate contact portion 8 is disposed.
반도체층(3) 상부에는 층간 절연막(9)이 형성되고, 소오스 영역(7a), 드레인 영역(7b) 및 기판 콘택부(8)이 오픈되도록 층간 절연막(9)의 소정 부분이 식각되어, 콘택홀이 형성된다.An interlayer insulating film 9 is formed on the semiconductor layer 3, and a predetermined portion of the interlayer insulating film 9 is etched to open the source region 7a, the drain region 7b, and the substrate contact portion 8. Holes are formed.
노출된 소오스 영역(7a), 드레인 영역(7b) 및 기판 콘택부(8)와 콘택되도록 콘택홀내에 베리어 금속막(10) 및 주 금속막(11)로 된 금속 배선이 형성된다.A metal wiring made of the barrier metal film 10 and the main metal film 11 is formed in the contact hole so as to be in contact with the exposed source region 7a, drain region 7b, and substrate contact portion 8.
이러한 SOI 구조의 모스펫은 확산층의 용량이 극도로 작게 할수 있고, 실리콘층의 두께를 100nm 이하로 하는 경우 온 전류를 증대시킬 수 있다는 장점이 있다.The MOSFET of the SOI structure has an advantage that the capacity of the diffusion layer can be extremely small, and the on-current can be increased when the thickness of the silicon layer is 100 nm or less.
그러나, SOI 구조의 반도체 집적회로는 다음의 문제점이 있다.However, the semiconductor integrated circuit of the SOI structure has the following problems.
집적회로에서는 특히, 트랜지스터 영역에는 열이 발생되고, 이 발열량은 상당하기 때문에 경우에 따라 수십 와트(watt)에 달하기도 한다. 그 때문에 집적회로 장치에서는 각각의 방열에 대한 대책이 행하여지지만, 여전히 집적회로의 온도는 수십도, 때에따라 수백도 근처까지 상승한다. 이러한 온도 상승은 집적회로의 동작에 악영향을 미친다. 즉, 캐리어의 이동도가 저하되기 때문에 트랜지스터의 온 전류가 저하되고, 금속 배선의 저항 성분이 증대하기 때문에 배선 지연이 증대된다. 이에따라, 모스펫의 문턱 전압이 저하되어, 오프 전류가 증대되기 때문에 소비 전력이 증대된다.In an integrated circuit, heat is generated, particularly in the transistor region, and the amount of heat generated is considerable, which sometimes amounts to several tens of watts. Therefore, in the integrated circuit device, countermeasures for the respective heat dissipation are taken, but the temperature of the integrated circuit still rises to tens of degrees and sometimes hundreds of degrees. This rise in temperature adversely affects the operation of the integrated circuit. That is, since the mobility of the carrier decreases, the on-state current of the transistor decreases, and the wiring delay increases because the resistance component of the metal wiring increases. As a result, the threshold voltage of the MOSFET is lowered, so that the off current is increased, so that power consumption is increased.
이때, 종래의 벌크 모스 트랜지스터는 트랜지스터에 열이 발생하는 경우 주로 반도체 기판을 통해서 칩 표면에 배치되어 있는 패키지로 배출하였다. 즉, 반도체 기판, 예를들어 실리콘 기판은 매우 열을 전달하는 속도가 빠르므로 패키지까지 빠른 속도로 열을 전달시키게 된다.In this case, the conventional bulk MOS transistor is discharged into the package disposed on the chip surface mainly through the semiconductor substrate when the transistor generates heat. That is, a semiconductor substrate, for example, a silicon substrate, transfers heat to a package at a high speed because the heat transfer rate is very fast.
하지만, 종래의 SOI 구조의 집적회로에서는 트랜지스터 영역과 반도체 기판 사이에는 수 마이크론대의 매몰 산화막이 존재한다. 매몰 산화막, 예를들어 실리콘 산화막은 열을 전달하기 어렵고, 발생한 열은 빠르게 패키지에 도달하는 것이 불가능하므로 기판 온도가 상승한다.However, in the integrated circuit of the conventional SOI structure, a buried oxide film of several microns exists between the transistor region and the semiconductor substrate. The buried oxide film, for example a silicon oxide film, is difficult to transfer heat, and the generated heat cannot reach the package quickly, so that the substrate temperature rises.
따라서, 본 발명의 목적은 상기한 종래의 문제점을 해결하기 위한 것으로, 트랜지스터에 발생된 열을 용이하게 방출시킬 수 있는 SOI 구조의 반도체 집적회로를 제공하는 것이다.Accordingly, an object of the present invention is to provide a semiconductor integrated circuit having an SOI structure capable of easily dissipating heat generated in a transistor.
또한, 본 발명의 다른 목적은 상기한 SOI 구조의 반도체 집적회로 제조방법을 제공하는 것이다.Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit having the SOI structure.
도 1은 일반적인 SOI 반도체 소자의 단면도.1 is a cross-sectional view of a typical SOI semiconductor device.
도 2a 내지 도 2f는 본 발명의 일실시예에 따른 SOI 구조의 반도체 집적 회로 및 그 제조방법.2A to 2F illustrate a semiconductor integrated circuit having a SOI structure and a method of manufacturing the same according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
20 - 반도체 기판 22 - 매몰 절연층20-semiconductor substrate 22-investment insulating layer
24 - 실리콘층 25 - 필드 산화막24-silicon layer 25-field oxide
26, 32, 33, 35 - 마스크 패턴 27a - 제 1 웰26, 32, 33, 35-mask pattern 27a-first well
27b - 제 2 웰 28 - 게이트 산화막27b-second well 28-gate oxide
29 - 게이트 전극 30a - 소오스 영역29-gate electrode 30a-source region
30b - 드레인 영역 31 - 기판 콘택부30b-drain region 31-substrate contact
32 - 층간 절연막 34 - 제 1 측벽 불순물 영역32-interlayer insulating film 34-first sidewall impurity region
36 - 제 2 측벽 불순물 영역 37 - 베리어 금속막36-second sidewall impurity region 37-barrier metal film
38 - 주 금속막 39a - 소오스 전극38-main metal film 39a-source electrode
39b - 드레인 전극 39c - 기판 전극39b-drain electrode 39c-substrate electrode
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 견지에 따르면, 반도체 기판, 매몰 절연층 실리콘층이 적층된 SOI 기판과, 상기 반도체 기판의 소정 부분에 형성된 제 1 웰과, 상기 제 1 웰 상부의 실리콘층에 형성되며 제 1 웰과 동일한 불순물 타입을 갖는 제 2 웰과, 상기 SOI 기판의 실리콘층 소정 부분에 형성되며 액티브 영역을 한정하는 필드 산화막과, 상기 실리콘층의 제 2 웰 상부의 소정 부분에 형성되는 게이트 전극과, 상기 게이트 전극 양측의 제 2 웰 영역에 형성되는 소오스 드레인 영역, 및 상기 소오스 또는 드레인 영역 일측의 제 2 웰 영역에 형성되는 기판 콘택부와, 상기 실리콘층 상부에 형성되는 층간 절연막과, 상기 층간 절연막내에 형성되고, 소오스 영역, 드레인 영역, 기판 콘택부의 소정 부분이 노출시키는 콘택홀, 및 상기 콘택홀내에 형성되어, 노출된 소오스 영역, 드레인 영역 및 기판 콘택부와 각각 콘택되는 소오스 전극, 드레인 전극 및 기판 전극을 포함하며, 상기 각각 콘택홀은 상기 층간 절연막, 실리콘층 및 매몰 절연층을 관통하여, 상기 반도체 기판의 제 1 웰 영역이 오픈되도록 형성되고, 상기 소오스 전극, 드레인 전극 및 기판 전극은 상기 노출된 소오스 영역, 드레인 영역 및 기판 콘택부와 콘택됨과 동시에 제 1 웰과 각각 콘택되는 것을 특징으로 한다.In order to achieve the above object of the present invention, according to one aspect of the present invention, a semiconductor substrate, an SOI substrate on which a buried insulating layer silicon layer is laminated, a first well formed in a predetermined portion of the semiconductor substrate, and the first A second well formed in the silicon layer above the well and having the same impurity type as the first well, a field oxide film formed in a predetermined portion of the silicon layer of the SOI substrate and defining an active region, and an upper part of the second well of the silicon layer A gate electrode formed in a predetermined portion of the substrate, a source drain region formed in the second well region on both sides of the gate electrode, a substrate contact portion formed in the second well region on one side of the source or drain region, and an upper portion of the silicon layer. An interlayer insulating film formed in the interlayer insulating film, a contact hole formed in the interlayer insulating film, and exposed by a predetermined portion of the source region, the drain region, the substrate contact portion, and the cone. A source electrode, a drain electrode, and a substrate electrode formed in the hole and contacting the exposed source region, the drain region, and the substrate contact portion, respectively, wherein each contact hole penetrates the interlayer insulating layer, the silicon layer, and the buried insulating layer. And the first well region of the semiconductor substrate is opened, and the source electrode, the drain electrode, and the substrate electrode are in contact with the exposed source region, the drain region, and the substrate contact portion, and the first well region is in contact with the first well, respectively. It is done.
또한, 본 발명의 다른 견지에 따르면, 반도체 기판, 매몰 절연층 및 실리콘층이 적층된 SOI 기판을 제공하는 단계와, 상기 실리콘층의 소정 부분에 필드 산화막을 형성하는 단계와, 상기 버퍼층의 소정 부분에 제 1 전도 타입의 불순물을 주입하여, 상기 반도체 기판과 실리콘층에 제 1 및 제 2 웰을 형성하는 단계와, 상기 제 2 웰의 소정 부분에 게이트 전극을 형성하는 단계와, 상기 게이트 전극 양측의 제 2 웰 영역에 제 2 전도 타입의 불순물을 이온 주입하여, 소오스, 드레인 영역을 형성하는 단계와, 상기 소오스 영역 또는 드레인 영역의 일측에 제 1 전도 타입의 불순물을 주입하여 기판 콘택부를 형성하는 단계와, 상기 실리콘층 상부에 층간 절연막을 형성하는 단계와, 상기 소오스 영역, 드레인 영역, 기판 콘택부를 노출시킴과 동시에 및 그 하부의 제 1 웰이 각각 노출되도록 층간 절연막, 실리콘층, 매몰 절연층을 식각하여 콘택홀을 형성하는 단계와, 상기 각각의 콘택홀 내벽 및 저면에 소정의 불순물을 주입하여 측벽 불순물 영역을 형성하는 단계, 및 상기 소오스 영역, 드레인 영역 및 기판 콘택부가 노출된 각각의 콘택홀 내에 소오스 전극, 드레인 전극 및 기판 전극을 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a SOI substrate in which a semiconductor substrate, a buried insulating layer, and a silicon layer are stacked, forming a field oxide film on a predetermined portion of the silicon layer, and a predetermined portion of the buffer layer. Implanting impurities of a first conductivity type into the semiconductor substrate and the silicon layer to form first and second wells, forming a gate electrode in a predetermined portion of the second well, and both sides of the gate electrode. Implanting an impurity of a second conductivity type into a second well region of the source to form a source and a drain region, and implanting an impurity of the first conductivity type into one side of the source or drain region to form a substrate contact portion Forming an interlayer insulating film over the silicon layer, exposing the source region, the drain region, and the substrate contact; Forming a contact hole by etching the interlayer insulating film, the silicon layer, and the buried insulating layer so as to expose each well, and implanting a predetermined impurity into the inner wall and the bottom of each contact hole to form a sidewall impurity region; and And forming a source electrode, a drain electrode, and a substrate electrode in each contact hole in which the source region, the drain region, and the substrate contact portion are exposed.
본 발명에 의하면, SOI 구조의 반도체 집적 회로에서, 소오스 전극, 드레인 전극 및 기판 전극을 매몰 절연층을 관통하여 웰이 형성된 반도체 기판과 콘택되도록 형성한다.According to the present invention, in a semiconductor integrated circuit having an SOI structure, a source electrode, a drain electrode, and a substrate electrode are formed so as to contact a well-formed semiconductor substrate through a buried insulating layer.
이에따라, 실리콘층에서 발생된 열은 열전달 특성이 우수한 웰이 형성된 반도체 기판쪽으로 흐르게 되어 용이하게 분산된다.Accordingly, the heat generated in the silicon layer flows toward the semiconductor substrate on which the wells having excellent heat transfer characteristics are formed and are easily dispersed.
따라서, 기판 온도 상승으로 인한 반도체 집적회로의 신뢰성 저하를 방지할 수 있다.Therefore, it is possible to prevent the degradation of the reliability of the semiconductor integrated circuit due to the rise of the substrate temperature.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2f는 본 발명의 일실시예에 따른 SOI 구조의 반도체 집적회로 제조방법을 설명하기 위한 각 공정별 단면도이다.2A through 2F are cross-sectional views of respective processes for describing a method for manufacturing a semiconductor integrated circuit having an SOI structure according to an embodiment of the present invention.
먼저, 도 2a를 참조하여, 반도체 기판(20), 매몰 절연층(22) 및 실리콘층(24)이 순차적으로 적층된 SOI 기판(100)이 제공된다. 이때, SOI 기판(100)은 공지된 본딩 방식, 또는 SIMOX(Separation by Implanted OXygen) 방식으로 형성될 수 있다. 이때, 매몰 절연층(22)은 실리콘 산화막 또는 실리콘 질화막일 수 있다. 그다음, 실리콘층(24)의 소정 부분에 공지의 로코스(LOCOS) 방법, 트랜치(trench) 방법등을 이용하여 필드 산화막(25)을 형성하여, 액티브 영역을 한정한다. 그후, 실리콘층(24) 상부에 포토레지스트막을 도포한다음, 선택적으로 노광 및 현상하여, 웰 형성용 제 1 마스크 패턴(26)을 형성한다. 그런다음, 노출된 SOI 기판에 웰 형성용 불순물 이온이 이온 주입된다. 이때, 웰 형성용 불순물은 P형 또는 N형일 수 있으며, 본 실시예에서는 P웰을 예를들어 설명한다. 또한, 웰 형성용 불순물은 매몰 절연층(22) 하부의 반도체 기판(20)까지 불순물이 도달할 수 있도록 높은 에너지로 주입된다. 이에따라, 반도체 기판(20) 및 실리콘층(24)에 웰(27a,27b)이 형성된다. 여기서, 반도체 기판(20)에 형성되는 웰을 제 1 웰(27a)이라 하고, 실리콘층(24)에 형성되는 웰을 제 2 웰(27b)이라 한다. 그후, 제 1 마스크 패턴(26)은 공지의 방식으로 제거된다.First, referring to FIG. 2A, an SOI substrate 100 in which a semiconductor substrate 20, a buried insulating layer 22, and a silicon layer 24 are sequentially stacked is provided. In this case, the SOI substrate 100 may be formed by a known bonding method or a Separation by Implanted Oxygen (SIMOX) method. In this case, the buried insulating layer 22 may be a silicon oxide film or a silicon nitride film. Next, the field oxide film 25 is formed in a predetermined portion of the silicon layer 24 using a known LOCOS method, a trench method, or the like to define the active region. Thereafter, a photoresist film is applied over the silicon layer 24, and then selectively exposed and developed to form a first mask pattern 26 for forming a well. Then, impurity ions for well formation are ion implanted into the exposed SOI substrate. In this case, the well-forming impurities may be P-type or N-type, and in this embodiment, P wells will be described. In addition, the impurities for well formation are injected with high energy so that the impurities can reach the semiconductor substrate 20 under the buried insulating layer 22. As a result, wells 27a and 27b are formed in the semiconductor substrate 20 and the silicon layer 24. Here, the well formed in the semiconductor substrate 20 is called the first well 27a, and the well formed in the silicon layer 24 is called the second well 27b. Thereafter, the first mask pattern 26 is removed in a known manner.
그리고나서, 도 2b에 도시된 바와 같이, 액티브 영역의 소정 부분에 게이트 절연막(28)과 게이트 전극(29)을 형성한다. 이어, 게이트 전극(29) 양측의 액티브 영역에 상기 웰(27a,27b)을 형성하는 이온과 반대 타입의 불순물 예를들어 N형 불순물을 이온 주입하여, 소오스, 드레인 영역(30a,30b)을 형성한다. 그리고나서, 소오스 또는 드레인 영역(30a,30b) 일측의 액티브 영역에 웰(27a,27b)과 동일한 불순물 예를들어, 고농도 P형의 불순물을 이온 주입하여, 기판 콘택부(31)를 형성한다. 여기서, 기판 콘택부(31)는 상기 제 2 웰(27b)이 플로팅되는 것을 방지하는 역할을 한다. 그후에, 실리콘층(24) 상부에 층간 절연막(32)을 증착한다음, 소오소, 드레인 영역(30a,30b) 및 기판 콘택부(31)가 노출되도록 층간 절연막(32)의 소정 부분을 식각하여, 제 1 콘택홀(h1)을 형성한다.Then, as shown in FIG. 2B, the gate insulating film 28 and the gate electrode 29 are formed in a predetermined portion of the active region. Subsequently, the source and drain regions 30a and 30b are formed by ion implanting impurities, for example, N-type impurities, opposite to the ions forming the wells 27a and 27b in the active regions on both sides of the gate electrode 29. do. Then, the same impurity as the wells 27a and 27b, for example, a high concentration of P-type impurities, is ion-implanted into the active region on one side of the source or drain regions 30a and 30b to form the substrate contact portion 31. Here, the substrate contact part 31 serves to prevent the second well 27b from floating. Thereafter, an interlayer insulating film 32 is deposited over the silicon layer 24, and then a predetermined portion of the interlayer insulating film 32 is etched to expose the source, drain regions 30a and 30b and the substrate contact portion 31. The first contact hole h1 is formed.
그 다음, 도 2c에 도시된 바와 같이, 상기 제 1 콘택홀(h1)이 형성된 층간 절연막(32)을 마스크로 하여, 반도체 기판(20)의 제 1 웰(27a)이 노출되도록 실리콘층(24), 매몰 절연층(22) 및 반도체 기판(20)의 소정 부분을 식각하여, 제 2 콘택홀(h2)을 형성한다. 이때, 제 2 콘택홀(h2)의 측벽 부분을 통하여, 소오스, 드레인 영역(30a,30b) 및 기판 콘택부(31)의 일부가 노출된다.Next, as shown in FIG. 2C, using the interlayer insulating film 32 having the first contact hole h1 as a mask, the silicon layer 24 is exposed to expose the first well 27a of the semiconductor substrate 20. ), A predetermined portion of the buried insulating layer 22 and the semiconductor substrate 20 is etched to form a second contact hole h2. At this time, a portion of the source, the drain regions 30a and 30b and the substrate contact portion 31 are exposed through the sidewall portion of the second contact hole h2.
그후, 도 2d에서와 같이, 층간 절연막(32) 상부에 상기 소오스, 드레인 영역(30a,30b)을 노출시키는 제 2 콘택홀(h2)들이 오픈되도록 제 2 마스크 패턴(33)을 형성한다. 이어서, 제 2 콘택홀(h2) 내벽 및 저면에 상기 소오스, 드레인 영역(30a,30b)을 구성하는 불순물과 동일한 타입의 불순물을 이온 주입하여, 제 2 콘택홀(h2) 내벽 및 저면에 제 1 측벽 불순물 영역(34)을 형성한다. 이때, 제 1 측벽 불순물 영역(34)을 형성하기 위한 불순물은 좌우 방향으로 1 내지 45도 틸트시켜서 주입함이 바람직하다.Thereafter, as shown in FIG. 2D, a second mask pattern 33 is formed on the interlayer insulating layer 32 so that the second contact holes h2 exposing the source and drain regions 30a and 30b are opened. Subsequently, an ion of an impurity of the same type as the impurities constituting the source and drain regions 30a and 30b is ion-implanted into the inner wall and the bottom of the second contact hole h2, and the first wall is formed on the inner wall and the bottom of the second contact hole h2. Sidewall impurity regions 34 are formed. At this time, it is preferable that the impurity for forming the first sidewall impurity region 34 is injected by tilting 1 to 45 degrees in the horizontal direction.
그 다음, 제 2 마스크 패턴(33)을 제거한다음, 도 2e에 도시된 바와 같이, 기판 콘택부(31)를 노출시키는 제 2 콘택홀(h2)이 오픈되도록 제 3 마스크 패턴(35)을 형성한다. 그후에 노출된 제 2 콘택홀(h2)의 내벽 및 저면에 상기 기판 콘택부(31)를 구성하는 불순물과 동일한 타입을 가진 불순물을 이온 주입하여, 제 2 측벽 불순물 영역(36)을 형성한다. 이때의 이온 주입 역시, 1 내지 45도 정도 틸트 시켜서 이온 주입함이 바람직하다.Next, after removing the second mask pattern 33, as shown in FIG. 2E, the third mask pattern 35 is formed to open the second contact hole h2 exposing the substrate contact part 31. do. Thereafter, impurities having the same type as the impurities constituting the substrate contact portion 31 are ion-implanted into the inner wall and the bottom of the exposed second contact hole h2 to form the second sidewall impurity region 36. The ion implantation at this time is also preferably tilted by 1 to 45 degrees and ion implanted.
그런다음, 도 2f에 도시된 바와 같이, 제 3 마스크 패턴(35)을 공지의 방법으로 제거한다. 이어, 상기 각각의 제 2 콘택홀(h)내에 측벽 불순물 영역(34,36)과 콘택되도록 베리어 금속막(37)과 주 금속막(38)을 형성한다음, 소정 부분 패터닝하여, 소오스 전극(39a), 드레인 전극(39b) 및 기판 전극(39c)을 형성한다.Then, as shown in FIG. 2F, the third mask pattern 35 is removed by a known method. Subsequently, a barrier metal film 37 and a main metal film 38 are formed in each of the second contact holes h so as to be in contact with the sidewall impurity regions 34 and 36, and then patterned by a predetermined portion to obtain a source electrode. 39a), the drain electrode 39b and the substrate electrode 39c are formed.
이러한 구성을 갖는 본 발명은 소오스 전극(39a), 드레인 전극(39b) 및 기판 전극(39c)이 모두 매몰 절연층(22)을 관통하여 반도체 기판(20)과 접속되어 있다. 이에따라, 집적회로가 형성되는 실리콘층(24)에 집적회로의 동작으로 열이 발생되어도, 실리콘 재질로 된 반도체 기판(20)으로 빠지게 되어, 열이 쉽게 분산된다.In the present invention having such a configuration, the source electrode 39a, the drain electrode 39b, and the substrate electrode 39c all pass through the buried insulating layer 22 and are connected to the semiconductor substrate 20. As a result, even when heat is generated in the silicon layer 24 on which the integrated circuit is formed, the heat is generated by the semiconductor substrate 20 made of silicon, and heat is easily dissipated.
더욱이, 전극들(39a,39b,39c)이 콘택되는 반도체 기판(20)에는 더욱 열 전달 특성이 우수하도록 웰이 형성되어 있으므로, 실리콘층에서 발생된 열이 더욱 효과적으로 방출된다.In addition, since the wells are formed in the semiconductor substrate 20 to which the electrodes 39a, 39b, and 39c are contacted, the heat transfer characteristics of the silicon layer 20 are more effectively discharged.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, SOI 구조의 반도체 집적 회로에서, 소오스 전극, 드레인 전극 및 기판 전극을 매몰 절연층을 관통하여 웰이 형성된 반도체 기판과 콘택되도록 형성한다.As described in detail above, according to the present invention, in a semiconductor integrated circuit having an SOI structure, the source electrode, the drain electrode, and the substrate electrode are formed to penetrate the buried insulating layer to be in contact with the semiconductor substrate on which the wells are formed.
이에따라, 실리콘층에서 발생된 열은 열전달 특성이 우수한 웰이 형성된 반도체 기판쪽으로 흐르게 되어 반도체 기판 바깥으로 용이하게 분산된다.Accordingly, the heat generated in the silicon layer flows toward the semiconductor substrate on which the wells having excellent heat transfer characteristics are formed and is easily dispersed outside the semiconductor substrate.
따라서, 기판 온도 상승으로 인한 반도체 집적회로의 신뢰성 저하를 방지할 수 있다.Therefore, it is possible to prevent the degradation of the reliability of the semiconductor integrated circuit due to the rise of the substrate temperature.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061844A KR100290789B1 (en) | 1998-12-30 | 1998-12-30 | SOI structure semiconductor integrated circuit and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061844A KR100290789B1 (en) | 1998-12-30 | 1998-12-30 | SOI structure semiconductor integrated circuit and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000045286A true KR20000045286A (en) | 2000-07-15 |
| KR100290789B1 KR100290789B1 (en) | 2001-07-12 |
Family
ID=19568541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980061844A KR100290789B1 (en) | 1998-12-30 | 1998-12-30 | SOI structure semiconductor integrated circuit and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100290789B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6759714B2 (en) | 2002-11-01 | 2004-07-06 | Electronics And Telecommunications Research Institute | Semiconductor device having heat release structure using SOI substrate and fabrication method thereof |
| CN110473880A (en) * | 2018-05-08 | 2019-11-19 | 三星电子株式会社 | Semiconductor devices and its manufacturing method |
-
1998
- 1998-12-30 KR KR1019980061844A patent/KR100290789B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6759714B2 (en) | 2002-11-01 | 2004-07-06 | Electronics And Telecommunications Research Institute | Semiconductor device having heat release structure using SOI substrate and fabrication method thereof |
| CN110473880A (en) * | 2018-05-08 | 2019-11-19 | 三星电子株式会社 | Semiconductor devices and its manufacturing method |
| CN110473880B (en) * | 2018-05-08 | 2024-05-17 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100290789B1 (en) | 2001-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6762477B2 (en) | Semiconductor device | |
| US7439112B2 (en) | Semiconductor device using partial SOI substrate and manufacturing method thereof | |
| JP3647676B2 (en) | Semiconductor device | |
| US6930361B2 (en) | Semiconductor device realizing characteristics like a SOI MOSFET | |
| US6531356B1 (en) | Semiconductor devices and methods of manufacturing the same | |
| KR19980020943A (en) | Insulation tunneling transistor and manufacturing method thereof | |
| US20030155615A1 (en) | Structure of a semiconductor integrated circuit and method of manufacturing the same | |
| KR100290789B1 (en) | SOI structure semiconductor integrated circuit and manufacturing method thereof | |
| US5933736A (en) | Method of manufacturing a semiconductor device | |
| US5159417A (en) | Semiconductor device having short channel field effect transistor with extended gate electrode structure and manufacturing method thereof | |
| US6597038B1 (en) | MOS transistor with double drain structure for suppressing short channel effect | |
| US5122855A (en) | Semiconductor device with latch-up prevention structure | |
| KR100307828B1 (en) | Manufacturing method of semiconductor device | |
| KR100505400B1 (en) | Semiconductor device formed SOI substrate and method for manufacturing the same | |
| KR100291517B1 (en) | SIO structure semiconductor integrated circuit and its manufacturing method | |
| KR100332473B1 (en) | Semiconductor device and device isolation method using it | |
| KR100201779B1 (en) | Semiconductor device and method of manufacturing the same | |
| JPS60154671A (en) | Semiconductor device | |
| KR100548536B1 (en) | Semiconductor device formed SOI substrate and method for manufacturing the same | |
| KR100239421B1 (en) | Method for manufacturing semiconductor device | |
| KR0151198B1 (en) | Semiconductor device | |
| KR20000006396A (en) | Semiconductor device and method of manufacturing the same | |
| KR100533395B1 (en) | Method For Forming The Vertical Transitor | |
| KR100257709B1 (en) | Method for manufacturing transistor soi device | |
| US6057201A (en) | Method of producing a transistor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110222 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |