KR20000042438A - Bit line equalizer of semiconductor memory device - Google Patents

Abstract

PURPOSE: A bit line equalizer in a semiconductor memory device is provided to improve the equalizing operation of a bit line by rapidly equalizing the bit line before turning on a word line. CONSTITUTION: An equalizing control signal(EQR) is generated by increasing and inverting the pulse width of an equalizing signal(/EQ). Herein, the inversion is operated to consider the logic of equalizing circuits as PMOS(P-channel Metal Oxide Semiconductor) transistors. Therefore, the bit line is equalized by the equalizing control signal before the word line is turned on. Moreover, the bit line is equalized regardless of the on time of word line. The bit line is equalized in the low state of the equalizing control signal to maximize the action of a high-speed memory.

Description

Bit line equalizer of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an equalization circuit, and more particularly to a method and apparatus for equalizing a bit line at high speed.

Semiconductor memory devices are getting faster. In particular, the static RAM is a memory device that operates with low power and high speed memory, and the process of equalizing bit lines becomes an important operation process for a new access operation. This equalization process is intended to speed up the development of a pair of bit lines or data lines.

The equalization pulse generated through the equalization circuit by the output of the address transition detector (ATD) before the word line selected by the address is turned on in the semiconductor memory device as described above. It is generally well known to improve bit line development by equalizing the bit lines by pulses. In a high speed memory device, it is preferable that the equalization pulses should be equalized before the selected word line is turned on.

Fig. 1 shows a bit line equalization timing diagram in a high speed memory. As shown in FIG. 1, since the bit line equalization process is generally (T1 + ΔT) later than the word line on-time T2 of FIG. 1, the bit line is equalized by the equalization pulse even when the word line is on. The bit line equalization operation cannot be improved.

This is because in the high-speed memory device, since its access time is less than 10 ns (nano second), it is difficult to generate a bit line equalization pulse suitable for the word line on time. For example, referring to FIG. 1, assuming that the word line on time T2 is about 4 ns, if the equalization pulse on time T1 is about 3 ns, the time ΔT required for bit line equalization is generally about 3 ns (T1 + ΔT) is about 6 ns. Therefore, since T2 is 2 ns faster than (T1 + ΔT), it is difficult to equalize the bit line before the word line on, which indicates a problem in that the performance of the overall memory device cannot be improved.

Accordingly, an object of the present invention is to provide a semiconductor memory device having an equalization control circuit having improved operation characteristics by improving bit line equalization operation, and a control method thereof.

Another object of the present invention is to provide a semiconductor memory device having an equalization control circuit for equalizing a bit line at high speed before word line on in a high speed memory device, and a control method thereof.

1 is a bit line equalization timing diagram according to the prior art;

2 is a bit line equalization timing diagram according to the present invention;

3 is a configuration diagram of an equalization control circuit according to the present invention;

4 is a block diagram of a circuit to which bit line equalization control logic according to FIGS. 2 and 3 is applied.

According to an aspect of the present invention, there is provided a semiconductor memory device, comprising: equalization signal generation means for outputting an equalization signal in response to an address input, an equalization signal, and an equalization control signal in response to a transition of the equalization signal; And a bit line equalization circuit for equalizing the bit line in response to the input of the equalization control signal.

In the above configuration, the equalization control signal generating means includes a delay unit for delayed transmission of the equalization signal, and a pulse generation unit for outputting an equalization control signal by combining the equalization signal and the output signal of the delay unit.

In addition, the equalization control method of the semiconductor memory device according to the present invention for achieving the above object, the first process of inputting the address, the second process of outputting the equalization signal in response to the address input, the input of the equalization signal And a fourth process of outputting an equalization control signal responsive to and a fourth process of equalizing the bit line before the word line is turned on in response to the input of the equalization control signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do. In the drawings, the same reference numerals are used for the same components as in the prior art.

2 shows a bit line equalization timing diagram according to the present invention. 2 is a process for realizing a bit line equalization control method according to the present invention, including inputting an address ADDRESS, outputting an equalization signal / EQ pulse in response to the address ADDRESS input, and performing the equalization. Outputting the equalization control signal EQR responsive to the input of the signal / EQ pulse; and equalizing the bit line / bit line before the word line word line on in response to the input of the equalization control signal EQR. Is done. More specifically, since the bit line cannot be equalized just before the word line is turned on by the equalization signal / EQ generated by the address ADDRESS, the equalization control signal EQR which is a feature of the present invention is generated. The equalization control signal EQR is a signal obtained by increasing the pulse width of the equalization signal / EQ by a predetermined time (T3-ΔT) and inverting it. The reason for the inversion here is that the logic of FIG. 4 to be described later is implemented by implementing a PMOS transistor. When the bit line is equalized by the equalization control signal EQR as described above, the bit line can be equalized for ΔT 'time until the word line is turned on after a predetermined time regardless of the on time T2 of the word line. That is, since the bit line is equalized when the equalization control signal EQR is "low", the bit line can be equalized regardless of the word line on time in the high speed memory, thereby maximizing the operation characteristics of the high speed memory. .

The semiconductor memory device according to the present invention includes an equalization signal generator for outputting an equalization signal in response to an address input, an equalization control signal generator for inputting the equalization signal and outputting an equalization control signal in response to a transition of the equalization signal; And a bit line equalization circuit unit for equalizing the bit line in response to the input of the equalization control signal. In this case, the equalization signal generator can perform a known circuit configuration as it is.

3 is a configuration diagram of an equalization control circuit according to the present invention. The circuit of FIG. 3 is a circuit for generating the equalization control signal EQR of FIG. A pulse generator (4) for combining the output signal of the unit (2) and outputting the equalization control signal EQR was implemented. In the above configuration, the delay unit 2 may be implemented to have a delay time of “(T3-ΔT) NS (where NS is nano second)” with reference to FIG. 2, and may be implemented as an inverter. In addition, the pulse generator 4 was implemented as a NAND gate. 3 is implemented such that the equalization control signal EQR inverted from the equalization signal / EQ is generated.

4 is a block diagram of a circuit to which bit line equalization control logic according to FIGS. 2 and 3 is applied. As shown, the equalization control signal EQR according to the present invention is input to the gates of the bit line equalization circuits P1, P2, and P3. The equalization operation of the bit line equalization circuits P1, P2, and P3 satisfies the timing of FIG.

Although the foregoing has been described with respect to embodiments of the present invention, those skilled in the art will understand that various implementations are possible within the scope of the technical idea of the present invention.

As described above, the present invention has the effect of improving the bit line equalization operation by improving the bit line equalization operation by equalizing the bit line at high speed before turning on the word line in the high speed memory device.

Claims (2)

In a semiconductor memory device, Equalization signal generation means for outputting an equalization signal in response to an address input; Equalization control signal generation means for inputting the equalization signal and outputting an equalization control signal in response to the transition of the equalization signal; And Bit line equalization circuit for equalizing the bit line in response to the input of the equalization control signal A semiconductor memory device comprising the. The method of claim 1, The equalization control signal generating means includes a delay unit for delaying the transmission of the equalization signal, and a pulse generator for inputting the equalization signal and the output signal of the delay unit in combination to output an equalization control signal. Device.