KR950003403B1 - Semiconductor device with level setting circuit - Google Patents

Abstract

The level-setting circuit for equalizing data line/bit line in the static RAM has the first sensing means receiving the control signal from the pulse generator where a channel is formed between the constant voltage generator and the transmission line; the second sensing means receiving the control signal from the said pulse generator where a channel is formed between the constant voltage generator and the sub data lines; the third sensing means receiving the control signal from the said pulse generator where a channel is formed between the constant voltage generator and the data lines. The transmission line is set at the constant voltage level when the transmission line is equalizing.

Description

Semiconductor memory device with level setting circuit

1 is a circuit diagram showing equalization of a conventional bit line or data line.

2 is a circuit diagram showing equalization according to the present invention.

3 is an embodiment of the 1/2 VCC generating circuit of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a level-setting circuit for equalizing a bit line or a data line for transferring predetermined data in a static RAM.

As semiconductor memory devices are increasingly highly integrated, the importance of high-speed operation of chips is increasing. For the high speed operation of the chip, it is already well known in the art that how fast the input / output operation of the data can be performed in the bit line or the data line for transmitting predetermined data. Thus, it has been proposed to precharge and equalize the bit line or data line to a predetermined voltage level before a data access operation. It is composed of a pair and equalizes bit lines and data lines having complementary logic operations with each other during a data access operation to a predetermined constant voltage level. One is a logic " high (H) " and the other is a logic " low (L) " which means an operating state each having a complementary voltage level.

In this regard, a circuit is shown in FIG. 1 that shows equalizing conventional bit lines and data lines. The configuration of FIG. 1 is a simplified illustration of equalizing a bit line or a data line. Those skilled in the art will readily understand that there are many configurations such as that of FIG. 1 in one chip. . SDL and in FIG. As is well known in the art, the sub data line is a data line DL according to the high integration of semiconductor memory devices. Bit line BL connected to ) Is too large and is an intermediate transmission line for connecting them in the middle. Meanwhile, in the configuration of FIG. 1, the sense amplifiers S / A-1 and S / A-2, the multiplexer MUX, and the pulse generating circuit 100 are well known in the art, and thus detailed circuits thereof are omitted. The configuration features of FIG. 1 include a bit line BL connected to an output terminal of the sense amplifier. ), Sub data lines (SDL, ), Dataline (DL, Equalization transistors (1.2, 11.12, 21.22) and the bit line (BL,) by using the output signal (Φ EQ) of the pulse generator (100 ') ), Sub data lines (SDL, ), Dataline (DL, ). Although not shown in FIG. 1, a sense amplifier is typically provided at the output terminal of the multiplexer MUX to amplify the output signal. The operating characteristics of FIG. 1 are as follows.

When the chip is not in an active cycle, the equalizing signal? EQ, which is an output signal of the pulse generating circuit 100 ', becomes a "high" level, and the bit line BL, ) And sub data lines (SDL, ) And data lines (DL, ) To the power supply voltage level. In the chip active cycle, the outputs of the sense amplifiers S / A-1 and S / A-2 are sufficiently developed during the sensing operation to perform data access operations. Finally, a Dout signal to the data output buffer (not shown) is generated. Afterwards, the equalizing signal Φ EQ is applied to the bit line BL, for the next access operation. ) And sub data lines (SDL, ) And data lines (DL, Equalize).

However, the following problem arises in the above manner. That is, when the sense amplifier is not operated, since the equalizing signal becomes the active "high" level, it takes a lot of time or needs to go through a read cycle to set it to the middle level. Therefore, the equalizing level takes a lot of time during the read operation in the write or the read operation in the standby (stand-by). On the other hand, in a circuit having a fairly small transistor size, such as an ultra-high density semiconductor memory device, it is susceptible to process conditions or external temperature. From this, as shown in FIG. The problem of termination occurs. In addition, when such a phenomenon occurs, it becomes difficult to secure the reliability of the semiconductor memory device, resulting in a bad phenomenon such as lowering the yield.

Accordingly, an object of the present invention is to provide a semiconductor memory device in which an equalization level of a signal transmission line such as a bit line or a data line is stabilized.

Another object of the present invention is to provide a semiconductor memory device in which a yield is improved by stabilizing an equalization level of a signal transmission line such as a bit line or a data line.

Still another object of the present invention is to provide a semiconductor memory device in which an equalization level of a signal transmission line such as a bit line or a data line is stabilized, and a signal is transmitted at a high speed during an active operation or a standby operation in a standby mode.

In order to achieve the object of the present invention, the present invention provides a predetermined pulse generating circuit, a transmission line configured as a pair and sensing predetermined data, a sense amplifier connected to the transmission line, and an output signal of the pulse generating circuit. A semiconductor memory device having an equalization circuit for inputting a control voltage and equalizing mutual voltage levels of a pair of transmission lines, the semiconductor memory device comprising: a predetermined constant voltage generation circuit and a channel between the constant voltage generation circuit and the transmission line; And a level-setting circuit formed of sensing means for controlling and inputting an output signal of the pulse generating circuit, and enabling the sensing means to set the transmission line to the constant voltage level when equalizing the transmission line. A semiconductor memory device. In the semiconductor memory device according to the present invention, equalization is performed after the transmission line is level-set to the constant voltage level. In addition, the sensing means of the level-setting circuit is characterized in that the pulse generation circuit is operated by the address transition detector (ATD) provided in the chip and is easily enabled therefrom. In addition, it is to be understood that the constant voltage generation circuit of the level-setting circuit can be easily implemented using the same thing as the 1/2 VCC generation circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. A circuit showing the equalization according to the present invention is shown in FIG. 2 shows equalizing a bit line or a data line with a level-setting circuit according to the invention as shown. And a half VCC generating circuit (as an embodiment of the constant voltage generating circuit) in FIG. 2 is shown.

The structural features of FIG. 2 according to the present invention are as follows. Although one level-setting circuit according to the present invention may be provided in a bit line or a data line, it is more preferable to provide each line for transmitting predetermined data as shown in FIG. . So the bitline (BL, ) And sub data lines (SDL, ) And data lines (DL, ), Respectively. In FIG. 2 according to the present invention, the same reference numerals and symbols as the conventional reference numerals and symbols indicate the same components. In the illustrated configuration, M1 and M2 represent bit lines BL, The first sensing means for applying 1/2 VCC to the), which is the bit line (BL, When equalizing), apply 1/2 VCC in advance and equalize to 1/2 VCC level. In the above, the first sensing means uses two transistors as shown, but one end of the bit line channel is a bit line BL, Only one transistor connected in common to the transistor can be used, and the EnMOS transistor can also be realized as a PMOS transistor. The second sensing means M3 and M4 and the third sensing means M5 and M6 also perform the same operations as the first sensing means M1 and M2, respectively. ) And data lines (DL, ) And equalize to 1/2 VCC level at the same time.

The operating characteristics of the semiconductor memory device including the level-setting circuit according to the present invention according to the above configuration are as follows. Prior to description, it should be noted that the gist of the present invention is to apply a predetermined constant voltage to the bit line or the data line and equalize to the constant voltage level. In FIG. 2, the operating characteristics of each of the sense amplifiers S / A-1 and S / A-2 and the multiplexer MUX, and the equalizing circuits 1.2, 11.12, and 21.22 are the same as those of the prior art. Done. When a predetermined address or data is input to the chip, the transition operation of the address or data is detected by an address transition detection circuit (ATD) provided in the chip, from which the pulse generating circuit 100 senses the active operation of the chip. And enable the first, second and third sensing means (M1.M2, M3.M4, M5.M6). Then the bit line (BL, ) And sub data lines (SDL, ) And data lines (DL, ) Are each half VCC voltage level, and when the equalizing circuits 1.2, 11.12, and 21.22 are enabled, they are equalized to each other at half VCC level. Then, when the chip is active, the bit lines BL, ) And sub data lines (SDL, ) And data lines (DL, Each developer's operation is a stable and high speed. The bit line BL, ) And sub data lines (SDL, ) And data lines (DL, ) Is applied with a 1/2 VCC voltage before the data access operation, and equalizes to the 1/2 VCC level, thereby preventing the level from shaking. This is, for example, when the write operation proceeds from the write operation to the read operation or in the standby operation in the read operation, the bit line BL, ) And sub data lines (SDL, ) And data lines (DL, ) Setting is stable and high speed (by high speed equalization to 1/2 VCC voltage level), allowing accurate development.

Meanwhile, the 1/2 VCC generation circuit 200 in FIG. 2 according to the present invention can be easily realized in the circuit shown in FIG. In FIG. 3, the 1/2 VCC voltage can be easily obtained by increasing the channel length of the transistors 32 and 33 than the channel lengths of the transistors 35 and 36. The 1/2 VCC generating circuit 200 can achieve the object of the present invention by using other circuits known in the art other than the circuit shown in FIG.

2 is an exemplary embodiment constructed in accordance with the spirit of the present invention, but this may be implemented differently as described in the foregoing description, and the 1/2 VCC generation circuit as the constant voltage generation circuit may be used. It should be noted that may be implemented in a circuit having a different constant voltage level as long as the effect of the present invention can be obtained.

As described above, the present invention has the advantage that the equalization level of the signal transmission line such as the bit line or the data line is stabilized, the transmission of the signal is performed at high speed during the active operation or during the standby operation in the standby mode, and the yield is improved. It works.

Claims (8)

A transmission configured by inputting a predetermined pulse generation circuit, a transmission line configured as a pair and sensing predetermined data, a sense amplifier connected to the transmission line, and an output signal of the pulse generation circuit as a control voltage. A semiconductor memory device having an equalization circuit for equalizing mutual voltage levels of lines, the semiconductor memory device comprising: a predetermined constant voltage generating circuit and a channel formed between the constant voltage generating circuit and the transmission line and controlling the output signal of the pulse generating circuit. And a level-setting circuit comprising a sensing means for enabling the sensing means to set the transmission line to the constant voltage level when equalizing the transmission line. The semiconductor memory device according to claim 1, wherein equalization is performed after the transmission line is level-set to the constant voltage level. 2. The semiconductor memory device according to claim 1, wherein said sensing means is enabled from operating said pulse generation circuit by an address transition detection circuit provided in a chip. The semiconductor memory device of claim 1, wherein the constant voltage generation circuit is a half VCC generation circuit. A predetermined pulse generating circuit, a first sense amplifier connected to a pair of bit lines, a second sense amplifier connected to a pair of sub data lines, and a third sense connected to a pair of data lines A semiconductor memory device having an amplifier and an equalization circuit for inputting an output signal of the pulse generating circuit as a control voltage and equalizing the mutual voltage levels of the paired bit line and sub data line and data line. A channel is formed between the constant voltage generator circuit, the constant voltage generator circuit and the bit line, and a first sensing means for controlling and inputting an output signal of the pulse generator circuit, and a channel is formed between the constant voltage generator circuit and the sub data line. Second sensing means for controlling inputting an output signal of the pulse generating circuit, and a channel is formed between the constant voltage generating circuit and the data line High levels characterized in that it comprises a third sensing means for controlling the input signal output from the pulse generating circuit, the circuit setting. 6. The level-setting circuit according to claim 5, wherein equalization is performed after the bit lines, sub data lines, and data lines are level-set to the constant voltage level. 7. The level-setting circuit according to claim 5 or 6, wherein the constant voltage generating circuit is a 1/2 VCC generating circuit. 6. The level-setting circuit as claimed in claim 5, wherein the first, second and third sensing means are enabled from the pulse generation circuit being operated by an address transition detection circuit provided in a chip.