KR20000039592A - Fabrication of substrate separation layer of semiconductor substrate - Google Patents
Fabrication of substrate separation layer of semiconductor substrate Download PDFInfo
- Publication number
- KR20000039592A KR20000039592A KR1019980054978A KR19980054978A KR20000039592A KR 20000039592 A KR20000039592 A KR 20000039592A KR 1019980054978 A KR1019980054978 A KR 1019980054978A KR 19980054978 A KR19980054978 A KR 19980054978A KR 20000039592 A KR20000039592 A KR 20000039592A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- layer
- trench
- insulating film
- etching
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 에스.티.아이(Shallow Trench Isolation) 공정에 관한 것으로, 특히 트랜치내에 소자분리막을 형성할 때 트랜치 상단의 필드영역과 소자영역 경계부분에서 발생되는 홈(Pit)을 제거하여 소자의 전기적 특성을 향상시키도록 한 반도체소자의 소자분리막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Shallow Trench Isolation process. In particular, when forming an isolation layer in a trench, an electrical device of the device is removed by removing a groove generated in a field region and an upper portion of the trench. The present invention relates to a device isolation film manufacturing method of a semiconductor device for improving the characteristics.
일반적으로, 반도체장치의 고집적화에 따라 반도체기판 상에 형성되는 개개의 소자 크기가 축소될 뿐만 아니라 개개의 소자를 전기적으로 분리시키는 소자분리영역의 크기도 점차 서브-마이크론(sub-micron)급까지 축소되고 있다. 이러한 고집적 반도체장치에서 반도체기판의 비활성영역에 세미-리세스(semi-recess)된 필드산화막을 형성하는 로코스(LOCOS) 방법을 사용할 경우 버즈빅(bird'beak)이 크게 발생하여 미세패턴에서의 소자분리가 어렵게 된다.In general, with the high integration of semiconductor devices, not only the size of individual devices formed on the semiconductor substrate is reduced but also the size of the device isolation region for electrically separating the individual devices is gradually reduced to sub-micron level. It is becoming. In the highly integrated semiconductor device, when the LOCOS method is used to form a semi-recessed field oxide film in an inactive region of a semiconductor substrate, bird'beak is largely generated, which causes a large pattern of fine patterns. Device separation becomes difficult.
이와같이 필드영역에서 발생할 수 있는 버즈빅의 문제점을 해결하기 위하여 에스.티.아이(Shallow Trench Isolation)공정이 개발 되었으며, 씨.엠.피(Chemical Mechanical Polishing) 공정이 도입됨에 따라 STI 공정은 보다 단순하게 되었다.In order to solve the problem of Buzzvik that can occur in the field area, the S.T.I.Shutter Trench Isolation process was developed, and the STI process is simpler as the chemical mechanical polishing process is introduced. Was done.
도 1 내지 도 3 은 종래 기술에 따른 반도체소자의 소자분리막 제조방법을 도시한 제조공정도로서 STI 기술을 적용한 예이다.1 to 3 is an example of applying the STI technology as a manufacturing process diagram showing a device isolation film manufacturing method of a semiconductor device according to the prior art.
도 1를 참조하면, 먼저 반도체 기판(10) 상에 버퍼용 패드산화막(12)과 질화막(14)을 순차적으로 증착한 다음, 질화막(14) 상에 트랜치 형성을 위한 개구부를 갖는 감광막(도시 안됨)의 패턴을 형성한다.Referring to FIG. 1, first, a buffer pad oxide film 12 and a nitride film 14 are sequentially deposited on a semiconductor substrate 10, and then a photoresist film having openings for trench formation on the nitride film 14 is illustrated. ) To form a pattern.
상기 감광막의 패턴을 식각마스크로 질화막(14)과 패드산화막(12)의 필드영역을 순차적으로 식각하여 질화막(14)의 패턴과 패드산화막(12)의 패턴을 형성하고 감광막의 패턴을 제거한 후, 이들의 패턴을 식각마스크로 이용하여 반도체 기판(10)을 소정 폭과 깊이로 식각한다. 따라서, 반도체 기판(10)의 필드영역에는 트랜치(16)가 형성된다.After etching the field regions of the nitride film 14 and the pad oxide film 12 sequentially using the pattern of the photoresist film, a pattern of the nitride film 14 and a pattern of the pad oxide film 12 are formed, and then the pattern of the photoresist film is removed. Using these patterns as an etching mask, the semiconductor substrate 10 is etched to a predetermined width and depth. Therefore, the trench 16 is formed in the field region of the semiconductor substrate 10.
도 2를 참조하면, 이후 트랜치(16)내에만 절연막(18)을 채운다. 이를 좀 더 상세히 언급하면, 트랜치(16)가 형성된 반도체기판(10)의 전면 상에 CVD산화막을 적층하고 이를 NH3분위기에서 플라즈마 처리한다.Referring to FIG. 2, the insulating film 18 is filled only in the trench 16. In more detail, the CVD oxide film is deposited on the entire surface of the semiconductor substrate 10 on which the trench 16 is formed, and then plasma-treated in an NH 3 atmosphere.
그런 다음, 상기 CVD산화막 상에 O3-TEOS막을 적층하고 이를 아르곤(Ar)의 스퍼터링으로 처리한 후, O3-TEOS막과 PE-TEOS막을 순차적으로 증착하여 트랜치(16)를 매립하고 고온 열처리 공정을 실시한다.Thereafter, an O 3 -TEOS film was deposited on the CVD oxide film and treated with sputtering of argon (Ar), followed by sequentially depositing an O 3 -TEOS film and a PE-TEOS film to bury the trench 16 and heat treatment at high temperature. Carry out the process.
여기서, 상기 NH3분위기에서 플라즈마 처리는 박막의 표면 처리를 위함이고, 고온 열처리 공정은 후속 박막의 조밀도를 향상시키기 위함이다.Here, the plasma treatment in the NH 3 atmosphere is for the surface treatment of the thin film, the high temperature heat treatment process is to improve the density of the subsequent thin film.
그 후, 상기 적층된 절연막(18)을 CMP 공정 또는 에치-백 공정으로 트랜치(16)의 외측에 위치한 질화막(14)이 노출될 때까지 연마하고 평탄화하여 트랜치(16) 내에만 절연막(18)을 남긴다.Thereafter, the stacked insulating film 18 is polished and planarized by the CMP process or the etch-back process until the nitride film 14 located outside the trench 16 is exposed, and the planarized insulating film 18 is formed in the trench 16 only. Leaves.
도 3을 참조하면, 트랜치(16)내에 절연막(18)이 남게되면 트랜치(16)의 외측에 위치한 영역, 즉 소자영역 상의 질화막(14)과 패드산화막(12)을 순차적으로 식각하여 소자분리막(20)을 형성한다.Referring to FIG. 3, when the insulating film 18 remains in the trench 16, the nitride film 14 and the pad oxide film 12 on the outside of the trench 16, ie, the device region, are sequentially etched to form the device isolation film ( 20).
이어서, 상기 구조물의 전표면에 웰 형성 및 문턱전압 조절용 버퍼산화막(도시 안됨)을 형성하여 웰영역을 형성함과 더불어 이온주입 공정으로 문턱전압을 조절한 후 이를 제거하고 게이트산화막(22)과 게이트용 폴리실리콘막(24)을 순차적으로 형성한 다음 후속의 반도체 제조공정을 진행한다.Subsequently, a buffer oxide film (not shown) for forming a well and a threshold voltage is formed on the entire surface of the structure to form a well region, and after adjusting the threshold voltage by an ion implantation process, the gate oxide film 22 and the gate are removed. The polysilicon film 24 is sequentially formed, and then a subsequent semiconductor manufacturing process is performed.
상기와 같은 종래 기술에 따르면, 트랜치내에만 절연막을 형성한 후 웰 형성 및 문턱전압 조절용 버퍼산화막을 형성하기 위해 트랜치 외측의 질화막과 패드산화막을 순차적으로 제거하는 경우, 트랜치내의 절연막 즉 필드영역과 소자영역의 경계부분 일부가 동시에 식각되어 홈(Pit)이 형성된다. 이로 인하여 후속의 산화공정시 트랜치내의 홈을 통하여 실리콘 내부로 스트레스가 인가된다.According to the prior art as described above, when the nitride film and the pad oxide film outside the trench are sequentially removed in order to form a buffer oxide film for well formation and threshold voltage control after forming the insulating film only in the trench, the insulating film in the trench, that is, the field region and the element A portion of the boundary of the region is simultaneously etched to form a groove. This causes stress to be applied into the silicon through the grooves in the trench during subsequent oxidation processes.
또한, 게이트 입력단에 전압을 인가하는 경우 다른 부분 보다 트랜치의 상단 소자영역과 필드영역의 경계부분에 형성되어 있는 홈에 전계가 집중되어 누설전류 등의 결함을 야기시킴으로써 게이트산화막의 특성 및 소자 특성의 열화를 초래하여 결국 소자의 신뢰성을 저하시킨다.In addition, when a voltage is applied to the gate input terminal, an electric field is concentrated in the groove formed at the boundary between the upper element region and the field region of the trench rather than the other portion, causing defects such as leakage current. It causes deterioration, which in turn lowers the reliability of the device.
상기한 문제점을 해결하기 위한 본 발명의 목적은 트랜치의 상단 필드영역과 소자영역의 경계부분에 형성되는 홈을 제거하여 소자의 전기적 특성을 향상시키도록 한 반도체소자의 소자분리막 제조방법을 제공하는 데 있다.An object of the present invention for solving the above problems is to provide a device isolation film manufacturing method of a semiconductor device to improve the electrical characteristics of the device by removing the groove formed in the boundary between the upper field region and the device region of the trench. have.
도 1 내지 도 3 은 종래 반도체소자의 소자분리막 제조방법을 도시한 제조공정도1 to 3 is a manufacturing process diagram showing a method of manufacturing a device isolation film of a conventional semiconductor device
도 4 내지 도 8 은 본 발명에 따른 반도체소자의 소자분리막 제조방법을 도시한 제조공정도4 to 8 are manufacturing process diagrams showing a device isolation film manufacturing method of a semiconductor device according to the present invention;
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
50 : 반도체기판 52 : 패드산화막 54 : 식각정지층50 semiconductor substrate 52 pad oxide film 54 etching stop layer
56 : 질화막 58 : 감광막 60 : 트랜치56 nitride layer 58 photosensitive layer 60 trench
62 : 절연막 64 : CVD산화막 66 : 스페이서62 insulating film 64 CVD oxide film 66 spacer
68 : 소자분리막 70 : 게이트산화막 72 : 게이트용 폴리실리콘막68 device isolation film 70 gate oxide film 72 polysilicon film for gate
상기한 목적을 달성하기 위하여 본 발명에 따른 반도체 소자의 소자분리막 제조방법은In order to achieve the above object, a device isolation film manufacturing method of a semiconductor device according to the present invention
반도체기판 상에 패드산화막과 식각정지층, 질화막을 순차적으로 적층하는 공정;Sequentially depositing a pad oxide film, an etch stop layer, and a nitride film on a semiconductor substrate;
상기 질화막 상에 감광막의 패턴을 형성하는 공정;Forming a pattern of a photosensitive film on the nitride film;
상기 감광막의 패턴을 식각마스크로 상기 질화막에서부터 순차적으로 식각하여 상기 반도체 기판에 소정 깊이의 트랜치를 형성하는 공정;Etching a pattern of the photoresist layer sequentially from the nitride layer using an etching mask to form a trench having a predetermined depth in the semiconductor substrate;
상기 트랜치를 포함한 상기 반도체 기판 상에 절연막을 적층하고 상기 절연막을 식각하여 상기 트랜치내에만 절연막을 남기는 공정;Stacking an insulating film on the semiconductor substrate including the trench and etching the insulating film to leave the insulating film only in the trench;
상기 절연막 외측의 상기 질화막을 제거하는 공정;Removing the nitride film outside the insulating film;
상기 결과물의 전면에 산화막을 증착하고 상기 절연막 외측의 식각정지층이 제거되기전 까지 건식식각한 후, 스페이서를 마스크로 상기 식각정지층을 식각하여 상기 절연막의 측벽에 스페이서를 형성하는 공정; 및Depositing an oxide film on the entire surface of the resultant and performing dry etching until the etch stop layer outside the insulating film is removed, and then etching the etch stop layer using a spacer as a mask to form a spacer on the sidewall of the insulating film; And
상기 스페이서를 마스크로 상기 절연막 외측의 패드산화막이 제거될 때까지 식각하여 상기 트랜치내에 소자분리막을 형성하는 공정을 포함한다.Forming a device isolation layer in the trench by etching the spacer with a mask until the pad oxide layer on the outside of the insulating layer is removed.
상기 식각정지층은 폴리실리콘막이나 비정질실리콘막으로 형성되며, 150Å ∼ 500Å 정도의 두께로 형성된다.The etch stop layer is formed of a polysilicon film or an amorphous silicon film, and is formed to a thickness of about 150 kPa to about 500 kPa.
상기와 같은 구조를 갖는 반도체 소자의 소자분리막 제조방법에 따르면, 트랜치내의 절연막 외측에 패드산화막과 식각정지층, 질화막이 순차적으로 형성된 상태에서 질화막을 제거한 후, 상기 구조물의 전면에 CVD산화막을 형성하고 절연막 외측의 식각정지층이 제거될 때 까지 식각하여 절연막의 측벽에 스페이서를 형성한 다음, 스페이스를 마스크로 절연막 외측의 패드산화막이 노출될 때까지 식각하여 트랜치내에 소자분리막을 형성함으로써 트랜치의 상단 소자영역과 필드영역의 경계부분에 홈이 형성되는 것을 방지할 수 있어 소자의 전기적 특성을 향상시킨다.According to the method of fabricating a device isolation film of a semiconductor device having the structure as described above, after removing the nitride film in a state in which the pad oxide film, the etch stop layer and the nitride film are sequentially formed on the outer side of the insulating film in the trench, a CVD oxide film is formed on the entire surface of the structure. Etch until the etch stop layer on the outside of the insulating film is removed to form a spacer on the sidewall of the insulating film, and then use a mask as a mask to etch until the pad oxide film on the outside of the insulating film is exposed to form a device isolation film in the trench, thereby forming an upper isolation device. Grooves can be prevented from being formed at the boundary between the region and the field region, thereby improving the electrical characteristics of the device.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 소자분리막 제조방법에 대하여 상세하게 설명하면 다음과 같다.Hereinafter, a device isolation film manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 4 내지 도 8 은 본 발명에 따른 반도체 소자의 소자분리막 제조방법을 도시한 제조공정도이다.4 to 8 are manufacturing process diagrams showing a device isolation film manufacturing method of a semiconductor device according to the present invention.
도 4를 참조하면, 먼저 반도체 기판(50) 상에 버퍼용 패드산화막(52)과 식각정지층(54), 질화막(56)을 순차적으로 증착한다. 패드산화막(52)은 100Å ∼ 200Å 정도의 두께로 형성되며, 질화막(56)은 1000Å ∼ 2000Å 정도의 두께로 형성한다.Referring to FIG. 4, first, a buffer pad oxide film 52, an etch stop layer 54, and a nitride film 56 are sequentially deposited on the semiconductor substrate 50. The pad oxide film 52 is formed to a thickness of about 100 kPa to about 200 kPa, and the nitride film 56 is formed to a thickness of about 1000 kPa to about 2000 kPa.
이 때, 식각정지층(54)은 질화막(56)과 패드산화막(52) 사이의 식각을 완화시키는 완충역할을 하며, 폴리실리콘막 또는 비정질실리콘막으로 형성한다. 또한, 식각정지층(54)은 1500Å ∼ 2000Å 정도의 두께로 형성됨이 바람직하다.At this time, the etch stop layer 54 serves as a buffer to alleviate the etching between the nitride film 56 and the pad oxide film 52, and is formed of a polysilicon film or an amorphous silicon film. In addition, the etch stop layer 54 is preferably formed to a thickness of about 1500 ~ 2000 ~.
다음, 반도체 기판(50)의 필드영역에 트랜치를 형성하기 위하여 질화막(56) 상에 감광막(58)의 패턴을 형성한다.Next, a pattern of the photosensitive film 58 is formed on the nitride film 56 to form a trench in the field region of the semiconductor substrate 50.
감광막(58)의 패턴을 마스크로 이용하여 질화막(56)과 식각정지층(54), 패드산화막(12)을 순차적으로 식각하여 이들의 패턴을 형성한 다음, 반도체 기판(10)을 소정의 폭과 깊이로 식각하여 트랜치(60)을 형성한다.Using the pattern of the photosensitive film 58 as a mask, the nitride film 56, the etch stop layer 54, and the pad oxide film 12 are sequentially etched to form these patterns, and then the semiconductor substrate 10 has a predetermined width. And to form a trench 60 by etching deeply and deeply.
트랜치(60)를 형성할 때 감광막(58)의 패턴을 제거한 후 질화막(56)과 식각정지층(54), 패드산화막(12)의 패턴을 식각마스크로 이용하여 반도체기판(50)에 트랜치(60)를 형성하여도 무방하다.When the trenches 60 are formed, the trenches are removed from the semiconductor substrate 50 by removing the pattern of the photoresist layer 58 and using the nitride layer 56, the etch stop layer 54, and the pad oxide layer 12 as an etch mask. 60) may be formed.
도 5를 참조하면, 감광막(58)의 패턴을 제거한 후 후속 공정에서 소자분리막을 형성하기 위한 절연막(62)을 트랜치(60)의 내,외측 상에 증착한 다음, CMP 또는 에치-백 공정으로 트랜치(60)의 외측영역, 즉 소자영역 상의 질화막(56)이 노출될 때까지 상기 절연막(62)을 연마하여 트랜치(60)내에만 절연막(62)을 남긴다.Referring to FIG. 5, after the pattern of the photoresist layer 58 is removed, an insulating layer 62 is formed on the inside and the outside of the trench 60 to form the device isolation layer in a subsequent process, followed by a CMP or etch-back process. The insulating film 62 is polished until the outer region of the trench 60, that is, the nitride film 56 on the device region is exposed, leaving the insulating film 62 only in the trench 60.
이 때, 상기 절연막(62)으로는 열산화막과, 질화막, CVD산화막을 적층하고 이를 NH3플라즈마 처리한다. 그런 다음, 상기 CVD막 상에 O3-TEOS막을 적층하고 이를 Ar 스퍼터링으로 처리한 후 O3-TEOS막과 PE-TEOS막을 순차적으로 증착한다. 그 후, 후속 공정에서의 박막 조밀도를 향상시키기 위해 고온 열처리을 진행한다.At this time, a thermal oxide film, a nitride film, and a CVD oxide film are stacked as the insulating film 62 and subjected to NH 3 plasma treatment. Thereafter, an O 3 -TEOS film is laminated on the CVD film and treated with Ar sputtering, and then an O 3 -TEOS film and a PE-TEOS film are sequentially deposited. Thereafter, high temperature heat treatment is performed to improve the thin film density in the subsequent step.
여기서, 상기 절연막(62)을 여러층으로 적층하는 이유는 소자의 리프레쉬 특성을 향상시키기 위함이다. 또한, 상기 NH3플라즈마 처리는 박막의 표면처리를 위함이다.The reason why the insulating layer 62 is stacked in multiple layers is to improve refresh characteristics of the device. In addition, the NH 3 plasma treatment is for the surface treatment of the thin film.
도 6을 참조하면, 소자영역 상의 질화막(56)을 인산용액으로 제거한 후, 상기 구조물의 전면에 고온에서 CVD산화막(64)을 1500Å ∼ 2000Å 정도의 두께로 형성한다.Referring to FIG. 6, after removing the nitride film 56 on the element region with a phosphate solution, a CVD oxide film 64 is formed on the entire surface of the structure at a high temperature of about 1500 kPa to about 2000 kPa.
도 7을 참조하면, CVD산화막(64)을 소자영역 상의 식각정지층(54)이 제거전 까지 이방성식각하여 스페이서를 형성한 후, 소자영역 상에 남아있는 식각정지층(54)을 선택적으로 제거하여 절연막(62)의 양측벽에 스페이서(66)을 형성한다.Referring to FIG. 7, after the CVD oxide film 64 is anisotropically etched until the etch stop layer 54 on the device region is removed, the etch stop layer 54 remaining on the device region is selectively removed. Thus, spacers 66 are formed on both side walls of the insulating film 62.
이 때, 절연막(62)의 측벽에 스페이서(66)가 형성됨으로서 종래 절연막 외측의 질화막과 패드산화막을 순차적으로 제거할때 절연막의 일부가 동시에 식각되어 트랜치의 상단부, 소자영역과 필드영역의 경계부분에 홈이 형성되는 것을 방지할 수 있다.At this time, the spacer 66 is formed on the sidewall of the insulating film 62, so that when the nitride film and the pad oxide film on the outside of the conventional insulating film are sequentially removed, part of the insulating film is etched simultaneously, so that the upper part of the trench, the boundary between the device region and the field region. The groove can be prevented from being formed.
도 8을 참조하면, 그 후 스페이서(66)를 마스크로 이용하여 반도체 기판(50) 상의 패드산화막(52)이 제거될 때까지 식각하여 트랜치(60)내에 소자분리막(68)을 형성하게 된다. 이 때, 스페이서(66)에 남아 있게되는 식각정지층(54)과 패드산화막(52)은 반복적인 산화 공정을 거쳐 산화시킨 후 습식식각 공정으로 제거한다.Referring to FIG. 8, the device isolation layer 68 is formed in the trench 60 by etching until the pad oxide layer 52 on the semiconductor substrate 50 is removed using the spacer 66 as a mask. At this time, the etch stop layer 54 and the pad oxide film 52 remaining in the spacer 66 are oxidized through a repetitive oxidation process and then removed by a wet etching process.
이어, 상기 결과물의 전면에 웰 형성 및 문턱전압 조절용 버퍼산화막(도시 안됨)을 형성하여 웰영역을 형성함과 더불어 이온주입 공정으로 문턱전압을 조절한 후 이를 제거하고 게이트산화막(70)과 게이트용 폴리실리콘막(72)을 순차적으로 증착한 후 후속의 반도체 제조공정을 진행한다.Subsequently, a buffer oxide layer (not shown) for forming a well and a threshold voltage is formed on the entire surface of the resultant to form a well region, and after adjusting the threshold voltage by an ion implantation process, the gate oxide layer 70 and a gate are removed. After the polysilicon film 72 is sequentially deposited, a subsequent semiconductor manufacturing process is performed.
한편, 절연막(62) 외측의 반도체 기판(50) 상에 잔존하는 패드산화막(52)을 제거하지 않고 이를 웰 형성 및 문턱전압 조절용 버퍼산화막으로 대체하여도 무방하다.Meanwhile, the pad oxide film 52 remaining on the semiconductor substrate 50 outside the insulating film 62 may be replaced with a buffer oxide film for well formation and threshold voltage adjustment without removing the pad oxide film 52.
상기한 본 발명에 따르면, 트랜치내의 필드영역을 충분히 덮을 정도의 크기로 소자분리막의 프로파일을 형성함으로써 트랜치의 상단부, 즉 필드영역과 소자영역의 경계부분에서 발생되는 홈의 형성을 방지한다.According to the present invention described above, by forming the profile of the device isolation film to a size sufficient to cover the field region in the trench, the formation of grooves generated at the upper end of the trench, that is, the boundary between the field region and the device region, is prevented.
이상에서와 같이 본 발명에 따르면, 트랜치내의 절연막 외측에 패드산화막과 식각정지층, 질화막이 순차적으로 형성된 상태에서 질화막을 제거한 후, CVD산화막을 형성하고 절연막 외측의 식각정지층이 제거되기전 까지 이방성식각하여 절연막의 측벽에 스페이서를 형성한 다음, 스페이스를 마스크로 이용하여 절연막 외측의 식각정지층을 식각하되 패드산화막이 노출될 때까지 식각하여 트랜치내의 필드영역을 충분히 덮을 정도의 크기로 소자분리막을 형성함으로써 다음과 같은 이점이 있다.As described above, according to the present invention, after removing the nitride film in a state where the pad oxide film, the etch stop layer and the nitride film are sequentially formed on the outer side of the insulating film in the trench, the anisotropy is formed until the CVD oxide film is formed and the etch stop layer outside the insulating film is removed. After etching, spacers are formed on the sidewalls of the insulating film. Then, using the space as a mask, the etching stop layer on the outside of the insulating film is etched and etched until the pad oxide film is exposed, so that the device isolation film is large enough to cover the field region in the trench. Formation has the following advantages.
첫째, 트랜치내의 소자분리막, 즉 필드영역과 소자영역의 경계부분에서 홈이 형성되는 것을 방지한다.First, grooves are prevented from being formed in the device isolation film in the trench, that is, the boundary between the field region and the device region.
둘째, 게이트산화막의 특성 및 소자 특성의 열화를 제거함으로써 소자의 전기적 특성 및 신뢰성을 향상시킨다.Second, the electrical characteristics and reliability of the device are improved by eliminating deterioration of the gate oxide film and device characteristics.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980054978A KR20000039592A (en) | 1998-12-15 | 1998-12-15 | Fabrication of substrate separation layer of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980054978A KR20000039592A (en) | 1998-12-15 | 1998-12-15 | Fabrication of substrate separation layer of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000039592A true KR20000039592A (en) | 2000-07-05 |
Family
ID=19562815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980054978A KR20000039592A (en) | 1998-12-15 | 1998-12-15 | Fabrication of substrate separation layer of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000039592A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11466915B2 (en) | 2015-04-06 | 2022-10-11 | Sl Usa, Llc | Snowmaking automation system and modules |
-
1998
- 1998-12-15 KR KR1019980054978A patent/KR20000039592A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11466915B2 (en) | 2015-04-06 | 2022-10-11 | Sl Usa, Llc | Snowmaking automation system and modules |
| US11892222B2 (en) | 2015-04-06 | 2024-02-06 | Sl Usa, Llc | Snowmaking automation system and modules |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6174785B1 (en) | Method of forming trench isolation region for semiconductor device | |
| KR100195208B1 (en) | Method of forming an element isolation region in a semiconductor device | |
| US6124184A (en) | Method for forming isolation region of semiconductor device | |
| KR20010065186A (en) | Method of manufacturing a flash memory device | |
| KR100275732B1 (en) | Method for forming a trench type device isolation film uisng an anneling | |
| KR20010068644A (en) | Method for isolating semiconductor devices | |
| KR20000039592A (en) | Fabrication of substrate separation layer of semiconductor substrate | |
| KR100305026B1 (en) | Manufacturing method of semiconductor device | |
| KR100268907B1 (en) | Isolation film of semiconductor device and method for forming the same | |
| KR100639182B1 (en) | Method for isolating semiconductor devices | |
| KR100419754B1 (en) | A method for forming a field oxide of a semiconductor device | |
| KR20000045299A (en) | Method for manufacturing semiconductor device | |
| KR20000039029A (en) | Method of forming trench isolation having double liner | |
| KR20010061041A (en) | Forming method for a field oxide of semiconductor device | |
| KR20040059998A (en) | Method for manufacturing isolation layer in semiconductor device | |
| KR20030052663A (en) | method for isolating semiconductor device | |
| KR19990057375A (en) | Device Separating Method of Semiconductor Device | |
| KR20000044658A (en) | Method for forming isolation layer of semiconductor device | |
| KR20010003615A (en) | A method for forming trench type isolation layer in semiconductor device | |
| KR19990048786A (en) | Method of forming device isolation film of semiconductor device | |
| KR100439105B1 (en) | Method for fabricating isolation layer of semiconductor device to improve cut-off characteristic at both corners of trench and inwe between narrow lines | |
| KR20030000436A (en) | Method for manufacturing isolation of semiconductor device | |
| KR19980038880A (en) | Device Separating Method of Semiconductor Device | |
| KR20030001953A (en) | Method for fabricating semiconductor device | |
| KR20010019280A (en) | Method for shallow trench isolation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |