KR20000034427A - Device for inverse-multiplexing tributary unit group signal and ds1 signal in optical subscriber transmission system - Google Patents

Abstract

PURPOSE: A device for inverse-multiplexing a tributary unit group(TUG-2) signal and a DS1 signal in an optical subscriber transmission system is provided so that the TUG-2 signal can be inverse-multiplexed to the DS1 signal. CONSTITUTION: A device for inverse-multiplexing a TUG-2 signal and a DS1 signal includes the following units. A clock control unit for TUG-2 signal(310) receives main clock signals, and generates a tributary unit(TU-11) signal conversion processing clock and a TU-11 signal clock for each channel. A TU-11 signal extracting unit(320) receives a parallel TUG-2 signal, and outputs a parallel TU-11 signal. A test pattern generating unit(340) generates a test DS1 signal. A DS1 signal processing unit(330) includes the following units. A clock processing unit for a pointer and a lower virtual container(332) generates a pointer processing clock and an overhead processing clock. A lower virtual container forming and synchronizing unit(331) receives the parallel TU-11 signal, forms a lower virtual container signal, and outputs the DS1 signal. An overhead processing unit(333) performs an alarm function in regard to the overhead. An encoder(334) selects the DS1 signal or the test DS1 signal, and encodes and outputs the selected signal.

Description

A unit of demultiplexing Tributary Unit Group-2 signals to DS1 signals in Fiber Loop Carrier system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demultiplexing device between a hierarchy unit group signal and a DS1 signal in an optical subscriber transmission device, and in particular, a hierarchy unit group signal (TUG-2: Tributary Unit Group-2) input for use in an optical subscriber transmission device. The present invention relates to a demultiplexing device that finally generates and outputs a DS1 signal by extracting each lower virtual box multiframe (VC-11 Multi-Frame) and processing overhead.

1 is a basic network configuration diagram of an optical subscriber transmission apparatus, and includes a main station (Central Office Terminal) and a remote station (Remote Terminal). At this time, the master station 10 is connected to each subscriber through a general switching line, a leased line, a local area network (LAN), and the like, and these subscribers are connected to the ordinary telephone subscriber or the leased line subscriber through the remote station 11. Connected with

The main station 10 and the remote station 11 constituting such an optical subscriber transmission device are connected by the optical path 12 to perform communication by light with each other. At this time, the communication by the light between the master station 10 and the remote station 11 is performed by using a synchronous transmission method. In the synchronous transmission method, each signal is multiplexed according to a synchronous digital hierarchy (SDH). It is multiplexed by the procedure and then transmitted and received.

FIG. 2 is a diagram illustrating a mapping structure of a DS1 signal to a synchronous transport module signal (STM-1) and a DS1 signal 110 is mapped to a lower box C-11: 120 having a container structure. When the lower path overhead 131 is added to the lower box C-11: 120, the lower virtual box 130 becomes a lower virtual box 130.

In addition, when a pointer 141 indicating the position of the lower virtual box 130 is added to the lower virtual box VC-11: 130, it becomes a level unit signal TU-11: 140, and the level unit signal 140 Four are gathered to form a hierarchical unit group signal 150 (TUG-2). The pointer 151 to the four hierarchical unit signals (TU-11: 140) is the front of the hierarchical unit group signal 150: TUG-2. It is located at all.

When seven hierarchical unit group signals 150 (TUG-2) are gathered and the upper path overhead 161 is added to the foremost part, a high-level virtual box signal (VC-3: 160) is generated. When the pointer 171 is added to the 160, a management unit signal (AU-3: 170) is generated, and three management unit signals (170) are gathered to form a management unit group signal (180: AUG). When a section overhead is added to the unit group signal 180 (AUG), the synchronous transport module signal STM-1: 190 is finally generated.

As described above, the DS1 signal 110 input to the optical subscriber transmission apparatus using the synchronous transmission method is made into the synchronous transport module signal (STM-1: 190) after each multiplexing process, and then the optical path 12 is opened. Is sent through.

Therefore, the optical subscriber transmission device requires a device that makes the input unit group signal 150 (TUG-2) into a DS1 signal during the demultiplexing procedure shown in FIG.

Accordingly, the present invention has been made to meet the above needs, and is used in the optical subscriber transmission apparatus, to provide an apparatus for demultiplexing the Tributary Unit Group-2 (TUG-2) into a DS1 signal Its purpose is.

In order to achieve the above object, in the optical subscriber transmission device according to the present invention, the demultiplexing device between the level unit group signal and the DS1 signal receives predetermined main clock signals and receives the parallel level unit group signal (TUG-2). A control unit for generating and outputting a predetermined unit signal conversion processing clock and a channel unit signal signal for each channel for converting the parallel unit signal (TU-11) into parallel; A hierarchical unit signal extracting unit which receives a predetermined hierarchical hierarchical unit signal (TUG-2), generates and outputs a predetermined number of hierarchical hierarchical unit signal (TU-11) using the hierarchical unit signal conversion processing clock; A test pattern generator for generating and outputting a predetermined test DS1 signal; And a predetermined pointer processing clock for pointer processing of the hierarchy unit signal TU-11 output from the hierarchy unit signal extracting unit and an overhead processing clock for overhead processing by using the channel unit signal clock for each channel. A pointer and a clock processing unit for a lower virtual box to generate and output the same; The lower level unit signal TU-11 is input from the level unit signal extracting unit, forms a lower virtual box signal VC-11 using the pointer processing clock, and then outputs the lower level virtual box signal VC-11. Virtual box forming and synchronizing unit; Receives the lower virtual box signal VC-11 formed from the lower virtual box forming and synchronizing unit, extracts each overhead data using the overhead processing clock, and performs a predetermined alarm function for each overhead. An overhead processor; And a coder for selecting and encoding one of the DS1 signal output from the lower virtual box forming and synchronizing unit and the DS1 signal output from the test pattern generator according to a predetermined transfer command signal sent from the main controller. It is characterized by including a DS1 signal processing unit.

At this time, the pointer and the lower virtual box clock processor uses the channel-level signal clock for each channel to extract the clock signal for the level signal pointers V1 to V4 and the clock for lower path overhead V5 and the pointer value. A hierarchical unit signal clock control unit for generating and outputting a predetermined hierarchical unit signal clock according to an increase / decrease of the control unit; After extracting a pointer from the parallel level unit group signal TUG-2 using the clock signals output from the level unit signal clock control unit, the pointer is interpreted to determine predetermined pointer state information, pointer adjustment information, and each level. A pointer processor configured to generate a low path overhead positioning clock (V5 clock) for each unit signal; A bit leaking control unit which receives the pointer adjustment information (stuffing information) and a read address and a write address used for a predetermined synchronization buffer and generates a predetermined reference clock accordingly; And a lower virtual box that generates and outputs an overhead processing clock and a predetermined DS1 processing clock of the lower virtual box signal VC-11 using the lower path overhead positioning clock (V5 clock) and a reference clock. It can be implemented more preferably by including a clock control unit.

In addition, the lower virtual box forming and synchronizing unit outputs the parallel lower level virtual box signal VC-11 synchronized with the reference clock by converting the parallel level unit signal TU-11 outputted from the level unit signal extracting unit. A reception synchronization buffer unit; According to a predetermined local loopback control signal from the main control device, a synchronized parallel lower virtual box signal VC-11 output from the reception synchronization buffer unit and a predetermined parallel lower virtual box signal VC-11 transmitted. A parallel / serial conversion unit for converting and outputting a lower virtual box signal VC-11 of a serial after selecting one of the serial signals; A clock generator which generates and outputs a DS1 processing clock that satisfies a predetermined jitter standard; And a receiving asynchronous buffer unit configured to receive the serial lower virtual box signal VC-11 outputted from the parallel / serial converting unit, remove overhead, and form and output a DS1 signal. Can be.

1 is a basic network configuration of an optical subscriber transmission device,

2 is a mapping structure diagram of a synchronous transport module signal STM-1 to a DS1 signal;

3 is a block diagram of the present invention;

4 is a block diagram of a clock processing unit for a pointer and a lower virtual box;

5 is a block diagram of a lower virtual box forming and synchronizing unit;

6 is a block diagram of an overhead processor.

* Explanation of symbols for main parts of the drawings

310: Clock control unit for the step unit group signal

320: step unit signal extraction unit 330: DS1 signal processing unit

331: Form and synchronize the child virtual box

332: Clock processing unit for pointer and sub virtual box

333: overhead processing unit 334: code unit

340: test pattern generator 410: step unit signal clock control unit

420: pointer processing unit 430: bit leaking control unit

440: clock control unit for the lower virtual box 510: reception synchronization buffer unit

520: parallel / serial conversion unit 530: reception asynchronous buffer unit

540: clock generator

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a block diagram of the demultiplexing apparatus 300 between the hierarchical unit group signal and the DS1 signal in the optical subscriber transmission device according to the present invention, wherein the hierarchical unit group signal clock control unit 310 and the hierarchical unit signal extracting unit 320 are shown. ), Four DS1 signal processing units 330 and a test pattern generation unit 340 which receive the hierarchical unit signals TU-11 from the hierarchical unit signal extracting unit 320 and convert them into DS1 signals.

The apparatus 300 of the present invention receives the parallel level unit group signal (TUG-2) under the control of a predetermined main control unit (200: Main control unit) responsible for the overall control of the optical subscriber transmission device, Demultiplexes into 4 DS1 signals and outputs them.

At this time, each DS1 signal processing unit 330 is composed of a lower virtual box forming and synchronization unit 331, a pointer and a lower virtual box clock processing unit 332, an overhead processing unit 333, and a code unit 334. do.

First, the clock control unit 310 for the hierarchy unit group signal will be described in detail.

The clock control unit 310 for the hierarchical unit group signal receives a predetermined main clock signal and converts the hierarchical unit signal TUG-2 in parallel to the hierarchical unit signal TU-11 in parallel. -11) Create and output the conversion processing clock and the channel-level signal clock for each channel.

That is, after receiving the 6.912 MHz clock and the 2 KHz frame clock as the main clock signal, the 864 KHz (6.912 MHz / 8) hierarchical unit group signal (TUG-) for receiving parallel hierarchical unit group signal (TUG-2) is used. 2) Create and output a receive clock, three 288KHz hierarchy unit signal (TU-11) processing clocks, and a 8KHz pointer clock.

In addition, the 864KHz clock is used to generate and output a 216KHz (864KHz / 4) clock for each of the four channel unit signals (TU-11).

The hierarchical unit signal extracting unit 320 receives a predetermined parallel hierarchical unit group signal (TUG-2: 864 Kbps), and then uses the hierarchical unit signal conversion processing clock signals output from the hierarchical unit group signal clock control unit 310. The signal is divided into four parallel leveling unit signals (TU-11: 208 KHz) and output to the respective DS1 signal processing units 330.

4 is a block diagram of the pointer constituting the DS1 signal processor 330 and the clock processor 332 for the lower virtual box, wherein the step unit signal clock controller 410, the pointer processor 420, and the bit leaking controller 430 are shown. And a lower virtual box clock control unit 440 to perform a pointer processing function, and generate an overhead processing clock, a clock for processing a DS1 signal, and the like.

First, the hierarchical unit signal clock control unit 410 receives a hierarchical unit signal (TU-11) clock for each channel from the hierarchical unit group signal clock control unit 310, and generates clocks for pointer processing using the same. In this case, each level unit signal TU-11 includes four pointer bytes and one low path overhead byte, and the four pointer bytes are called V1, V2, V3, and V4, respectively, and the low path overhead Is called V5.

That is, the hierarchical unit signal clock control unit 410 generates and outputs a V1 byte extracting clock, a V2 byte extracting clock, a V3 byte extracting clock, a V4 byte extracting clock, and a V5 byte extracting clock. In addition, if the pointer is increased, a 200 kHz level unit signal (TU-11) clock is generated by gapping the byte immediately after the V3 byte. TU-11) generates a clock. If the pointer is not increased or decreased, a TU-11 clock signal of 208KHz is generated and output.

The pointer processing unit 420 extracts and interprets the pointer from the parallel level unit group signal TUG-2 using the pointer processing clocks sent from the level unit signal clock control unit 410 to determine the state of the pointer and the alarm state. In addition, it performs a pointer adjustment function and generates a V5 clock of received data for each level unit signal.

More specifically, the parallel unit signal of the unit unit receives the V1 byte extraction clock, the V2 byte extraction clock, the V3 byte extraction clock, and the V4 byte extraction clock from the hierarchical unit signal clock control unit 410. Extracts V1 byte, V2 byte, V3 byte, and V4 byte from (TUG-2), and outputs the V2 byte and V4 byte values separately so that they can be referenced from other devices.

In addition, when an abnormal pointer state is received more than 8 times in succession, or when a new data indicator (NDF: New Data Flag) having a value of "1001" is received more than 8 times in succession, the pointer loss state (LOP: Loss). Outputs a " LOP signal "

If a normal pointer value is received in three consecutive frames, or if a new data indicator (NDF) having a value of "110" is detected three times in a steady state, the pointer loss state (LOP) is released. In addition, the pointer loss state (LOP) is canceled even when an alarm indication signal (AIS) for the hierarchical unit signal is received.

On the other hand, when the V1 byte and the V2 byte are both received in a state of having a logic value '1' three times in succession, a signal indicating an alarm display signal (AIS) reception state for the hierarchy unit signal is output. At this time, when the new data indicator (NDF) of the V1 byte and the V2 byte is "1001", or a valid pointer value having a normal new data indicator is detected three times in succession, or eight abnormal pointers are received in succession. In this case, the alarm display signal (AIS) reception status of the step unit signal is canceled.

In addition, the new data indicator (NDF) is normal and the signal magnitude bit (SS) coincides, and at least 3 bits of the 5-bit incremental bits (I bits) in the pointer value (PV) are inverted, and 5 bits. More than 3 bits of the decrease bit (D bit) of the inverted state are not inverted, and the pointer increase signal is generated when the new data indicator (NDF) enable, pointer increase, and pointer decrease have not occurred during the previous 3 frames. .

In addition, the new data indicator (NDF) is normal and the signal magnitude bits (SS) also match, at least three of the five bit reduction bits (D bits) are inverted in the pointer value, and five bit increment bits (I bits). More than 3 bits are not inverted and pointer decrement signal is generated when new data indicator (NDF) enable, pointer increase and pointer decrement have not occurred during the previous 3 frames.

At this time, when the pointer adjustment occurs, the bit leaking control unit 430 notifies this, and the state of the signal magnitude bit SS is separately output through the external signal line.

If the signal magnitude bit (SS) matches, the pointer value is within addresses 0 to 139, and the new data indicator (NDF) is "1001", "1", "1101", "1011", or "1000" Generates a new data indicator (NDF) enable signal, the received pointer value is outside the range of address 0 to address 103, the signal magnitude bit (SS) is in an inconsistent state, or the new data indicator (NDF). If it is enabled and the new data indicator (NDF) is not in a normal state, it is regarded as an invalid pointer value (Invalid PV) state and outputs it.

In addition, when the received signal magnitude bit SS is in an inconsistent state three or more times in succession, the signal magnitude bit SS state signal indicates a signal magnitude bit error state.

Then, the V5 offset signal (V5 clock) according to the pointer value is calculated and output. At this time, the current pointer value is determined as shown in Table 1 below.

Previous pointer value state Current pointer value state Current PV value No pointer increment / decrement Pointer Loss (LOP) Previous pointer value No pointer increment / decrement Alarm display signal (AIS) Previous pointer value No pointer increment / decrement Invalid pointer value Previous pointer value No pointer increment / decrement NDF enable Current pointer value No pointer increment / decrement 3 consecutive frames normal Current pointer value No pointer increment / decrement Pointer up / down Previous pointer value Pointer increments Invalid pointer value PV + 1 before pointer increments Pointer decrement Invalid pointer value PV-1 before pointer decrement Pointer value = 0 Pointer decrement Pointer value = 104

On the other hand, when the alarm display signal AIS state or the pointer loss state LOP of the hierarchical unit signal TU-11 as described above is released or when the pointer value is changed (except the pointer increase / decrease), The virtual box forming and synchronizing unit 331 outputs an initialization control signal to the receiving synchronization buffer unit 510.

The bit leaking control unit 430 receives a pointer adjustment signal (stuffing information) from the pointer processing unit 420, calculates a bit leaking interval, and generates a 1.664 MHz clock from the 6.912 MHz clock. In addition, by receiving the read address and the write address from the reception sync buffer unit 510, the underflow and overflow states of the buffer are monitored, and the compensation process is performed accordingly.

The lower virtual box clock control unit 440 uses the lower virtual box signal VC-11 processing clock (1.664 MHz) from the bit-leaking control unit 430 and the V5 clock from the pointer processing unit 420. An overhead processing clock and a DS1 processing clock required for overhead extraction of the box signal VC-11 signal are generated and output. That is, a clock is generated which converts the parallel lower virtual box signal (VC-11: 208 KHz) into a serial signal (1.664 MHz).

In addition, according to the state of the C1 bit and the C2 bit, the read clock of the receiving asynchronous buffer unit 530 is generated as shown in Table 2 below, and according to the centering request signal from the receiving asynchronous buffer unit 530. Gap one bit into the frame.

At this time, the C1 bit and the C2 bit are bits that are inserted when the DS1 signal matches the lower virtual box signal VC-11, and are bits used for alignment control on the alignment enforcement bits J1 and J2.

C1 status C2 status Read clock 0 0 1.546 MHz One 0 1.544 MHz 0 One 1.544 MHz One One 1.542 MHz

5 is a block diagram of the lower virtual box forming and synchronizing unit 331. The receiving synchronous buffer unit 510, the parallel / serial converting unit 520, the receiving asynchronous buffer unit 530, and the clock generating unit 540. In this case, the parallel unit signal TU-11 is received from the unit signal extractor 320 and processed, and then outputs as a DS1 signal.

The reception synchronization buffer unit 510 performs an elastic buffer function for synchronizing the lower virtual box signal VC-11 in parallel synchronized with the step unit signal formation clock (208 KHz) to the synchronization clock (1.664 MHz). The lower virtual box signal (VC-) synchronized with the parallel lower unit signal TU-11 output from the unit signal extractor 320 to the parallel lower virtual box signal VC-11 receiving clock (1.664 MHz). 11) to make output.

At this time, the reception synchronization buffer unit 510 is initialized by changing the buffer initialization control signal from the pointer processing unit 420 or the forced initialization control signal from the main controller 200 (the write / read address is changed to an initial state). do. As a preferred embodiment of determining the starting point of an address, start at zero for the write clock and start at seven for the read clock.

In addition, for self-diagnosis of the reception direction, an 8-bit parity is calculated for the lower virtual box signal VC-11, and a parity error signal is detected when an error occurs after detecting an error by detecting whether it matches the input parity bit. Outputs

The parallel / serial converter 520 converts the synchronized parallel lower virtual box signal VC-11 outputted from the reception sync buffer unit 510 into a serial lower virtual box signal VC-11 of 1.664 Mbps and outputs the converted VC-11. do.

In addition, a predetermined local loopback control signal is received from the main controller 200. When the signal is a signal instructing to perform a local loopback function for the lower virtual box signal VC-11, the lower virtual received is received. The lower virtual box signal VC-11 transmitted instead of the box signal VC-11 is selected and output.

The reception asynchronous buffer unit 530 receives the serial lower virtual box signal VC-11 output from the parallel / serial converter 520 and uses the 64-stage elastic buffer to lower virtual box signal VC-11. In the multi-frame consisting of the information data excluding the overhead, that is, pure DS1 signal is produced and output. In this case, a read clock generated by the clock controller 440 for the lower virtual box is used as the read clock.

First, when the first two V5 clocks are generated by using the DS1 processing clock (1.664MHz) and the overhead processing clock, 64 division is performed to generate the write address of the buffer, and the DS1 processing clock (1.544MHz) is used. It creates a read address of the buffer. Initially, when the write address is 36, the read address is 0.

Then, the write address is compared with the read address, and both read addresses have logical value '1', all write addresses have logical value '0', all read addresses have logical value '0' and all write addresses have logical value. If the status is '1', the address value is the same, or the difference between the write address and the read address is 1 or 2, the buffer automatic initialization function is executed and a signal (initialization status signal) indicating this is output.

In addition, when the reception synchronization buffer unit 510 is initialized, the reception synchronization buffer unit 510 is initialized together, and a write request signal is output by comparing a write address with a read address.

On the other hand, according to a predetermined read clock selection signal sent from the main controller, one of the clock generated by the lower virtual box clock controller 440 and the clock generated by the clock generator 540 is selected as the read clock. .

The clock generator 540 generates a 1.544 MHz clock that satisfies a predetermined jitter standard and provides the received asynchronous buffer unit 530.

6 is a block diagram of the overhead processing unit 333. The overhead processing unit 333 is a parallel lower virtual box signal VC-11 and a lower virtual box clock control unit (outputted from the reception synchronization buffer unit 510). After receiving the overhead processing clocks output from 440, each overhead data is extracted from the received parallel lower virtual box signal VC-11.

At this time, a majority decision (2/3) of the C1 bit and the C2 bit is performed, and a Remote Failure Indication (RFI) bit of the extracted V5 byte is output.

In addition, a bit interpolation parity-2 (BIP-2) bit from the extracted V5 data and a bit interpolation parity (BIP-2) value calculated from the received serial lower virtual box signal VC-11 are obtained. In comparison, if an error exists, a bit shift parity error signal is output.

If the RDI bit has a logical value of '1' for 10 consecutive times, the RDI bit outputs a signal indicating an RDI error condition, and the RDI bit is set to 10. If it has a logic value of '0' consecutively, a signal for releasing a remote fault indication (RDI) error state is output.

If the signal level display state is received more than 3 times in an inconsistent state, a signal indicating the V5 Mismatch path trace ID / signal label (MIS) state is output, and when the normal byte is received more than 3 times, the signal is released. . If the signal level display state is received three times in succession, the state of the equipment level is declared and the equipment is unequipped. If the normal byte is received three or more times, the state is released.

In addition, for the lower virtual box signal VC-11, the bit error rate exceeding state (E-BER: Extensive-Bit Error Rate) is declared or released.

The coder 334 selects one of the DS1 signal output from the reception asynchronous buffer unit 530 and the DS1 signal output from the test pattern generator 340 according to the transfer command signal sent from the main controller 200. After encoding according to the B8ZS code method, it is output. At this time, the clock signal used to process each input signal is also switched.

On the other hand, the test pattern generator 340 generates a DS1 pattern required for self-test in synchronization with a predetermined DS1 alarm display signal (AIS) clock and supplies it as an input signal of the coder 334.

As described above, the present invention can be generally used where a demultiplexing function of a management unit group signal (TUG-2) to a DS1 signal is required in configuring a communication device using a synchronous transmission method.

Claims (3)

A device which is used in a predetermined optical subscriber transmission device and demultiplexes a hierarchy group unit signal (TUG-2) into a DS1 signal during a synchronous demultiplexing procedure under the control of a predetermined main control unit (MCU), the predetermined main clock signal Level unit for generating and outputting a predetermined level unit signal conversion processing clock for converting the parallel level unit group signal (TUG-2) into a parallel level unit signal (TU-11) and a level level unit signal clock for each channel. A clock control unit for the group signal; A hierarchical unit signal extracting unit which receives a predetermined hierarchical hierarchical unit signal (TUG-2), generates and outputs a predetermined number of hierarchical hierarchical unit signal (TU-11) using the hierarchical unit signal conversion processing clock; A test pattern generator for generating and outputting a predetermined test DS1 signal; And A predetermined pointer processing clock for pointer processing of the hierarchy unit signal TU-11 output from the hierarchy unit signal extracting unit and an overhead processing clock for overhead processing are used by using the channel unit signal clock for each channel. A pointer for creating and outputting a clock processing unit for a lower virtual box; The lower level unit signal TU-11 is input from the level unit signal extracting unit, forms a lower virtual box signal VC-11 using the pointer processing clock, and then outputs the lower level virtual box signal VC-11. Virtual box forming and synchronizing unit; Receives the lower virtual box signal VC-11 formed from the lower virtual box forming and synchronizing unit, extracts each overhead data using the overhead processing clock, and performs a predetermined alarm function for each overhead. An overhead processor; And A DS1 comprising a coder for selecting and encoding one of a DS1 signal output from the lower virtual box forming and synchronizing unit and a DS1 signal output from a test pattern generation unit according to a predetermined transfer command signal sent from the main controller; The demultiplexer between the hierarchical unit group signal and the DS1 signal in the optical subscriber transmission device, characterized in that it comprises a signal processing unit. The clock signal processor of claim 1, wherein the pointer and the lower virtual box clock processing unit extracts a clock for extracting the hierarchy unit signal pointers V1 to V4 and a clock for extracting the lower path overhead V5 using the channel-specific signal for each channel. A level unit signal clock controller configured to generate and output a predetermined level unit signal clock according to an increase / decrease of a pointer value; After extracting a pointer from the parallel level unit group signal TUG-2 using the clock signals output from the level unit signal clock control unit, the pointer is interpreted to determine predetermined pointer state information, pointer adjustment information, and each level. A pointer processor configured to generate a low path overhead positioning clock (V5 clock) for each unit signal; A bit leaking control unit which receives the pointer adjustment information (stuffing information) and a read address and a write address used for a predetermined synchronization buffer and generates a predetermined reference clock accordingly; And The lower virtual box clock for generating and outputting the overhead processing clock and the predetermined DS1 processing clock of the lower virtual box signal VC-11 using the lower path overhead positioning clock (V5 clock) and the reference clock. A demultiplexing device between a hierarchy unit group signal and a DS1 signal in an optical subscriber transmission device comprising a control unit. 2. The parallel virtual box signal VC-11 of claim 1, wherein the lower virtual box forming and synchronizing unit synchronizes the parallel level unit signal TU-11 outputted from the level unit signal extracting unit to the reference clock. A reception synchronization buffer unit for outputting the same; According to a predetermined local loopback control signal from the main control device, a synchronized parallel lower virtual box signal VC-11 output from the reception synchronization buffer unit and a predetermined parallel lower virtual box signal VC-11 transmitted. A parallel / serial conversion unit for converting and outputting a lower virtual box signal VC-11 of a serial after selecting one of the serial signals; A clock generator which generates and outputs a DS1 processing clock that satisfies a predetermined jitter standard; And And a receiving asynchronous buffer unit configured to receive the serial lower virtual box signal VC-11 outputted from the parallel / serial conversion unit, exclude overhead, and form and output a DS1 signal. A demultiplexing device between a hierarchy unit group signal and a DS1 signal in a transmission device.