KR20000027870A - Column repair apparatus for semiconductor memory - Google Patents

Abstract

PURPOSE: A column repair apparatus for a semiconductor memory is provided to minimize a chip size required when operating a column repair and to reduce delay time when operating the column repair by alternating an input and output line to a redundancy input and output line. CONSTITUTION: A reconfiguration controller(400) reads data of a fuse in which a fail is occurred and outputs a signal to a fail input and output line for switching a data line suitable for a bank approached when operating a column of a memory. A data line switching decoder(401) receives the signal to the fail input and output line from the reconfiguration controller(400) and decodes the received signal. A data line reconfiguration unit(402) switches the fail input and output line of a memory cell array unit(403) to a redundancy input and output line according to a decoding signal of the data line switching decoder(401).

Description

Column repair device of semiconductor memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column repair apparatus of a semiconductor memory, and more particularly, to replacing a input / output line connected to a failed bit line of a memory having a large number of input / output lines with a redundancy input / output line to a chip required for a column repair operation. The present invention relates to a column repair apparatus of a semiconductor memory capable of minimizing an area and reducing a delay time during a column repair operation.

Column repair is a method of improving the yield of memory by replacing a corresponding bit line with a redundancy bit line when a fail occurs in a memory cell array. On the contrary, a fail occurs in a word line of a memory cell array so that a fail word line is repaired. Replacing with a redundancy word line is called a word repair or a lowly pair.

In general, when the column address of the memory is input from the outside, the column address is compared with the fail column address stored in the column fuse array. If the column address and the fail column address match, the input column address is a fail bit. Since the data stored in the line is to be accessed, the decoder corresponding to the column address does not operate. Instead, the redundant column decoder is operated to perform the repair operation by writing or reading information in the corresponding redundancy bit line.

Recently, a new concept of memory in the form of integrating memory and logic has been studied. In this case, since memory and logic input and output are connected inside the chip, it is not necessary to drive large capacities at the time of input and output. To increase the bandwidth of the logic, a wideband data I / O bus is used.

FIG. 1 is a block diagram showing an embodiment of a conventional column repair apparatus of a semiconductor memory. As shown in FIG. 1, a column address for receiving a predetermined column address signal and comparing it with a fail column address stored in a fuse array in advance is subjected to predetermined processing. A signal decoder 100 and a column decoder 101 for receiving a column address signal, decoding the same, and outputting a column selection signal according to the result of the comparison between the column address signal processor 100 and the fail column address. )Wow; A memory cell array unit 104 which receives a column selection signal from the column decoders 101 and 102 and selects a bit line corresponding thereto; A redundancy decoder 103 which receives a fail column address signal and decodes it to select a redundancy column line when the column address and the fail column address match the input result as a result of the comparison of the column address signal processing unit 100; The redundancy cell array unit 105 receives a redundancy column selection signal from the redundancy decoder 103 and selects a corresponding redundancy bit line. The operation of the conventional apparatus configured as described above will be described.

First, the column address signal processing unit 100 receives a predetermined column address signal and compares it with a fail column address signal previously stored in the fuse array, and outputs a column address signal or a fail column address signal accordingly.

At this time, if the input column address signal and the fail column address signal do not match, the column address signal processing unit 100 outputs the column address signal accordingly.

Then, the column decoders 101 and 102 receive the column address signal from the column address signal processing unit 100, decode the column address signal, and apply the corresponding column selection signal to the memory cell array unit 104. The memory cell array unit 104 receives the column selection signals of the column decoders 101 and 102 and selects the corresponding bit lines. As a result, the memory cell array unit 104 together with the word lines selected by the previously generated word line signals is consequently selected. A predetermined cell of the two-dimensional memory cell array unit 104 is selected.

In contrast, the column address signal processing unit 100 outputs a fail column address signal to the redundancy decoder 103 when the input column address signal and the fail column address signal match.

As a result, the redundancy decoder 103 receives the fail column address signal from the column address signal processing unit 100, decodes the redundancy column selection signal, and applies the redundancy column selection signal accordingly to the redundancy cell array unit 105. The cell array unit 105 receives a redundancy column selection signal from the redundancy decoder 103, selects a corresponding redundancy bit line, and performs a column repair operation.

Here, the column repair operation will be described in the flowchart of FIG.

First, when the column address signal is input, the column address signal is compared with the fail column address signal previously recorded in the column fuse array.

At this time, if the column address signal inputted as a result of the comparison is different from the fail address signal recorded in the fuse array, the normal column path is opened, and the bit lines selected by the corresponding column decoders 101 and 102 are connected to the input / output line. If the column address signal is the same as the fail address signal recorded in the fuse array, instead of selecting the column decoders 101 and 102, a redundancy column decoder is selected so that the redundancy bit line is connected to the input / output line to perform the column repair operation. Perform.

Therefore, when performing the column repair operation as described above, a step of comparing the input column address signal with the fail address signal stored in the fuse array is required for each column operation of the memory into which the column address signal is input. Since the column operation of the memory operates much faster than the row operation of the memory in which the word line is selected / released, reducing the cycle time of the column operation is inevitable for the high speed of the memory.

3 is a block diagram showing a configuration of a column repair apparatus of a semiconductor memory in which the number of bit lines corresponding to one column address is doubled. As shown in FIG. 3, the general configuration and operation are the same as in FIG. Since the number of bit lines corresponding to the redundancy bit line is doubled, the area of the portion consumed by the column repair is doubled even if only one bit line fails.

That is, in the case of a conventional device operating as described above, when an arbitrary bit line fails, the normal column path corresponding thereto is closed and the redundancy path is opened to perform the repair. In the case of a wide input / output memory having a large number of bit lines corresponding to the column address, Since the number of bit lines that need to be replaced at the time of repair operation is large, the area of the chip required for the repair operation increases, and the step of comparing the column address inputted during the memory operation with the fail column address stored in the fuse array. This necessitates a time delay in processing the column address signal, thereby inhibiting the speed of the memory.

Accordingly, the present invention devised in view of the above-described problems is to replace the input and output lines connected to the failed bit line with redundant input and output lines to perform column repair to minimize the area of the chip and to reduce the delay time It is an object of the present invention to provide a column repair apparatus of a memory.

1 is a block diagram showing a configuration of a column repair apparatus of a conventional semiconductor memory.

2 is an operation flowchart of a column repair method of a conventional semiconductor memory.

Fig. 3 is a block diagram showing the configuration of a column repair apparatus of a semiconductor memory in which the number of bit lines corresponding to one column address has doubled.

Fig. 4 is a block diagram showing the structure of the column repair apparatus of the semiconductor memory of the present invention.

***** Description of the symbols for the main parts of the drawings *****

400: Reconstruction Controller 401: Data Line Switching Decoder

402: data line reconfiguration section 403: memory cell array section

In order to achieve the above object, the present invention provides a reconfiguration controller that reads data of a failing fuse and outputs a signal for a fail input / output line to switch a data line suitable for each bank approaching a column operation of a memory. ; A data line switching decoder which receives a signal for a fail input / output line from the reconstruction controller and decodes it; The data line reconfiguring unit is configured to switch the fail input / output line of the memory cell array unit to the redundancy input / output line by the decoding signal of the data line switching decoder.

Hereinafter, operations and effects of the column repair apparatus of the semiconductor memory according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram showing an exemplary embodiment of a column repair apparatus of a semiconductor memory according to the present invention. As shown in FIG. 3, data suitable for each bank accessed when a column operation of a memory is read by reading data of a failed fuse is shown. A reconfiguration controller 400 for outputting a signal for the fail input / output line to switch the line; A data line switching decoder 401 which receives a signal for a fail input / output line from the reconstruction controller 400 and decodes it; The data line reconstruction unit 402 switches the fail input / output line of the memory cell array unit 403 to a redundant input / output line by the decoding signal of the data line switching decoder 401.

The reconstruction controller 400 stores first and second fuses having addresses of fail data lines for each of the first and second banks B0 and B1 and the first and second low blocks. Parts F0 and F1; The first bank B0 that reads data stored in the fuses of the first and second fuses F0 and F1 and has them for each bank, and accesses the column operation of the memory cell array unit 403. Or a latch unit LH for latching and outputting data line switching information according to the second bank B1; The operation of the present invention configured as a multiplexer (MUX) for receiving a signal from the latch unit (LH) and multiplexing it will be described.

First, in the test of the memory, if the output signal of the data line switching decoder 401 is 'high', it is a normal signal and 'low' is a redundancy, so that a predetermined number of normal data lines are connected to the same number of external data lines. .

After the test, when the fail data line corresponding to the fail bit line is determined, the address is recorded in the column fuse arrays of the fuses F0 and F1.

When the fail data line is approached during operation of the memory, the redundant data line is replaced with a redundancy data line. The redundancy data line is disposed in the center to minimize the length of the normal data line and the length of the line when the redundancy data line is replaced. .

That is, the reconstruction controller 400 reads the data of the failed fuse and outputs a signal for the fail input / output line to switch the appropriate data line for each bank accessed during the column operation of the memory. The data line switching decoder 401 receives a signal for the fail input / output line from the reconstruction controller 400 and decodes the signal for outputting the data line switching information accordingly.

Then, the data line reconstruction unit 402 receives the data line switching information and switches the fail input / output line of the memory cell array unit 403 to the redundancy input / output line.

The data line switching decoder 401 can be simply configured as a NAND gate. For example, in order to switch 32 data lines, 32 NAND gates are required, and each NAND gate has 6 inputs.

That is, five outputs of the fuses F0 and F1 that store the 5-bit data lines storing the addresses of 32 data lines and one output from one drive fuse are connected to the NAND gate. Become input.

In this case, when the output of the driving fuse is low, only the normal data line is connected to the external data line regardless of the values of the fuses F0 and F1, and the repair of the fail data line is performed in the unit of low block. The low block unit refers to a unit of a memory cell array connected to a low decoder that is simultaneously driven, and when the number of redundant data lines increases, the switching transistor and the data line switching decoder of the data line reconstruction unit 402 accordingly increase. What is necessary is to increase the number of decoders and fuse arrays of 401).

In this case, the operation of the reconstruction controller 400 will be described in detail as follows.

First, the first and second fuses F0 and F1 store addresses of fail data lines for each of the first and second banks B0 and B1 and for each of the first and second low blocks. The latch portion LH reads the data stored in the fuses of the first and second fuses F0 and F1 and stores the data in the banks B0 and B1, respectively. The data line switching information is latched and output according to the first bank B0 or the second bank B1 approaching during the column operation of the unit 403, wherein the multiplexer MUX receives a signal from the latch unit LH. Receives the signal and transmits it to the data line switching decoder 401.

That is, after the row operation of each bank B0 and B1 of the memory cell array unit 403 is performed, the latch unit LH fails to fit the fail data line based on the low block selected in each of the banks B0 and B1. After the column operation occurs in each bank B0 and B1, the fail data line is repaired as a redundancy data line according to the address stored in the latch section LH. Unlike the repair method, the column address comparison process is omitted and the column operation can be speeded up because the data line is repaired by reading the address of the fail line from the latch independently of the occurrence of the column select signal.

At this time, the data of the latch unit LH is output to the data line switching decoder 401 through the 2: 1 multiplexer MUX since the bank assumes two memory cell arrays.

As described in detail above, the present invention has the effect of minimizing the chip area required for the column repair operation and reducing the delay time by replacing the fail input / output line to which the failed bit line is connected with the redundancy input / output line.

Claims (2)

A reconstruction controller that reads data of a failed fuse and outputs a signal for a fail input / output line to switch a data line suitable for each bank accessed during a column operation of the memory; A data line switching decoder which receives a signal for a fail input / output line from the reconstruction controller and decodes it; And a data line reconfiguration section for switching a fail input / output line of a memory cell array section to a redundancy input / output line in response to a decoded signal of the data line switching decoder. 2. The system of claim 1, wherein the reconstruction controller includes: a plurality of fuses for storing addresses of fail data lines for respective banks and low blocks; A plurality of latch sections for reading and storing data stored in the fuses of the plurality of fuse sections for each bank and latching and outputting data line switching information according to a bank approaching a column operation of a memory cell array section; And a multiplexer configured to receive signals from the plurality of latch units and multiplex them.