KR20090007859A - Flash memory device and repairing method thereof - Google Patents

Flash memory device and repairing method thereof Download PDF

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Publication number
KR20090007859A
KR20090007859A KR1020070071038A KR20070071038A KR20090007859A KR 20090007859 A KR20090007859 A KR 20090007859A KR 1020070071038 A KR1020070071038 A KR 1020070071038A KR 20070071038 A KR20070071038 A KR 20070071038A KR 20090007859 A KR20090007859 A KR 20090007859A
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KR
South Korea
Prior art keywords
data line
address
redundancy
block
main
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KR1020070071038A
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Korean (ko)
Inventor
김기석
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070071038A priority Critical patent/KR20090007859A/en
Publication of KR20090007859A publication Critical patent/KR20090007859A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy

Abstract

A flash memory device and a repairing method thereof are provided to improve repair efficiency of a flash memory device by performing repair operation with string unit instead of column unit. A NAND flash memory device(100) comprises a main cell array(10) and a redundancy cell array(11). The main cell array and the redundancy cell array comprise a plurality of strings. One string comprises a plurality of cells which is serially connected. A main page buffer(12a, 12b) and a main column gate(13a, 13b) are arranged in a top and a bottom of the main cell array. The main page buffer is selected by an address fuse block(17a, 17b). A redundancy page buffer(14a, 14b) and a redundancy column gate(15a, 15b) are arranged in a top and a bottom of the redundancy cell array. The redundancy page buffer is selected by the redundancy column gate. The address fuse block outputs an output signal(rYENt, rYENb) according to an external address. The output signal is transmitted to an I/O fuse block(18a, 18b) and the redundancy column gate. A block fuse part(19) determines a state of a corresponding memory block. A data line selecting part(20) connects one among a first, a third, and a fourth data lines to a second data line.

Description

Flash memory device and repair method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a repair method thereof, and to a flash memory device repairable in units of strings by selecting a redundancy data line using repair information of a block and repair information of a column address, and a repair method thereof. will be.

The semiconductor memory device does not function as a memory if any one of a large number of fine cells is defective in manufacturing, and thus is treated as a defective product. However, even though only a few cells in the memory have failed, discarding the entire device as defective is an inefficient method of processing.

At present, the yield is improved by replacing the normal unit cell in which a defect has occurred by using a spare unit cell previously installed in the memory device.

In general, a repair method of a flash memory device replaces a column sharing a bit line with a redundancy column in order to repair a single fail cell. Considering that the number of blocks that share one bit line, that is, the number of cell strings is generally 2048, the repair efficiency may be 1/2048.

As memory devices become increasingly high in capacity, process defects increase and the frequency of fail cell generation increases, requiring more redundancy columns to secure yields. As a result, device size losses increase as devices increase in capacity. .

An object of the present invention is to perform a repair operation by replacing a main data line with a redundant data line in response to an output signal of a block fuse unit having repair information of a memory block and a column repair signal selected by an external address, thereby performing a repair operation. The present invention provides a flash memory device that can be repaired as well as a repair method thereof.

Flash memory devices according to an embodiment of the present invention are disposed in the main cell array, and the first and second page buffers for transferring data through the first data line to the second data line according to the address of the main column to be repaired; Third and fourth page buffers arranged in a redundancy cell array and simultaneously selected according to the address of the main column to transfer data to the second data line through third and fourth data lines, respectively; A block fuse unit for receiving a control signal and outputting a control signal according to a repair state of the block, an I / O buffer connected to the second data line to output data transmitted to the second data line, and an address of the main column; Select one of the first, third, and fourth data lines according to the control signal output from the block fuse unit to select the second And a data line selector connected to the data line.

When the address of the main column is the same and the control signal is enabled, the third and fourth data lines are simultaneously selected through the data line selector and connected to the second data line.

When the address of the main column is different from each other and the control signal is enabled, one of the third and fourth data lines is selected through the data line selector and connected to the second data line.

The apparatus further includes first and second address fuse blocks for selecting the third and fourth page buffers according to the address of the main column, respectively.

The electronic device further includes first and second I / O fuse blocks configured to control the data line selector according to output signals of the first and second address fuse blocks. Preferably, the data line selector is a multiplexer.

The block fuse unit may be configured as a fuse or a cam cell to store repair information.

According to an embodiment of the present invention, a repair method of a flash memory device may include: determining a repair state of a block by comparing a repair address of a pre-cut block with a row address; determining a repair state of a column according to a column address; Connecting a redundancy data line and an input / output data line when the column includes a repair cell or includes a fail cell, and the block includes a repair cell or a fail cell, and the block includes the repair cell or the In the case of a normal block including no fail cell, the input / output data line and the main data line are connected.

According to an exemplary embodiment of the present invention, in response to an output signal of a block fuse having repair information of a memory block and a column repair signal selected by an external address, the main data line is replaced with a redundant data line to perform a repair operation. The repair efficiency of the flash memory device may be improved by performing the repair operation in units of string instead of.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a block diagram of a flash memory device 100 illustrated to explain a repair method of a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a NAND flash memory device 100 according to an exemplary embodiment of the present invention includes a main cell array 10 and a redundancy cell array 11. The main cell array 10 and the redundancy cell array 11 are composed of a plurality of strings, and one string is formed by connecting a plurality of cells (16 or 32) in series.

Main page buffers 12a and 12b and main column gates 13a and 13b are disposed at the top and bottom of the main cell array 10. Similarly, the redundancy page buffers 14a and 14b and the redundancy column gates 15a and 15b are disposed in the top and bottom of the redundancy cell array 11. The main page buffers 12a and 12b are selected by address fuse blocks 17a and 17b which operate according to the external address CA [0: 8]. If one of the main page buffers 12a and 12b is selected, the other is not selected.

The redundancy cell array 11 may be formed of, for example, 2N redundancy strings. In this case, 2N redundancy page buffers 14a and 14b are disposed at the top and the bottom of the redundancy cell array 11, and 2N redundancy column gates are respectively formed at the top and the bottom to correspond to the redundancy page buffers 14a and 14b. 15a, 15b) are arranged. Each redundancy page buffer 14a, 14b is a redundancy column gate 15a controlled by signals rYENt [0: N-1], rYENb [0: N-1] output from the address fuse blocks 17a, 17b. , 15b). N redundancy page buffers 14a and 14b may be disposed so that one page buffer may be connected to two strings.

In addition, the flash memory device requires the address fuse blocks 17a and 17b and the I / O fuse blocks 18a and 18b as many as the number of redundancy strings (redundancy columns) to be repaired for multi-I / O repair. The redundancy page buffers 14a and 14b are divided and arranged in the top and the bottom, as the redundancy page buffers 14a and 14b are arranged in the top and the bottom of the redundancy cell array 11.

The address fuse blocks 17a and 17b output the output signals rYENt and rYENb according to the external address CA to be repaired in the repair operation. These signals rYENt and rYENb are transmitted to the I / O fuse blocks 18a and 18b and the redundancy column gates 15a and 15b to control them.

When the output signals rYENt and rYENb are input from the address fuse blocks 17a and 17b, the I / O fuse blocks 18a and 18b output signals rIOENt and rIOENb corresponding to information on which main column is to be repaired. do.

The block fuse unit 19 determines whether the corresponding memory block includes a repair cell, a fail cell, or a normal memory block in response to a row address (RA) input from an external control signal (BF). Outputs The block fuse unit 19 outputs an output signal for determining whether a memory block includes a normal memory cell or a memory block including a fail cell or a repair cell according to a cutting state of the fuse. The block fuse unit 19 may be configured as a cam cell (code address memory) instead of a fuse. The block fuse unit 19 may store repair information in a fuse or a cam cell.

The data line selector 20 controlled by the control signals rIOENt [0: 7], rIOENb [0: 7] and the control signal BF may be configured as shown in FIG. 2 as an example. As shown in FIG. 2, the data line selector 20 is configured by as many switching units as the number of I / Os. For example, the switching unit is composed of a multiplexer (MUltipleXer, MUX), and here, eight as an example. Each multiplexer MUX0 to MUX7 selects one of the main data line mDL [0: 7] and the redundancy data lines rDLt and rDLb to be connected to the data line DL [0: 7]. . For example, when repairing, each of the multiplexers MUX0 to MUX7 connects the redundancy data line rDLt and the data line DL when the signal rIOENt and the control signal BF are enabled at the same time, and the signal rIOENb is When enabled and the control signal BF is enabled, the redundancy data line rDLb and the data line DL are connected. In addition, when the control signal BF is disabled, the main data line mDL [0: 7] and the data line DL [0: 7] are connected.

For reference, the data lines rDLt and rDLb are determined according to the number of main columns having the same address CA. For example, when there are M columns of the main cell array 10 having the same address CA, redundancy is obtained. In the block, M data lines rDLt and rDLb are required.

Hereinafter, a repair method of a flash memory device according to an exemplary embodiment of the present invention will be described.

The row address RA is input to the block fuse unit 19 from the outside. The block fuse unit 19 outputs a control signal BF by comparing the input row address RA with a pre-cut state. That is, the block fuse unit 19 determines whether the memory block corresponding to the row address RA is a memory block including a fail cell or a repair cell or a memory block composed of normal memory cells to determine a control signal BF. Output

The column address CA is simultaneously input to the top / bottom address fuse blocks 17a and 17b. At this time, the column address CA is also input to the top / bottom column decoders 16a and 16b. The top / bottom column decoders 16a and 16b decode the column address CA and output the decoded column addresses CA to the top / bottom main column gates 13a and 13b, respectively. The top / bottom main column gates 13a and 13b receive data of the main cell array 10 transmitted through the corresponding main page buffers 12a and 12b according to the decoding signals of the top / bottom column decoders 16a and 16b, respectively. It is sent to the main data line (mDL). In practice, one of the top / bottom column decoders 16a and 16b is selected to carry the data of the main cell array 10 to the main data line mDL.

On the other hand, the top / bottom address fuse blocks 17a and 17b respectively output signals rYENt and rYENb according to the column address CA. The signal rYENt is input to the top redundancy column gate 15a and the top I / O fuse block 18a, and the signal rYENb is input to the bottom redundancy column gate 15b and the top I / O fuse block 18b. do. The redundancy column gates 15a and 15b are selected according to the signals rYENt and rYENb, respectively, and carry the data transmitted through the corresponding redundancy page buffers 14a and 14b to the redundancy data lines rDLt and rDLb. For example, in the case of 2-I / O repair, the top redundancy column gate 15a and the bottomum redundancy column gate 15b are the signals rYENt and rYENb of the top address fuse block 17a and the bottomum address fuse block 17b, respectively. Are selected simultaneously. For example, a redundancy column corresponding to the main column to be repaired through the top redundancy column gate 15a is selected, and a redundancy column corresponding to another main column to be repaired through the bottom redundancy column gate 15b is selected. Therefore, two main column data to be repaired and two redundancy column data corresponding to the top redundancy data line rDLt and the bottom redundancy data line rDLb are respectively loaded.

Meanwhile, the top / bottom I / O fuse blocks 18a and 18b control signals for controlling the data line selector 20 according to the signals rYENt and rYENb of the top / bottom address fuse blocks 17a and 17b, respectively. Outputs (rIOENt, rIOENb).

The data line selector 20 supplies main data according to the signals rIOENt and rIOENb output from the top / bottom I / O fuse blocks 18a and 18b and the control signal BF output from the block fuse 19. One of the line mDL and the redundancy data lines rDL and rDLb is selected and connected to the data line DL. For example, when the control signals rIOENt and rIOENb are input at different levels and the control signal BF is enabled as shown in FIG. 2, the connection between the main data line mDL and the data line DL is blocked. do. When the control signal rIOENt is input at the high level and the control signal rIOENb is input at the low level, the top redundancy data line rDLt and the data line DL are connected to each other. On the other hand, when the control control signal rIOENt is input at the low level and the control signal rIOENb is input at the high level, the bottom redundancy data line rDLb and the data line DL are connected to each other. As a result, when the control signal rIOENt is input at a high level, the data transmitted to the top redundancy data line rDLt is transferred to the I / O buffer 21 through the data line DL, and the control signal rIOENb. Is input to the high level, the data transmitted to the bottom redundancy data line rDLb is transferred to the I / O buffer 21 through the data line DL. When the control signal BF is disabled, the main data line mDL and the data line DL are connected regardless of the control signals rIOENt and rIOENb. That is, the repair operation of the block is performed by the control signal (BF) having the repair information of the block, so that the repair operation can be performed on a column of one block, that is, on a string basis.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram showing the configuration of a NAND flash memory device according to a preferred embodiment of the present invention.

FIG. 2 is a diagram illustrating the configuration of the data line selector illustrated in FIG. 1.

<Explanation of symbols for main parts of drawing>

10: main cell array

11: redundancy cell array

12a, 12b: main page buffer

13a, 13b: main column gate

14a, 14b: redundancy page buffer

15a, 15b: redundancy column gate

16a, 16b: column decoder

17a, 17b: address fuse block

18a, 18b: I / O fuse block

19: block fuse

20: data line selector

21: I / O buffer part

22: X-decoder

Claims (8)

Comparing the repair information of the block with the row address to determine a repair status of the block; Determining a repair status of a column according to the column address; Connecting a redundancy data line and an input / output data line when the column includes a repair cell or a fail cell and the block includes a repair cell or a fail cell; And And repairing the repair cell or the normal block not including the fail cell, wherein the input / output data line and the main data line are connected to each other. First and second page buffers disposed in a main cell array and configured to transfer data through the first data line to a second data line according to an address of a main column to be repaired; Third and fourth page buffers disposed in a redundancy cell array and simultaneously selected according to the address of the main column to transfer data to the second data line through third and fourth data lines, respectively; A block fuse unit receiving a row address and outputting a control signal according to a repair state of the block; An I / O buffer connected to the second data line and outputting data transmitted to the second data line; And And a data line selector configured to select one of the first, third, and fourth data lines and connect the second data line according to an address of the main column and the control signal output from the block fuse unit. Memory elements. The method of claim 2, And the third and fourth data lines are simultaneously selected through the data line selector and connected to the second data line when the address of the main column is the same and the control signal is enabled. The method of claim 2, And the third and fourth data lines are selected through the data line selector to be connected to the second data line when the addresses of the main columns are different from each other and the control signal is enabled. The method of claim 2, And first and second address fuse blocks for selecting the third and fourth page buffers according to the address of the main column, respectively. The method of claim 5, wherein And first and second I / O fuse blocks for controlling the data line selector according to output signals of the first and second address fuse blocks. The method of claim 2, And the data line selector comprises a multiplexer. The method of claim 2, The block fuse unit may be configured of a fuse or a cam cell to store repair information.
KR1020070071038A 2007-07-16 2007-07-16 Flash memory device and repairing method thereof KR20090007859A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8625351B2 (en) 2010-12-23 2014-01-07 Samsung Electronics Co., Ltd. Nonvolatile memory devices
CN103907882A (en) * 2013-01-04 2014-07-09 广东省农业科学院蚕业与农产品加工研究所 Production method of plum juice and straw mushroom seasoning
KR20190050610A (en) * 2017-11-03 2019-05-13 삼성전자주식회사 Non-Volatile Memory device and method for repairing defective strings

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8625351B2 (en) 2010-12-23 2014-01-07 Samsung Electronics Co., Ltd. Nonvolatile memory devices
CN103907882A (en) * 2013-01-04 2014-07-09 广东省农业科学院蚕业与农产品加工研究所 Production method of plum juice and straw mushroom seasoning
KR20190050610A (en) * 2017-11-03 2019-05-13 삼성전자주식회사 Non-Volatile Memory device and method for repairing defective strings

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