KR20000026821A - Method for manufacturing register of lsi semiconductor memory - Google Patents
Method for manufacturing register of lsi semiconductor memory Download PDFInfo
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- KR20000026821A KR20000026821A KR1019980044526A KR19980044526A KR20000026821A KR 20000026821 A KR20000026821 A KR 20000026821A KR 1019980044526 A KR1019980044526 A KR 1019980044526A KR 19980044526 A KR19980044526 A KR 19980044526A KR 20000026821 A KR20000026821 A KR 20000026821A
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- peripheral region
- word lines
- cell region
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 11
- 230000002093 peripheral effect Effects 0.000 claims description 35
- 239000011229 interlayer Substances 0.000 claims description 15
- 239000010410 layer Substances 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000000206 photolithography Methods 0.000 abstract description 5
- 238000005137 deposition process Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 고집적 반도체메모리의 레지스터(resistor) 제조방법에 관한 것으로, 특히 256M 이상의 디램(DRAM)에서 플러그의 형성시에 사용되는 도핑된 폴리실리콘을 통해 공정의 추가없이 레지스터를 제조하기에 적당하도록 한 고집적 반도체메모리의 레지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a resistor of a highly integrated semiconductor memory, and in particular to a suitable for manufacturing a resistor without the addition of a process through the doped polysilicon used in the formation of plugs in DRAM (DRAM) of 256M or more. A method for manufacturing a register of a highly integrated semiconductor memory.
일반적으로, 반도체메모리의 셀 영역에 워드라인, 비트라인 또는 커패시터의 플레이트전극을 형성하기 위한 도전성 물질로 폴리실리콘이 사용되는 경우에 그 폴리실리콘을 이용하여 주변영역에 회로설계에 요구되는 레지스터를 형성하게 된다.In general, when polysilicon is used as a conductive material for forming a plate electrode of a word line, a bit line, or a capacitor in a cell region of a semiconductor memory, a resistor required for circuit design is formed in the peripheral region by using the polysilicon. Done.
종래기술의 일 예로써, 상기한 바와같은 워드라인을 이용한 레지스터 제조방법을 도1a 내지 도1e의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.As an example of the prior art, a method of manufacturing a register using the word line as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1E.
먼저, 도1a에 도시한 바와같이 반도체기판(1)상의 셀영역과 주변영역에 폴리실리콘(2)과 절연막(3)을 증착한 후, 패터닝하여 워드라인을 형성한다. 이때, 주변영역에 폴리실리콘(2)의 레지스터(10)가 형성된다.First, as shown in FIG. 1A, the polysilicon 2 and the insulating film 3 are deposited in the cell region and the peripheral region on the semiconductor substrate 1, and then patterned to form a word line. At this time, the register 10 of the polysilicon 2 is formed in the peripheral region.
그리고, 도1b에 도시한 바와같이 상기 워드라인과 레지스터(10)가 형성된 반도체기판(1)의 상부전면에 산화막(4)을 증착한 후, 이온 반응성 식각(reactive ion etching : RIE) 방법을 이용하여 상기 워드라인과 레지스터(10)의 측면에 측벽을 형성한다.As shown in FIG. 1B, an oxide film 4 is deposited on the upper surface of the semiconductor substrate 1 on which the word line and the resistor 10 are formed, and then an ion reactive etching (RIE) method is used. As a result, sidewalls are formed on side surfaces of the word line and the register 10.
그리고, 도1c에 도시한 바와같이 상기 측벽이 형성된 반도체기판(1)의 상부전면에 층간절연막(5)을 증착하여 평탄화한다.As shown in FIG. 1C, the interlayer insulating film 5 is deposited and planarized on the upper surface of the semiconductor substrate 1 on which the sidewalls are formed.
그리고, 도1d에 도시한 바와같이 상기 층간절연막(5)의 상부에 감광막(6)을 증착한 후, 노광 및 현상하여 상기 레지스터(10) 상부의 층간절연막(5)을 노출시킨다.Then, as shown in FIG. 1D, the photosensitive film 6 is deposited on the interlayer insulating film 5, and then exposed and developed to expose the interlayer insulating film 5 on the resistor 10.
그리고, 도1e에 도시한 바와같이 상기 노출된 층간절연막(5) 및 레지스터(10)의 폴리실리콘(2) 상부에 형성된 절연막(3)을 이온 반응성 식각방법을 통해 제거하여 레지스터(10)의 폴리실리콘(2)을 노출시킨 후, 상기 감광막(6)을 제거한다.As shown in FIG. 1E, the exposed interlayer insulating film 5 and the insulating film 3 formed on the polysilicon 2 of the resistor 10 are removed by an ion reactive etching method to remove the poly of the resistor 10. After exposing the silicon 2, the photosensitive film 6 is removed.
그러나, 상기한 바와같은 종래의 레지스터 제조방법은 반도체메모리가 고집적화됨에 따라 워드라인, 비트라인 또는 커패시터의 플레이트전극을 형성하기 위하여 폴리실리콘 보다 저항이 매우 낮은 도전성 물질을 사용하고 있다.However, the conventional resistor manufacturing method as described above uses a conductive material having a much lower resistance than polysilicon to form a plate electrode of a word line, a bit line, or a capacitor as the semiconductor memory is highly integrated.
따라서, 레지스터를 제조하기 위해서 별도의 폴리실리콘 증착공정 및 사진식각공정이 요구되어 공정이 복잡해지고, 제조비용이 증가하는 문제점이 있었다.Therefore, in order to manufacture a resistor, a separate polysilicon deposition process and a photolithography process are required, so that the process becomes complicated and manufacturing costs increase.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 256M 이상의 디램에서 플러그의 형성시에 사용되는 도핑된 폴리실리콘을 통해 공정의 추가없이 레지스터를 제조할 수 있는 고집적 반도체메모리의 레지스터 제조방법을 제공하는데 있다.The present invention has been devised to solve the above-mentioned conventional problems, and an object of the present invention is to manufacture a resistor without addition of a process through doped polysilicon used in the formation of a plug in a DRAM of 256M or more. The present invention provides a register manufacturing method for a highly integrated semiconductor memory.
도1은 종래 워드라인을 이용한 레지스터 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a register using a word line.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12A∼12C:워드라인11: Semiconductor substrate 12A to 12C: Word line
13A,13B:더미 워드라인 14:산화막13A, 13B: Dummy word line 14: Oxide film
15,18,23:감광막 패턴 16,21:측벽15,18,23: photosensitive film pattern 16,21: side wall
17:폴리실리콘 19:폴리플러그17: polysilicon 19: poly plug
20:레지스터 22:층간절연막20: register 22: interlayer insulating film
상기한 바와같은 본 발명의 목적을 달성하기 위한 고집적 반도체메모리의 레지스터 제조방법의 바람직한 일 실시예는 반도체기판상에 금속물질과 절연막을 증착한 후, 패터닝하여 셀영역에 서로 이격되는 다수개의 워드라인을 형성함과 아울러 주변영역에 서로 이격되는 더미(dummy) 워드라인을 형성하는 공정과; 상기 셀영역과 주변영역의 상부전면에 제1산화막을 형성한 후, 주변영역의 제1산화막 상부에 제1감광막 패턴을 형성하고, 셀영역의 제1산화막을 식각하여 셀영역의 워드라인 측면에 측벽을 형성하는 공정과; 상기 제1감광막 패턴을 제거하고, 셀영역과 주변영역의 상부전면에 폴리실리콘을 증착한 후, 에치-백(etch back)하는 공정과; 상기 셀영역과 주변영역의 상부에 제2감광막 패턴을 형성하고, 노출된 폴리실리콘을 식각하여 셀영역의 워드라인과 주변영역의 더미 워드라인 사이에 각각 폴리플러그를 형성하는 공정과; 상기 제2감광막 패턴을 제거하고, 셀영역과 주변영역의 상부전면에 제2산화막을 형성한 후, 식각하여 주변영역의 더미 워드라인 측면에 측벽을 형성하는 공정과; 상기 셀영역과 주변영역의 상부전면에 층간절연막을 형성하고, 그 층간절연막의 상부에 제3감광막 패턴을 형성한 후, 노출된 층간절연막을 식각하여 상기 주변영역의 더미 워드라인 사이에 형성된 폴리플러그를 노출시키는 공정을 구비하여 이루어짐을 특징으로 한다.One preferred embodiment of the method of manufacturing a resistor of a highly integrated semiconductor memory for achieving the object of the present invention as described above is a plurality of word lines spaced apart from each other in the cell region by depositing a metal material and an insulating film on the semiconductor substrate Forming a dummy word line spaced apart from each other in the peripheral area; After the first oxide film is formed on the upper surface of the cell region and the peripheral region, a first photoresist layer pattern is formed on the first oxide layer of the peripheral region, and the first oxide layer of the cell region is etched to the word line side of the cell region. Forming sidewalls; Removing the first photoresist pattern, depositing polysilicon on upper surfaces of the cell region and the peripheral region, and then etching back; Forming a second photoresist pattern on the cell region and the peripheral region, and etching the exposed polysilicon to form a polyplug between the word line of the cell region and the dummy word line of the peripheral region; Removing the second photoresist layer pattern, forming a second oxide layer on the upper surface of the cell region and the peripheral region, and then etching and forming sidewalls on the side of the dummy word line of the peripheral region; After forming an interlayer insulating film on the upper surface of the cell region and the peripheral region, and forming a third photoresist pattern on the interlayer insulating layer, the exposed interlayer insulating film is etched to form a polyplug formed between the dummy word lines of the peripheral region. It is characterized by consisting of a process for exposing.
상기한 바와같은 본 발명에 의한 고집적 반도체메모리의 레지스터 제조방법의 일 실시예를 도2a 내지 도2f의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.An embodiment of a method of manufacturing a register of a highly integrated semiconductor memory according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2F.
먼저, 도2a에 도시한 바와같이 반도체기판(11)상에 금속물질과 절연막을 증착한 후, 패터닝하여 셀영역에 서로 이격되는 워드라인(12A∼12C)을 형성함과 아울러 주변영역에 서로 이격되는 더미 워드라인(13A,13B)을 형성한다. 이때, 워드라인(12A∼12C)과 더미 워드라인(13A,13B)은 고집적 반도체메모리에서 요구되는 고성능(high performance)을 갖도록 하기 위하여 폴리실리콘보다 저항이 매우낮은 금속물질을 사용하여 형성한다.First, as shown in FIG. 2A, a metal material and an insulating film are deposited on the semiconductor substrate 11, and then patterned to form word lines 12A to 12C spaced apart from each other in the cell region, and spaced apart from each other in the peripheral region. Dummy word lines 13A and 13B are formed. In this case, the word lines 12A to 12C and the dummy word lines 13A and 13B are formed using a metal material having a much lower resistance than polysilicon in order to have high performance required in a highly integrated semiconductor memory.
그리고, 도2b에 도시한 바와같이 상기 셀영역과 주변영역의 상부전면에 산화막(14)을 형성한 후, 주변영역의 산화막(14) 상부에 감광막 패턴(15)을 형성하고, 셀영역의 산화막(14)을 이온 반응성 식각하여 셀영역의 워드라인(12A∼12C) 측면에 측벽(16)을 형성한다.As shown in FIG. 2B, after the oxide film 14 is formed on the upper surface of the cell region and the peripheral region, the photoresist pattern 15 is formed on the oxide film 14 of the peripheral region, and the oxide film of the cell region is formed. (14) is ion reactively etched to form sidewalls 16 on the side of the word lines 12A-12C in the cell region.
그리고, 도2c에 도시한 바와같이 상기 감광막 패턴(15)을 제거하고, 셀영역과 주변영역의 상부전면에 폴리실리콘(17)을 증착한 후, 에치-백 또는 화학기계적 연마공정(CMP)을 수행한다.As shown in FIG. 2C, the photoresist pattern 15 is removed, and polysilicon 17 is deposited on the upper surface of the cell region and the peripheral region, and then an etch-back or chemical mechanical polishing process (CMP) is performed. Perform.
그리고, 도2d에 도시한 바와같이 상기 셀영역과 주변영역의 상부에 감광막 패턴(18)을 형성하고, 노출된 폴리실리콘(17)을 식각하여 셀영역의 워드라인(12A∼12C)과 주변영역의 더미 워드라인(13A,13B) 사이에 각각 폴리플러그(19)를 형성한다. 이때, 폴리플러그(19)는 상기 측벽(16)을 통해 워드라인(12A∼12C) 및 더미 워드라인(13A,13B)과 격리되어 이후에 형성되는 층간절연막(22)상의 콘택을 통해 반도체기판(11)과 금속배선을 선택적으로 접속시키며, 상기 더미 워드라인(13A,13B) 사이에 형성된 폴리플러그(19)는 이후의 공정을 통해 레지스터(20)가 된다.As shown in FIG. 2D, the photoresist pattern 18 is formed on the cell region and the peripheral region, and the exposed polysilicon 17 is etched to etch the word lines 12A to 12C and the peripheral region of the cell region. Polyplugs 19 are formed between the dummy word lines 13A and 13B, respectively. In this case, the polyplug 19 is isolated from the word lines 12A to 12C and the dummy word lines 13A and 13B through the sidewall 16 and is formed through the contact on the interlayer insulating layer 22 formed thereafter. 11) and the metal wirings are selectively connected, and the polyplug 19 formed between the dummy word lines 13A and 13B becomes a resistor 20 through a subsequent process.
그리고, 도2e에 도시한 바와같이 상기 감광막 패턴(18)을 제거하고, 셀영역과 주변영역의 상부전면에 산화막을 형성한 후, 이온 반응성 식각하여 주변영역의 더미 워드라인(13A,13B) 측면에 측벽(21)을 형성한다.As shown in FIG. 2E, the photoresist pattern 18 is removed, an oxide film is formed on the upper surface of the cell region and the peripheral region, and then ion-reactively etched to the side of the dummy word lines 13A and 13B of the peripheral region. The side wall 21 is formed in the.
그리고, 도2f에 도시한 바와같이 상기 셀영역과 주변영역의 상부전면에 층간절연막(22)을 형성하고, 그 층간절연막(22)의 상부에 감광막 패턴(23)을 형성한 후, 노출된 층간절연막(22)을 식각하여 상기 주변영역의 더미 워드라인(13A,13B) 사이에 형성된 폴리플러그(19)의 레지스터(20)를 노출시킨다.Then, as shown in FIG. 2F, an interlayer insulating film 22 is formed on the upper surface of the cell region and the peripheral region, and a photosensitive film pattern 23 is formed on the interlayer insulating film 22, and then the exposed interlayer is formed. The insulating layer 22 is etched to expose the register 20 of the polyplug 19 formed between the dummy word lines 13A and 13B of the peripheral region.
상기한 바와같은 본 발명에 의한 고집적 반도체메모리의 레지스터 제조방법은 셀영역에 폴리플러그를 형성하는 공정이 이루어질 때, 주변영역에 레지스터를 형성함에 따라 별도의 폴리실리콘 증착공정 및 사진식각공정이 요구되지 않고도 사진식각공정에 대한 마진을 확보할 수 있어 공정 단순화 및 제조비용 절감의 효과가 있다.As described above, in the method of manufacturing a resistor of a highly integrated semiconductor memory according to the present invention, when a process of forming a poly plug in a cell region is performed, a separate polysilicon deposition process and a photolithography process are not required as a resistor is formed in a peripheral region. The margin for the photolithography process can be secured, thereby simplifying the process and reducing manufacturing costs.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980044526A KR20000026821A (en) | 1998-10-23 | 1998-10-23 | Method for manufacturing register of lsi semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980044526A KR20000026821A (en) | 1998-10-23 | 1998-10-23 | Method for manufacturing register of lsi semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000026821A true KR20000026821A (en) | 2000-05-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980044526A KR20000026821A (en) | 1998-10-23 | 1998-10-23 | Method for manufacturing register of lsi semiconductor memory |
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| Country | Link |
|---|---|
| KR (1) | KR20000026821A (en) |
-
1998
- 1998-10-23 KR KR1019980044526A patent/KR20000026821A/en not_active Application Discontinuation
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