KR20000025682A - Method for fabricating capacitor of ferroelectric ram - Google Patents
Method for fabricating capacitor of ferroelectric ram Download PDFInfo
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- KR20000025682A KR20000025682A KR1019980042845A KR19980042845A KR20000025682A KR 20000025682 A KR20000025682 A KR 20000025682A KR 1019980042845 A KR1019980042845 A KR 1019980042845A KR 19980042845 A KR19980042845 A KR 19980042845A KR 20000025682 A KR20000025682 A KR 20000025682A
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000003990 capacitor Substances 0.000 title claims abstract description 29
- 239000010408 film Substances 0.000 claims abstract description 81
- 238000005530 etching Methods 0.000 claims abstract description 53
- 239000010409 thin film Substances 0.000 claims abstract description 32
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000012790 adhesive layer Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000010410 layer Substances 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000000295 emission spectrum Methods 0.000 claims description 6
- 239000007772 electrode material Substances 0.000 claims description 5
- 239000002904 solvent Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 210000002381 plasma Anatomy 0.000 claims 8
- 238000009413 insulation Methods 0.000 abstract 2
- AVFZOVWCLRSYKC-UHFFFAOYSA-N 1-methylpyrrolidine Chemical compound CN1CCCC1 AVFZOVWCLRSYKC-UHFFFAOYSA-N 0.000 description 3
- AHVYPIQETPWLSZ-UHFFFAOYSA-N N-methyl-pyrrolidine Natural products CN1CC=CC1 AHVYPIQETPWLSZ-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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Abstract
Description
본 발명은 FeRAM의 캐패시터 제조방법에 관한 것으로서, 특히 전극물질을 하드마스크인 SiON막을 식각마스크로 사용하여 식각함으로써 식각공정시 폴리머가 발생하는 것을 방지하여 후속공정을 용이하게 실시하고 그에 따른 소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of FeRAM, in particular, by etching the electrode material using a hard mask of SiON film as an etching mask to prevent the occurrence of polymer during the etching process to facilitate the subsequent process and the characteristics of the device accordingly And a technology capable of improving reliability.
일반적으로, 반도체소자의 고집적화가 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 전하저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다. 이를 해결하기 위한 방안 중의 하나로서 높은 유전상수를 갖는 물질을 적용하려는 시도가 이루어지고 있다.In general, as the high integration of semiconductor devices increases, a fixed capacitance of a capacitor is required. In order to solve this problem, a method of using a material having a high dielectric constant of a capacitor, reducing the thickness of a dielectric film, or increasing the surface area of a charge storage electrode has emerged. In order to solve this problem, attempts have been made to apply a material having a high dielectric constant.
상기와 같이 유전상수가 높은 물질인 강유전체막은 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remainent polarization) 상태를 갖는 강유전체로 박막화하여 전원이 꺼진 상태에서도 데이타를 기억하는 비휘발성(nonvolatile)메모리인 FeRAM 소자 개발에 적용되고 있다.The ferroelectric film, which is a material having a high dielectric constant, is nonvolatile that stores data even when the power is turned off by thinning a ferroelectric film having a dielectric constant ranging from several hundreds to thousands at room temperature and having two stable polarization states. It is applied to the development of FeRAM device which is a memory.
이하, 첨부된 도면을 참고로 하여 종래기술을 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in the prior art.
도 1a 및 도 1b 는 종래기술에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a capacitor of FeRAM according to the prior art.
먼저, 소정의 하부구조물이 형성되어 있는 반도체기판(도시안됨) 상부에 저장전극 콘택(도시안됨)을 구비하는 층간절연막(11)을 형성한다.First, an interlayer insulating film 11 having a storage electrode contact (not shown) is formed on a semiconductor substrate (not shown) on which a predetermined lower structure is formed.
다음, 상기 구조 상부에 Ti 또는 TiN 막 등을 사용하여 글루레이어(도시안됨)을 형성하고, 그 상부에 Pt막이나 Ir/IrO2적층구조를 사용하여 하부전극용 박막(13)을 형성한다.Next, a glue layer (not shown) is formed on the structure by using a Ti or TiN film, and the lower electrode thin film 13 is formed on the structure using a Pt film or an Ir / IrO 2 stacked structure.
그 다음, 상기 하부전극용 박막(13) 상부에 유전막(15)과 상부전극용 박막(도시안됨)을 형성한다. 여기서, 상기 유전막(15)은 PZT막이나 SBT막을 사용하여 형성하고, 상기 상부전극용 박막은 상기 하부전극용 박막(13)과 같은 종류의 박막을 사용하여 형성한다.Next, a dielectric film 15 and an upper electrode thin film (not shown) are formed on the lower electrode thin film 13. Here, the dielectric film 15 is formed using a PZT film or an SBT film, and the upper electrode thin film is formed using the same kind of thin film as the lower electrode thin film 13.
다음, 상부전극용 마스크를 이용하여 상기 상부전극용 박막을 식각하여 상부전극(17)을 형성한다.Next, the upper electrode thin film is etched using the mask for the upper electrode to form the upper electrode 17.
그 다음, 전체표면 상부에 하부전극으로 예정되는 부분을 보호하는 감광막 패턴(19)을 형성한다. (도 1a참조)Next, a photosensitive film pattern 19 is formed on the entire surface to protect a portion of the lower electrode. (See FIG. 1A)
다음, 상기 감광막 패턴(19)을 식각마스크로 사용하여 상기 유전막(15)과 하부전극용 박막(13)을 식각한다. 상기 식각공정후 식각잔류물(21)이 식각면에 증착되어 펜스를 형성한다. (도 1b참조)Next, the dielectric layer 15 and the lower electrode thin film 13 are etched using the photoresist pattern 19 as an etching mask. After the etching process, the etching residue 21 is deposited on the etching surface to form a fence. (See FIG. 1B)
상기와 같이 종래기술에 따른 FeRAM의 캐패시터 제조방법은, 상부전극과 하부전극간의 단차에 의해 감광막이 일정한 두께로 남아 있지 않아 식각공정시 상기 상부전극이 플라즈마에 노출되어 소자의 특성에 악영향을 미치고, 식각공정후에는 식각잔류물이 펜스를 이루어 상부전극과 하부전극간에 쇼트를 유발하는 문제점이 있다.As described above, in the capacitor manufacturing method of the FeRAM according to the prior art, the photoresist film does not remain at a constant thickness due to the step between the upper electrode and the lower electrode, so that the upper electrode is exposed to the plasma during the etching process, which adversely affects the characteristics of the device. After the etching process, the etching residue forms a fence and causes a short between the upper electrode and the lower electrode.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, SiON막을 식각마스크로 사용하여 하부전극을 식각함으로써 식각공정후 식각잔류물이 식각면에 형성되어 펜스를 형성하는 것을 방지하고, 감광막을 형성하기 전에 반사방지막을 형성하는 공정이 필요하지 않고, 유전막의 열화를 방지하여 소자의 특성 및 신뢰성을 향상시키는 FeRAM의 캐패시터 제조방법을 제공하는데 그 목적이 있다.The present invention to solve the above problems of the prior art, by using the SiON film as an etching mask to etch the lower electrode to prevent the etching residue is formed on the etching surface after the etching process to form a fence, to form a photosensitive film It is an object of the present invention to provide a method of manufacturing a capacitor of FeRAM, which does not require a process of forming an anti-reflection film before, and prevents deterioration of the dielectric film to improve device characteristics and reliability.
도 1a 및 도 1b 는 종래기술에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method for manufacturing a capacitor of FeRAM according to the prior art.
도 2a 내지 도 2c 는 본 발명에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a method for manufacturing a capacitor of FeRAM according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
11, 12 : 층간절연막 13, 14 : 하부전극용 박막11, 12: interlayer insulating film 13, 14: thin film for lower electrode
15, 16 : 유전막 17, 18 : 상부전극15, 16: dielectric film 17, 18: upper electrode
19, 22 : 감광막 패턴 20 : SiON막19, 22: photosensitive film pattern 20: SiON film
21 : 식각잔류물21: etching residue
이상의 목적을 달성하기 위하여 본 발명에 따른 FeRAM의 캐패시터 제조방법은,In order to achieve the above object, a capacitor manufacturing method of FeRAM according to the present invention,
FeRAM 의 캐패시터 제조방법에 있어서,In the capacitor manufacturing method of FeRAM,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the semiconductor substrate on which a predetermined lower structure is formed;
상기 층간절연막 상부에 접착층, 하부전극용 박막 및 유전막을 형성하는 공정과,Forming an adhesive layer, a lower electrode thin film and a dielectric film on the interlayer insulating film;
상기 유전막 상부에 상부전극을 형성하는 공정과,Forming an upper electrode on the dielectric layer;
전체표면 상부에 SiON막을 형성하는 공정과,Forming a SiON film over the entire surface;
상기 SiON막 상부에 하부전극으로 예정되는 부분을 보호하는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the SiON film to protect a portion intended as a lower electrode;
상기 감광막 패턴을 식각마스크로 사용하여 상기 SiON막을 제1플라즈마식각하는 공정과,First plasma etching the SiON film using the photoresist pattern as an etching mask;
상기 감광막 패턴을 제거하는 공정과,Removing the photoresist pattern;
상기 SiON막을 식각마스크로 사용하여 상기 유전막과 하부전극용 박막을 제2플라즈마식각한 다음, 세정하는 공정을 포함하는 것을 특징으로 한다.And etching the second thin film for the dielectric film and the lower electrode using the SiON film as an etching mask, followed by cleaning.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of FeRAM according to the present invention.
먼저, 반도체기판(도시안됨) 상에 소자분리 산화막(도시안됨)과 게이트산화막(도시안됨)을 형성하고, 게이트전극(도시안됨)과 소오스/드레인전극(도시안됨)으로 구성되는 모스 전계효과 트랜지스터를 형성하고 전체표면을 평탄화시킨 후, 상기 구조 상부에 저장전극 콘택 플러그를 구비하는 층간절연막(12)을 형성한다.First, an MOS field effect transistor is formed on a semiconductor substrate (not shown), and a device isolation oxide film (not shown) and a gate oxide film (not shown) are formed and a gate electrode (not shown) and a source / drain electrode (not shown) are formed. After forming and planarizing the entire surface, an interlayer insulating film 12 having a storage electrode contact plug is formed on the structure.
다음, 상기 층간절연막(12) 상부에 Ti막으로 접착층(도시안됨)을 형성한다.Next, an adhesive layer (not shown) is formed on the interlayer insulating film 12 with a Ti film.
그 다음, 상기 접착층 상부에 하부전극용 박막(14)을 1000∼2000Å 두께로 형성하고, 상기 하부전극용 박막(14) 상부에 유전막(18)을 1000∼2000Å 두께로 형성한 후, 그 상부에 상부전극용 박막(도시안됨)을 1000∼2000Å 두께로 형성한다. 이때, 상기 하부전극용 박막(14)과 상부전극용 박막은 Pt막이나 Ir/IrO2막을 사용하고, 상기 유전막(16)은 SBT나 PZT를 사용하여 형성한다.Next, the lower electrode thin film 14 is formed to have a thickness of 1000 to 2000 micrometers on the adhesive layer, and the dielectric film 18 is formed to have a thickness of 1000 to 2000 micrometers on the lower electrode thin film 14. An upper electrode thin film (not shown) is formed to a thickness of 1000 to 2000 micrometers. In this case, the lower electrode thin film 14 and the upper electrode thin film are formed using a Pt film or an Ir / IrO 2 film, and the dielectric film 16 is formed using SBT or PZT.
다음, 상기 상부전극용 박막 상부에 상부전극으로 예정되는 부분을 보호하는 감광막 패턴(도시안됨)을 형성한 다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 상부전극용 박막을 식각하여 상부전극(18)을 형성한다. 이때, 상기 감광막 패턴은 0.4 ∼ 0.6㎛ 두께로 형성하여 식각공정후 잔류 감광막을 최소화함으로써 식각잔류물의 형성을 감소시킨다. 상기 식각공정은 Cl2와 Ar 플라즈마를 이용한 실시하고, 식각공정후에는 세정공정을 실시한다.Next, a photoresist pattern (not shown) is formed on the upper thin film for protecting the upper electrode, and the thin film for the upper electrode is etched using the photoresist pattern as an etch mask. ). In this case, the photoresist pattern is formed to a thickness of 0.4 ~ 0.6㎛ to minimize the residual photoresist after the etching process to reduce the formation of etch residues. The etching process is performed using Cl 2 and Ar plasma, and the etching process is performed after the etching process.
그 다음, 전체표면 상부에 반사방지막과 하드마스크의 역할을 하는 SiON막(20)을 1000∼2000Å 두께로 형성한다.Next, a SiON film 20 serving as an antireflection film and a hard mask is formed on the entire surface to a thickness of 1000 to 2000 Å.
다음, 상기 SiON막(20) 상부에 하부전극으로 예정되는 부분을 보호하는 감광막 패턴(22)을 형성한다. (도 2b참조)Next, a photosensitive film pattern 22 is formed on the SiON film 20 to protect a portion intended as a lower electrode. (See Figure 2b)
그 다음, 상기 감광막 패턴(22)을 식각마스크로 사용하여 상기 SiON막(20)을 식각한 후, 상기 감광막 패턴(22)을 O2플라즈마를 이용하여 제거한다. 상기 SiON막(20)의 식각공정은 CHF3, CH2F2계 플라즈마를 이용한 건식식각공정으로 F 라디칼의 발광 스펙트럼을 관찰하여 F의 농도가 급격히 증가하는 점을 식각종말점으로 검출하여 실시한다.Next, the SiON film 20 is etched using the photoresist pattern 22 as an etching mask, and then the photoresist pattern 22 is removed using an O 2 plasma. The etching process of the SiON film 20 is a dry etching process using a CHF 3 , CH 2 F 2 -based plasma to observe the emission spectrum of the F radical to detect the point where the concentration of F rapidly increases by the etching end point.
다음, 상기 식각공정시 발생된 식각잔류물을 제거하기 위하여 30 ∼ 90℃의 온도의 NMP(n-methyl pyrrolidine)계 용제에서 5 ∼ 30 분간 세정공정을 실시한다.Next, in order to remove the etching residues generated during the etching process, a washing process is performed for 5 to 30 minutes in an NMP (n-methyl pyrrolidine) solvent having a temperature of 30 to 90 ° C.
그리고, 상기 SiON막(20)을 식각마스크로 사용하여 상기 유전막(16)과 하부전극용 박막(14)을 식각한다. 상기 식각공정은 먼저 Cl2/Ar/HBr 혼합 플라즈마를 사용하여 상기 유전막(16)을 식각하되 2 ∼ 5mTorr의 압력에서 100 ∼ 300W의 바이어스 파워를 사용하여 상기 하부전극용 박막(14)과 식각선택비를 1 : 1 정도로 조절하면서 실시하고, Cl2/O2혼합플라즈마나 Cl2/Ar 혼합플라즈마를 사용하여 상기 하부전극용 박막(14)과 접착층계면에 형성된 TiOx를 식각하되 2 ∼ 10 mTorr의 압력에서 100 ∼ 500W의 바이어스 파워를 인가하여 상기 SiON막(20)과의 식각선택비를 10 : 1 이 되독록 조절하면서 실시한다. 이때, 상기 Ar의 유량은 전체가스의 70 ∼ 90%를 첨가하고, 식각공정후 상기 유전막(16)과 하부전극용 박막(14)이 80 ∼ 90。의 프로파일을 갖도록 한다.The dielectric layer 16 and the lower electrode thin film 14 are etched using the SiON layer 20 as an etching mask. In the etching process, first, the dielectric layer 16 is etched using a Cl 2 / Ar / HBr mixed plasma, but an etching selection is performed with the lower electrode thin film 14 using a bias power of 100 to 300 W at a pressure of 2 to 5 mTorr. The TiO x formed on the lower electrode thin film 14 and the adhesive layer interface is etched using a Cl 2 / O 2 mixed plasma or a Cl 2 / Ar mixed plasma, while adjusting the ratio of about 1: 1 to 2 to 10 mTorr. A bias power of 100 to 500 W is applied at a pressure of and the etching selectivity with the SiON film 20 is adjusted to 10: 1. In this case, the flow rate of Ar is added to 70 to 90% of the total gas, so that the dielectric film 16 and the lower electrode thin film 14 after the etching process has a profile of 80 ~ 90 °.
상기 식각공정시 플라즈마 내의 하부전극물질의 발광 스펙트럼이 급격히 증가할 때 1 ∼ 5%이 시간오차범위에서 상기 유전막(16)의 식각을 마치고, 감소할 때 1 ∼ 5%이 시간오차범위에서 상기 하부전극용 박막(14)의 식각공정을 마친다. 그리고, 상기 식각공정시 10 ∼ 80%의 과도식각을 실시하되, SiON막(20)이 200 ∼ 1000 Å 두께 잔류하여 상기 유전막(16)이 플라즈마에 노출되어 특성이 열화되는 것을 방지한다.When the emission spectrum of the lower electrode material in the plasma rapidly increases during the etching process, 1-5% finishes etching the dielectric film 16 in a time error range, and when the decrease decreases, 1-5% decreases the lower part in the time error range. The etching process of the electrode thin film 14 is completed. In the etching process, 10-80% of the transient etching is performed, but the SiON film 20 remains 200-1000 mm thick, thereby preventing the dielectric film 16 from being exposed to the plasma and deteriorating characteristics thereof.
다음, NMP계 용제에서 20 ∼ 40분간 세정공정을 실시하여 남아있는 식각잔류물을 모두 제거한다. (도 2c참조)Next, the cleaning process is performed for 20 to 40 minutes in an NMP solvent to remove all remaining etching residues. (See FIG. 2C)
이상에서 설명한 바와 같이 본 발명에 따른 FeRAM의 캐패시터 제조방법은, SiON막을 식각마스크로 사용하여 하부전극용 박막과 유전막을 플라즈마식각하여 식각공정시 폴리머가 발생하는 것을 방지하고, 반사방지막의 형성공정을 생략할 수 있으므로 공정을 단순하게 하여 후속공정을 용이하게 실시함으로써 소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the FeRAM capacitor manufacturing method according to the present invention, the SiON film is used as an etch mask to plasma-etch the lower electrode thin film and the dielectric film to prevent the polymer from being generated during the etching process and to form the anti-reflection film. Since the process can be omitted, the process can be simplified and the subsequent process can be easily performed, thereby improving the characteristics and reliability of the device.
Claims (16)
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| KR1019980042845A KR20000025682A (en) | 1998-10-13 | 1998-10-13 | Method for fabricating capacitor of ferroelectric ram |
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