KR100334527B1 - Method for fabricating charge storage electrode of semiconductor device - Google Patents
Method for fabricating charge storage electrode of semiconductor device Download PDFInfo
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- KR100334527B1 KR100334527B1 KR1019980000046A KR19980000046A KR100334527B1 KR 100334527 B1 KR100334527 B1 KR 100334527B1 KR 1019980000046 A KR1019980000046 A KR 1019980000046A KR 19980000046 A KR19980000046 A KR 19980000046A KR 100334527 B1 KR100334527 B1 KR 100334527B1
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000001301 oxygen Substances 0.000 claims abstract description 14
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000006884 silylation reaction Methods 0.000 abstract 4
- 239000011229 interlayer Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002091 carbon monoxide Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
본 발명은 반도체소자의 전하저장전극 형성방법에 관한 것으로서, 특히 고유전체막을 캐패시터에서 사용되는 전하저장전극인 Ru 또는 RuO2 막을 산소분위기에서 실리레이션된 감광막을 이용하여 식각함으로써 감광막과 전하저장전극의 식각선택비를 향상시켜 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a semiconductor device, and more particularly, by etching a Ru or RuO2 film, which is a charge storage electrode used in a capacitor, by using a photosensitive film that has been silized in an oxygen atmosphere. The present invention relates to a technology capable of improving selectivity and thereby improving characteristics and reliability of semiconductor devices.
일반적으로, 반도체소자의 고집적화가 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 전하저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다. 이를 해결하기 위한 방안 중의 하나로서 높은 유전상수를 갖는 물질을 적용하려는 시도가 이루어지고 있다.In general, as the high integration of semiconductor devices increases, a fixed capacitance of a capacitor is required. In order to solve this problem, a method of using a material having a high dielectric constant of a capacitor, reducing the thickness of a dielectric film, or increasing the surface area of a charge storage electrode has emerged. In order to solve this problem, attempts have been made to apply a material having a high dielectric constant.
상기와 같이 유전상수가 높은 물질 중에 하나로 PZT 또는 BST 와 같은 물질은 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remainent polarization) 상태를 갖는 강유전체로 박막화하여 비휘발성(nonvolatile) 메모리인 FeRAM(Ferroelectric RAM) 소자 개발에 적용되고 있다.As one of the materials having a high dielectric constant, a material such as PZT or BST is a nonvolatile memory that is thinned to ferroelectric having two stable residual polarization states at several hundreds to thousands of dielectric constants at room temperature. It is applied to the development of FeRAM (Ferroelectric RAM) devices.
도시되어 있지는 않지만, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 살펴보면 다음과 같다.Although not shown, looking at the capacitor manufacturing method of the semiconductor device according to the prior art as follows.
먼저, 반도체기판 상에 소자분리 산화막과 게이트산화막을 형성하고, 게이트전극과 소오스/드레인전극으로 구성되는 모스 전계효과 트랜지스터를 형성하고 전체 표면을 평탄화시킨 후, 상기 구조의 전표면에 층간절연막을 형성한다.First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, a MOS field effect transistor including a gate electrode and a source / drain electrode is formed, the entire surface is planarized, and an interlayer insulating film is formed on the entire surface of the structure. do.
그 다음, 상기 소오스/드레인전극 중 전하저장전극 컨택으로 예정되어 있는 부분 상측의 층간절연막을 제거하여 전하저장전극 컨택홀을 형성하고, 상기 컨택홀을 통하여 상기 소오스/드레인전극과 접속되는 컨택 플러그를 형성한 후, 상기 컨택 플러그의 표면에 확산방지막과 도전층의 적층구조로 저장전극을 형성하고, 저장전극 상부에 유전체막을 형성한 다음, 원하는 강유전체의 잔류분극 특성을 얻기위해 열처리공정을 실시하고, 전체표면 상부에 플레이트 전극을 형성하여 캐패시터를 완성한다.Next, a charge storage electrode contact hole is formed by removing an interlayer insulating layer on an upper portion of the source / drain electrode, which is intended as a charge storage electrode contact, and a contact plug connected to the source / drain electrode through the contact hole. After the formation, a storage electrode is formed on the surface of the contact plug with a diffusion barrier layer and a conductive layer, a dielectric film is formed on the storage electrode, and a heat treatment process is performed to obtain residual polarization characteristics of the desired ferroelectric material. A plate electrode is formed on the entire surface to complete the capacitor.
상기와 같은 종래기술에 따른 반도체소자의 캐패시터에서 유전체막으로 PZT 또는 BST 막과 같은 고유전체막들 형성하는 경우에는 전하저장전극도 기존의 다결정실리콘 대신 Ru 또는 RuO2 막과 같은 고내산화성 도전물질을 사용하여야 하는데, 이중 Ru 또는 RuO2 막은 산소분위기의 플라즈마에서 식각이 이루어진다. 그러나, 패턴 형성을 위한 마스크로 감광막을 사용하기 때문에 산소분위기에서의 식각 선택비가 높지않다. 즉, 상기 감광막은 탄소와 수소로 이루어진 유기물이기 때문에 산소와 반응하여 이탄화탄소, 일산화탄소, 수증기 등으로 휘발이 잘 이루어져 상기 Ru 또는 RuO2 막이 식각되기 전에 상기 감광막이 산소에 의해 소멸되는 문제점이 있다.In the case of forming high-k dielectric films such as PZT or BST films as dielectric films in the capacitor of the semiconductor device according to the prior art, the charge storage electrode also uses a high oxidation resistant conductive material such as Ru or RuO2 film instead of conventional polycrystalline silicon. The double Ru or RuO2 film is etched in the plasma of oxygen atmosphere. However, since the photosensitive film is used as a mask for pattern formation, the etching selectivity in the oxygen atmosphere is not high. That is, since the photoresist film is an organic material composed of carbon and hydrogen, there is a problem in that the photoresist is extinguished by oxygen before the Ru or RuO 2 film is etched due to the volatilization of carbon dioxide, carbon monoxide, water vapor, etc. by reaction with oxygen.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, Ru 또는 RuO2 막으로 전하저장전극을 형성한 다음, 실릴레이션된 감광막을 이용한 마스크 패턴을 사용하여 상기 Ru 또는 RuO2 막을 패턴닝함으로서 상기 Ru 또는 RuO2 막을 패터닝하는 동안 감광막이 손실되는 것을 방지하는 반도체소자의 전하저장전극 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the Ru or RuO2 film is formed by forming a charge storage electrode with a Ru or RuO2 film, and then patterning the Ru or RuO2 film using a mask pattern using a silicified photosensitive film. An object of the present invention is to provide a method for forming a charge storage electrode of a semiconductor device which prevents the photoresist film from being lost while patterning the film.
도 1 내지 도 3 는 본 발명의 실시예에 따른 반도체소자의 전하저장전극 형성방법을 도시한 단면도.1 to 3 are cross-sectional views illustrating a method of forming a charge storage electrode of a semiconductor device according to an embodiment of the present invention.
〈도면의 주요부분에 대한 부호 설명〉<Explanation of symbols on main parts of the drawing>
11 : 층간절연막 13 : Ru 또는 RuO2 막11: interlayer insulating film 13: Ru or RuO2 film
15 : 실리레이션용 감광막 17 : 실릴화된 감광막15: silicidation photosensitive film 17: silylated photosensitive film
19 : 실리콘 산화막19 silicon oxide film
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 전하저장전극 형성방법은,In order to achieve the above object, the charge storage electrode forming method of a semiconductor device according to the present invention,
고내산화성 도전물질을 전하저장전극으로 사용하고, 고유전막을 사용하는 캐패시터를 구비하는 반도체기판의 전하저장전극 형성방법에 있어서,In the method of forming a charge storage electrode of a semiconductor substrate using a high oxidation resistant conductive material as a charge storage electrode, and having a capacitor using a high dielectric film,
반도체기판 상부에 Ru, RuO2 또는 Pt 로 이루어지는 군으로부터 선택된 물질을 도포하여 전하저장전극용 도전막을 형성하는 공정과,Forming a conductive film for a charge storage electrode by applying a material selected from the group consisting of Ru, RuO2 or Pt on the semiconductor substrate;
상기 전하저장전극용 도전막 상에 실리레이션용 감광막을 형성하고, 상기 실리레이션용 감광막을 선택적으로 노광시키는 공정과,Forming a silicide photosensitive film on the conductive film for charge storage electrode, and selectively exposing the silicide photosensitive film;
상기 실릴레이션용 감광막의 전면에 실릴레이션 처리하는 단계와,Silylating the entire surface of the siliculation photosensitive film;
상기 실릴레이션용 감광막을 산소플라즈마로 건식현상하여 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern by dry developing the silicide photoresist with oxygen plasma;
상기 감광막 패턴을 식각마스크로 사용하여 산소 분위기 플라즈마에서 상기 전하저장전극용 도전막을 패터닝하는 공정과,Patterning the conductive film for the charge storage electrode in an oxygen atmosphere plasma by using the photoresist pattern as an etching mask;
상기 감광막 패턴을 제거하는 공정을 포함하는 것을 특징으로 한다.It characterized in that it comprises a step of removing the photosensitive film pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 및 도 3 는 본 발명에 따른 반도체소자의 전하저장전극 형성방법을 도시한 단면도이다.1 and 3 are cross-sectional views illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention.
먼저, 반도체기판(도시안됨) 상에 소자분리 산화막(도시안됨)과 게이트산화막(도시안됨)을 형성하고, 게이트전극(도시안됨)과 소오스/드레인전극(도시안됨)으로 구성되는 모스 전계효과 트랜지스터를 형성하고 전체표면을 평탄화시킨 후, 상기 구조의 전표면에 층간절연막(11)을 형성한다.First, an MOS field effect transistor is formed on a semiconductor substrate (not shown), and a device isolation oxide film (not shown) and a gate oxide film (not shown) are formed and a gate electrode (not shown) and a source / drain electrode (not shown) are formed. And the entire surface are planarized, then an interlayer insulating film 11 is formed on the entire surface of the structure.
그 다음, 상기 소오스/드레인전극 중 전하저장전극 컨택으로 예정되어 있는 부분 상측의 층간절연막(11)을 제거하여 전하저장전극 컨택홀(도시안됨)을 형성하고, 상기 컨택홀을 통하여 상기 소오스/드레인전극과 접속되는 컨택 플러그를 형성한 후, 상기 컨택 플러그의 표면에 전하저장전극을 구성하는 Ru 또는 RuO2 막(13)을 형성한다.Next, an interlayer insulating layer 11 on the upper portion of the source / drain electrode, which is intended as a charge storage electrode contact, is removed to form a charge storage electrode contact hole (not shown), and the source / drain is formed through the contact hole. After forming the contact plug to be connected to the electrode, a Ru or RuO2 film 13 constituting the charge storage electrode is formed on the surface of the contact plug.
다음, 상기 Ru 또는 RuO2 막(13) 상부에 감광막 패턴을 형성한다. 여기서, 상기 감광막 패턴은 다음과 같이 형성한다.Next, a photoresist pattern is formed on the Ru or RuO 2 film 13. Here, the photosensitive film pattern is formed as follows.
먼저, 상기 Ru 또는 RuO2 막(13) 상부에 실리레이션용 감광막(15)을 형성하고, 상기 실리레이션용 감광막(15)을 노광마스크를 사용하여 선택적으로 노광시킨 후, 베이크한다.First, a silicide photosensitive film 15 is formed on the Ru or RuO2 film 13, and the silicide photosensitive film 15 is selectively exposed using an exposure mask and then baked.
다음, 상기 실리레이션용 감광막(15)의 노광부 표면을 실리레이션 에이젼트를 사용하여 시릴화 시켜 시릴화된 감광막(17)을 형성한다.Next, the surface of the exposed portion of the silicide photosensitive film 15 is cyrilized using a silicide agent to form a silylized photosensitive film 17.
그 다음, 산소플라즈마를 이용한 건식현상(dry development) 공정을 실시하면, 상기 시릴화된 감광막(17) 상부에는 실리콘 산화막(19)이 형성되어 산소플라즈마에 내성을 갖게 되고, 상기 실리레이션용 감광막(15)의 비노광부는 제거되어 감광막(15) 패턴이 형성된다. (도 1참조)Then, when a dry development process using an oxygen plasma is performed, a silicon oxide film 19 is formed on the silylated photoresist film 17 to become resistant to oxygen plasma, and the photoresist film for silicidation ( The non-exposed part of 15 is removed to form a photosensitive film 15 pattern. (See Fig. 1)
그리고, 상기 감광막 패턴을 식각마스크로 사용하여 상기 Ru 또는 RuO2 막(13)을 패터닝한다. (도 2참조)Then, the Ru or RuO 2 film 13 is patterned using the photoresist pattern as an etching mask. (See Fig. 2)
다음, 상기 남아 있는 실리레이션용 감광막(15) 및 시릴화된 감광막(17)은 비.오.이.(bufferde oxide etchant, 이하 BOE 라 함) 용액 또는 HF 용액을 사용한 습식식각방법으로 제거하고, 상기 실리콘 산화막(19)는 황산(H2SO4)용액/과수(H2O2)용액의 혼합용액을 사용한 습식식각방법으로 제거함으로써 Ru 또는 RuO2 막(13)으로 구성된 전하저장전극을 형성한다. (도 3참조)Next, the remaining silicide photosensitive film 15 and the silylated photosensitive film 17 are removed by a wet etching method using a buffer oxide etchant (hereinafter referred to as BOE) solution or HF solution. The silicon oxide film 19 is removed by a wet etching method using a mixed solution of sulfuric acid (H 2 SO 4) solution / fruit tree (H 2 O 2) solution to form a charge storage electrode composed of a Ru or RuO 2 film 13. (See Fig. 3)
한편, 상기와 같은 방법은 패턴형성이 어려운 Pt 막 식각공정에도 적용할 수 있다. 여기서, 상기 Pt 막을 식각하는 공정을 실시할 때 식각가스에 산소를 첨가하여 진행한다.On the other hand, the above method can be applied to the Pt film etching process difficult to form a pattern. In this case, when the Pt film is etched, oxygen is added to the etching gas.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 전하저장전극 형성방법은, PZT 또는 BST 막을 고유전체막으로 사용하는 캐패시터는 전하저장전극을 Ru 또는 RuO2 막을 사용하는데 이를 실릴레이션된 감광막을 식각마스크로 사용하여 패터닝함으로써 상기 감광막 패턴과 상기 Ru 또는 RuO2 막과의 식각선택비를 높여 상기 전하저장전극 패터닝시 감광막이 소멸되는 것을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of forming the charge storage electrode of the semiconductor device according to the present invention, the capacitor using the PZT or BST film as the high-k dielectric film uses the Ru or RuO2 film as the charge storage electrode. By using the patterning method, an etch selectivity between the photoresist pattern and the Ru or RuO2 film is increased, thereby preventing the photoresist from disappearing during patterning of the charge storage electrode, thereby improving characteristics and reliability of the semiconductor device.
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