JPH1174481A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form fine storage contact holes and a storage node pattern with high accuracy. SOLUTION: On a semiconductor substrate 1 on which an interlayer insulating film 6, a bit contact and bit lines 7-b are formed on transistors, an oxide film 8 and a BPSG film 9 are formed and flattened, and a mask pattern 10 composed of a nitride film is formed on the film 9. Then, another BPSG film 12 is formed on the mask pattern 10 and, after the film 12 is flattened and a resist pattern is formed on the film 12, the film 12 is etched by using the resist pattern as a mask. After the film 12 is etched, the BPSG film 9, oxide film 8, and insulating layer 6 are successively etched. Then, after a polycrystalline silicon film 15 and an oxide film 16 are formed on the entire surface, the films 15 and 16 are subjected to a CMP(chemical mechanical polishing) treatment until the BPSG film 12 is exposed. Thereafter, the films 12 and 16 are removed and dielectric films are formed on storage node electrodes 15. In addition, cell plate electrodes are formed on the dielectric films.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for processing a storage node contact hole and a storage node electrode in a method for manufacturing a DRAM semiconductor device.

[0002]

2. Description of the Related Art As a prior art, Japanese Patent Laid-Open No. 6-15174 is known.
No. 8, Japanese Patent Application Laid-Open No. Hei 6-21393, and a method for manufacturing a capacitor electrode. JP-A-6-
In the manufacturing method described in JP-A-151748, a polycrystalline silicon 111 is deposited on an oxide film 116, an oxide film 112 is deposited thereon, and the oxide film 112 is anisotropically etched to form a trapezoidal support 112a. And the polycrystalline silicon 111 is etched using the support 112a as a mask to form the bottom electrode 111a.

Next, a polycrystalline silicon 113 is deposited, and a cylindrical electrode 113a is formed by anisotropic etching. Next, the support 112a and the oxide film 1 are etched by the etching.
16 is removed.

In the manufacturing method described in Japanese Patent Application Laid-Open No. Hei 6-21393, a silicon nitride film 20 is formed on interlayer insulating films 7 and 9, and a contact is made with the interlayer insulating films 7 and 9 and the silicon nitride film 20. A hole 10 is formed, a polycrystalline silicon 21 and an oxide film 22 are sequentially formed, and these are patterned to form a lower electrode 23.

[0005]

Problems to be Solved by the Invention Japanese Patent Application Laid-Open No. Hei 6-15174
In the manufacturing method described in Japanese Patent Publication No. 8, as the size of the storage node contact becomes smaller due to miniaturization, an abnormality occurs in which the capacitor lower electrode falls down during drying with a spin dryer or the like during wet etching,
This was causing the yield to drop.

In the method of manufacturing a capacitor electrode as disclosed in Japanese Patent Application Laid-Open No. Hei 6-21393, it is possible to manufacture a high-capacity capacitor electrode, but there is a problem that miniaturization cannot be performed.

In the conventional method of manufacturing a semiconductor device, when a contact hole having a dimension of 0.25 μm or less is formed by dry etching, if the aspect ratio of the contact hole is large, a resist having a thickness of about 1 μm is used as a mask. Must be used. Then, the resolution of the resist is not good, or the resist pattern is reduced due to insufficient etching selectivity between the resist pattern and the insulating film as a material to be etched, and a contact hole having a good shape is formed. There was a problem that it could not be formed.

It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a fine storage contact hole and a storage node pattern with high precision.

[0009]

A method of manufacturing a semiconductor device according to the present invention comprises a gate insulating film, a gate electrode on the gate insulating film, a cap insulating film on the gate electrode, and a sidewall insulating film on the side surface of the gate electrode. A first step of forming a first interlayer insulating film on a semiconductor substrate on which a transistor including a pair of diffusion layers is formed, and after the first step,
Forming a first contact hole in the first interlayer insulating film; and forming one of the pair of diffusion layers on the first interlayer insulating film via the first contact hole. A third step of forming a bit line electrically connected to the diffusion layer, and after the third step, a fourth step of forming a second interlayer insulating film on the semiconductor substrate, A fifth step of forming a mask film different from the first and second interlayer insulating films on the interlayer insulating film, a sixth step of patterning the mask film by etching, After the step, a seventh step of forming a third interlayer insulating film different from the mask film on the semiconductor substrate, an eighth step of forming a resist pattern on the third interlayer insulating film, Using the resist pattern and the mask film as a mask, the first, second A ninth step of etching the third interlayer insulating film, and after the ninth step, a tenth step of forming a first polycrystalline silicon film on the semiconductor substrate; and An eleventh step of polishing the first polycrystalline silicon film so that an insulating film is exposed and processing the first polycrystalline silicon film into a storage node electrode shape, and after the eleventh step, A twelfth step of removing the third interlayer insulating film.

Another feature of the present invention is that
After the twelfth step, a thirteenth step of forming a dielectric film on the semiconductor substrate, and a fourteenth step of forming a second polycrystalline silicon film on the dielectric film And a fifteenth step of processing the second polycrystalline silicon film into a cell plate electrode shape.

In another feature of the present invention, the mask film is a silicon nitride film.

Another feature of the present invention is that, after the tenth step, the method further includes a step of forming a fourth insulating film on the first polycrystalline silicon film. In one step, the fourth insulating film and the first polycrystalline silicon film are polished so that the third interlayer insulating film is exposed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. This embodiment is an embodiment in which the present invention is applied to formation of a contact hole and a metal wiring of a highly integrated semiconductor device.

Referring to FIG. 1A, a known technique is used to form an element isolation region 2 by a field shield method on a semiconductor substrate 1 in which a necessary impurity is previously introduced into a necessary region near a main surface. After that, a gate insulating film, a gate wiring 3,
A cap insulating film and sidewalls 4 are formed.

Next, a diffusion layer is formed by known ion implantation. Next, a polysilicon film 5 is formed, and a polysilicon pad 5 that covers the active region on the semiconductor substrate 1 and overlaps the element isolation region 2 and the gate wiring 3 is formed.

Next, the BPSG film 6 is grown, reflowed and planarized, the BPSG film 6 is opened so that the poly pad 5 is exposed, and a bit contact 7-a is formed there. Form -b.

Next, as shown in FIG. 1B, a silicon oxide film 8 having a thickness of 1000.degree.
And then grows a 4000 mm thick BPSG film 9
After the reflow, the surface of the BPSG film 9 is cleaned by a known CMP (Chemical M
The surface is removed by 2000 to 3000 degrees by the mechanical polishing (polishing) method.

In FIG. 2, a silicon nitride film 10 having a thickness of 500 ° is grown on the BPSG film 9 by a low pressure chemical vapor deposition method, and an anti-reflection film and a chemically amplified resist (not shown) are applied on the silicon nitride film 10. Then, exposure and development are performed using a known KrF excimer laser beam lithography technique to form a mask pattern of the storage node contact hole, and the silicon nitride film 10 is dry-etched using this mask pattern as a mask to open the BPSG film 9. A mask 11 for the storage node contact hole is formed.

Here, the antireflection film is used for the purpose of preventing the standing wave effect of the chemically amplified resist at the time of exposure and preventing the loss of acid in the chemically amplified resist by the silicon nitride film. Improve controllability and prevent poor resolution.

Next, as shown in FIG.
The BPSG film 12 is grown and reflowed to a thickness of 00 °, and then a novolak type resist (not shown) is applied, and exposure and development are performed using i-line lithography to form a mask pattern for a capacitor lower electrode (not shown) on the BPSG film 12. I do.

Using the mask pattern as a mask, the BPSG film 12 is removed by dry etching,
The capacitor lower electrode pattern 13 is formed by using the silicon nitride film 10 as an etching stopper film, and the silicon nitride film 1 in the capacitor lower electrode pattern 13 is previously formed.
In the portion where the mask 11 of the storage node contact hole 14 is formed by removing 0, the BPSG film 9, the silicon oxide film 8 and the BPSG film 6 are continuously etched using the silicon nitride film 10 as a mask, and the semiconductor A storage node contact hole 14 connected to the substrate 1 is formed.

In the dry etching of a silicon oxide film such as a BPSG film, a CF-based gas is used. Otherwise, the selection ratio is not good.

According to our experiments, in order to obtain a selectivity between a silicon oxide film and a silicon nitride film, a CF film is deposited as an etching protection film on a silicon nitride film by mixing a CO gas with an etching gas. Selectivity 1
About 7 could be realized.

Next, as shown in FIG. 3B, a polysilicon film 15 having a thickness of 1500 ° and a silicon oxide film 16 having a thickness of approximately 1500 ° are grown by a low pressure chemical vapor deposition method.
Silicon oxide film 1 until the BPSG film 12 is exposed
6. The polysilicon film 15 is polished and removed.

The silicon oxide film 16 is a polysilicon film 1 serving as a capacitor lower electrode in the capacitor lower electrode pattern 13 which is not mechanically polished without contact during CMP polishing.
5 is used to prevent chemical etching with a chemical polishing agent.

Next, the BPSG film 12 and the silicon oxide film 16 are removed by wet etching with a buffered hydrofluoric acid solution.
As shown in FIG. 4A, a capacitor lower electrode 15 is formed. Thereafter, as shown in FIG. 4B, an ONO film 19 serving as a capacitor dielectric film and a capacitor upper electrode 20 were formed to realize a capacitor electrode.

[0027]

As described above, according to the present invention,
The nitride film is used as an etching mask for forming the storage node contact hole, and the lower electrode pattern of the capacitor and the storage node contact hole are collectively formed to improve the dry etching resistance and resolution of the photoresist. Instead, a fine storage node contact hole can be formed with high precision while maintaining the number of steps as before.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation region 3 gate wiring 4 side wall 5 pad 6 BPSG film 7-a bit contact 7-b bit wiring 8 silicon oxide film 9 BPSG film 10 silicon nitride film mask 12 BPSG film 13 capacitor lower electrode pattern 14 storage Node contact hole 15 Polysilicon film (capacitor lower electrode) 16 Silicon oxide film 19 ONO film 20 Capacitor upper electrode

Claims (4)

[Claims] A semiconductor substrate on which a transistor including a gate insulating film, a gate electrode on the gate insulating film, a cap insulating film on the gate electrode, a sidewall insulating film on a side surface of the gate electrode, and a pair of diffusion layers is formed. A first step of forming a first interlayer insulating film thereon; a second step of forming a first contact hole in the first interlayer insulating film after the first step; Forming a bit line electrically connected to one of the pair of diffusion layers through the first contact hole on the interlayer insulating film; and the third step. Thereafter, a fourth step of forming a second interlayer insulating film on the semiconductor substrate, and forming a mask film different from the first and second interlayer insulating films on the second interlayer insulating film A fifth step, and etching the mask film by etching. A sixth step of turning, and after the sixth step, a seventh step of forming a third interlayer insulating film different from the mask film on the semiconductor substrate, and on the third interlayer insulating film, An eighth step of forming a resist pattern, a ninth step of etching the first, second, and third interlayer insulating films using the resist pattern and the mask film as a mask; and A tenth step of forming a first polycrystalline silicon film on the semiconductor substrate after the step, and polishing the first polycrystalline silicon film so that the third interlayer insulating film is exposed. An eleventh step of processing one polycrystalline silicon film into a storage node electrode shape, and a twelfth step of removing the third interlayer insulating film after the eleventh step. Manufacturing method of a semiconductor device. 2. A thirteenth step of forming a dielectric film on the semiconductor substrate after the twelfth step, and a second step of forming a second polycrystalline silicon film on the dielectric film. The method according to claim 1, further comprising: a fourteenth step; and a fifteenth step of processing the second polycrystalline silicon film into a cell plate electrode shape. 3. The method according to claim 1, wherein the mask film is a silicon nitride film. 4. The method according to claim 1, further comprising, after the tenth step, a step of forming a fourth insulating film on the first polycrystalline silicon film, wherein in the eleventh step, the third interlayer insulating film is formed. The method according to claim 1, wherein the fourth insulating film and the first polycrystalline silicon film are polished so that the film is exposed.