KR100358149B1 - Method for forming FeRAM by using plasma treatment for recovering degradation of ferroelectric capacitor - Google Patents

Abstract

The present invention relates to a method of fabricating a ferroelectric memory device that restores deterioration of a ferroelectric capacitor by using a plasma process that is applicable even after forming a metal film, and is characterized in recovering deterioration of a ferroelectric capacitor generated after metal film etching using a plasma process have. That is, according to the present invention, a plasma process is performed in a downstream apparatus in which a plasma generation region and a process progress region are distinguished from each other to prevent high-energy charged particles from reaching a semiconductor substrate, and ultraviolet rays in a plasma reach a substrate, Hole pair in the ferroelectric film, and the electron-hole pairs thus formed serve to neutralize the charge fixed on the domain interface, thereby smoothly moving the domain wall, thereby restoring deterioration of the ferroelectric capacitor.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a ferroelectric memory device for recovering degradation of a ferroelectric capacitor using a plasma process,

The present invention relates to a ferroelectric memory device manufacturing field, and more particularly, to a ferroelectric memory device manufacturing method for recovering deterioration of a ferroelectric capacitor by using a plasma process applicable even after forming a metal film.

2. Description of the Related Art Development of a device capable of overcoming the refresh limit required in conventional dynamic random access memory (DRAM) devices and utilizing a large memory capacity has been proceeded by using a ferroelectric material in a capacitor in a semiconductor memory device. Ferroelectric random access memory (FeRAM) is a kind of nonvolatile memory device. It has the advantage of storing the stored information even when the power is off, and the operating speed is also attracting attention as a next generation memory device comparable to the conventional DRAM.

As the storage material of FeRAM, Sr _i Bi _j Ta ₂ O ₉ (hereinafter referred to as SBT) and Pb (Zr, Ti) O ₃ (hereinafter referred to as PZT) thin films are mainly used. The ferroelectric has a dielectric constant ranging from several hundreds to several thousands at room temperature and has two stable remnant polarization states, which are thinned to realize application as a nonvolatile memory device. The nonvolatile memory device using the ferroelectric thin film uses a principle of controlling the polarization direction in the direction of the applied electric field and storing the digital signals 1 and 0 according to the direction of the residual polarization when the electric field is removed .

In order to put the FeRAM into practical use, the characteristics of the capacitor must be maintained even after the passivation layer forming process. If deterioration of the capacitor occurs before the metal wiring formation process, the capacitor characteristics deteriorated by the heat treatment can be recovered. However, due to the characteristics of the metal film, the heat treatment process can not be performed after the metal wiring formation process.

Therefore, when the capacitor is deteriorated after the metal wiring forming process, it is difficult to secure good electrical characteristics of the device.

A method of manufacturing a FeRAM device according to the related art will be described in detail with reference to FIGS. 1A to 1D.

1A shows a semiconductor device in which a field oxide film 11 for isolating a device and a semiconductor substrate 10 on which a transistor (CMOS transistor) composed of a gate insulating film 12, a gate electrode 13 and an active region 14 have been formed A contact hole is formed in the first interlayer insulating film 15 and a bit line 16 connected to the active region 14 of the transistor is formed through the contact hole. The second interlayer insulating film 17 and the passivation oxide film 18 are formed on the second interlayer insulating film 17. The CMOS transistor forming process shown in FIG. 1B is generally used in a DRAM manufacturing process, and is generally referred to as a front-end process.

1B shows an example in which an adhesive layer 19 for improving bonding between the lower electrode and the passivation oxide film 18 is formed on the semiconductor substrate 10 having completed the front-end process as described above, and the lower electrode film 20, The ferroelectric film 21 and the upper electrode film 22 are stacked and the capacitor is formed by selectively etching the plasma.

1C, a third interlayer insulating film 23 is formed on the entire structure in which the capacitor is formed, and a first contact hole C1 (see FIG. 1C) for exposing the capacitor upper electrode film 22 by selectively etching the third interlayer insulating film 23, The first diffusion preventing film 24 is formed in contact with the upper electrode 22 through the first contact hole C1 and the third interlayer insulating film 23 and the passivation oxide film 18 are formed, The second interlayer insulating film 17 and the first interlayer insulating film 15 are selectively etched to form the second contact hole C2 exposing the active region 14 of the transistor.

1D shows a structure in which a second diffusion preventing film 25 and a metal film 26 are formed on the entire structure and a metal film 26 and a second diffusion preventing film 25 are selectively plasma etched to form an upper electrode And a metal wiring connecting the active region 22 of the transistor and the active region 14 of the transistor is formed.

In the above-described conventional FeRAM device fabrication process, the deterioration of the capacitor occurring before the formation of the first diffusion prevention film 24 shown in FIG. 1C can be recovered by the high temperature heat treatment process at 700 ° C. or more. However, the deterioration of the capacitor that occurs after the formation of the first diffusion prevention film 24 can not be recovered by the heat treatment process. In other words, if the first diffusion prevention film 24 is formed of TiN, for example, a phase transition occurs when the temperature is 400 ° C or more in an oxygen atmosphere, thereby acting as a diffusion barrier The high temperature heat treatment can not be performed.

Since the deterioration of the capacitor after the metal film etching can not be recovered by the high temperature heat treatment, the recovery heat treatment is performed at a relatively low temperature of 400 ° C in some cases, but the deteriorated capacitor characteristics It is difficult to make.

The conventional technique of recovering the deteriorated ferroelectric capacitor characteristics by the heat treatment method as described above can not be applied after forming the metal film and it is difficult to recover deterioration of the ferroelectric capacitor caused by the metal film etching process or the like.

It is another object of the present invention to provide a method of recovering deterioration of a ferroelectric capacitor by using a plasma process applicable even after forming a metal film.

FIGS. 1A to 1D are cross-sectional views of a conventional FeRAM device manufacturing process,

FIGS. 2A to 2E are sectional views of a manufacturing process of a FeRAM device according to an embodiment of the present invention,

FIGS. 3A and 3B are graphs showing a polarization hysteresis curve before and after the plasma treatment according to the present invention. FIG.

DESCRIPTION OF THE RELATED ART [0002]

40: lower electrode film 41: ferroelectric film

42: upper electrode film 44: first diffusion barrier film

45: second diffusion preventing film 46: metal film

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a ferroelectric capacitor by stacking a lower electrode, a ferroelectric film, and an upper electrode on a semiconductor substrate having a lower structure including a transistor formed thereon; Forming a metal interconnection connecting the transistor and the ferroelectric capacitor; And recovering characteristic deterioration of the ferroelectric material generated in the step of forming the metal interconnection by performing a plasma treatment in an apparatus for diffusing a plasma from a plasma generating region to a process progressing region .

The present invention is characterized in that the deterioration of the ferroelectric capacitor generated after the metal film etching is recovered by using a plasma treatment. That is, a charged particle fixed at a domain interface or a grain boundary is removed by plasma treatment to restore deterioration of the capacitor.

In the plasma etching process, ions and electrons in the plasma strike the substrate with high energy. Also, the radiation of the plasma damages the ferroelectric. In micro-scale, the damage of ferroelectric is caused by diffusion of ions and electrons generated by plasma or electrons generated by spinning into the capacitor and fixed to the interface or grain boundary of the domain and domain of the ferroelectric. Thereby interfering with the motion of the domain wall and causing deterioration of the capacitor.

Therefore, the present invention can provide a plasma processing apparatus and a plasma processing method that can perform plasma processing in a downstream apparatus in which a plasma generation region and a process progress region are separated, thereby preventing high-energy charged particles from reaching a semiconductor substrate, Hole pairs in the ferroelectric film by ultraviolet rays reaching the substrate and neutralizing the charges fixed on the domain interface by the pair of electrons and holes formed as described above to smooth the motion of the domain wall, thereby deteriorating the deterioration of the ferroelectric capacitor .

A method of manufacturing a FeRAM device according to the related art will be described in detail with reference to FIGS. 2A to 2E.

First, as shown in FIG. 2A, a field oxide film 31 for isolating elements and a semiconductor substrate 30 (a gate electrode) are formed on which a transistor (CMOS transistor) composed of a gate insulating film 32, a gate electrode 33 and an active region 34 has been formed A bit line 36 connected to the active region 34 of the transistor is formed through the contact hole and then the bit line 36 is formed in the first interlayer insulating film 35, A front-end process is performed in which the second interlayer insulating film 37 and the passivation oxide film 38 are formed on the entire structure.

Next, as shown in FIG. 2B, an adhesive layer 39 for improving bonding between the lower electrode and the passivation oxide layer 38 is formed on the semiconductor substrate 30 having completed the front-end process as described above, The electrode film 40, the ferroelectric film 41, and the upper electrode film 42 are laminated and selectively etched by plasma to form a capacitor. The lower electrode film 40 and the upper electrode film 42 may be formed of at least one material selected from the group consisting of Pt, Ir, Ru, IrO _2, and RuO ₂ , and the ferroelectric film 41, the perovskite (perovskite) Pb (Zr, Ti ) of the structure _{O 3, (Pb, La)} (Zr, Ti) O 3, layered perovskite (layered-perovskite) structure of BiSr ₂ Ta ₂ O _9, BiSr ₂ (Ta, Nb) ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ , or (Bi, La) ₄ Ti ₃ O ₁₂ .

Next, as shown in FIG. 2C, a third interlayer insulating film 43 is formed on the entire structure in which the capacitor is formed, and the third interlayer insulating film 43 is selectively etched to expose the capacitor upper electrode film 42 A first diffusion preventing film 44 pattern is formed in contact with the upper electrode 42 through the first contact hole C1 after forming the first contact hole C1 and the third interlayer insulating film 43, The passivation oxide film 38, the second interlayer insulating film 37 and the first interlayer insulating film 35 are selectively etched to form a second contact hole C2 exposing the active region 34 of the transistor.

Next, as shown in FIG. 2D, a second diffusion preventing film 45 and a metal film 46 are formed on the entire structure, and the metal film 46 and the second diffusion preventing film 45 are selectively plasma- And forms a metal wiring connecting the upper electrode 42 used as a node and the active region 34 of the transistor.

Next, as shown in FIG. 2E, a plasma treatment is performed to recover the ferroelectric characteristic deteriorated in the etching process for forming the metal wiring. At this time, the plasma treatment may be performed by using a mixed gas of O ₂ and N ₂ or a mixed gas of Ar, Cl ₂ , He, CF ₄ , and H ₂ (mixed gas) in the microwave or radio frequency O, CHF ₃ , and NH ₃ gas at a flow rate of 20 sccm to 5000 sccm, applying a source power of 200 W to 4000 W, applying a pressure of 0.1 torr to 100 torr, The temperature is 20 to 300 DEG C for 30 to 300 seconds. Unlike a plasma generation apparatus generally used in etching, a downstream type apparatus is divided into a plasma generation region and a process progress region, and the plasma generated in the plasma generation region is diffused downstream in the process region. During diffusion, most charge carriers such as ions and electrons almost disappear and a small amount of charge carriers, oxygen and nitrogen radicals are mainly reached on the semiconductor substrate, and ultraviolet light is irradiated on the substrate. In other words, unlike in a conventional etching apparatus, a small amount of low-energy charge carriers delivered by a downstream-type plasma does not cause damage to the capacitor even if it hits the wafer surface, and neutralizes the charge fixed on the domain interface It plays a role. Therefore, when the plasma process is performed for a predetermined time with the plasma diffused in the downstream mode, the characteristics of the degraded capacitor can be recovered.

The plasma treatment should be performed without applying a bias power. This is because, when bias power is applied, high-energy charge carriers strike the surface of the wafer to increase the deterioration of the ferroelectric capacitor.

On the other hand, the plasma treatment may be performed in a chamber for removing the photoresist pattern used as an etching mask in the formation of the metal wiring.

FIG. 3A shows a polarization hysteresis curve after the etching process for forming a metal wiring as shown in FIG. 2D, and FIG. 3B shows a polarization hysteresis curve after plasma treatment as shown in FIG. 2E. 3A and 3B, it can be seen that the polarization characteristic of the ferroelectric capacitor is improved by the plasma treatment according to the present invention.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art.

According to the present invention as described above, the characteristics of the ferroelectric capacitor can be restored without a high-temperature heat treatment process at 700 ° C or higher. Thereby ensuring excellent capacitor characteristics even after the metal film etching process, so that not only the production yield can be increased but also the reliability of the device can be improved.

Claims (7)

delete delete In a ferroelectric memory device manufacturing method, Forming a ferroelectric capacitor by stacking a lower electrode, a ferroelectric film, and an upper electrode on a semiconductor substrate on which a substructure including a transistor is formed; Forming a metal interconnection connecting the transistor and the ferroelectric capacitor; And Performing a plasma treatment in an apparatus for diffusing a plasma from a plasma generation region to a process progress region to recover the characteristic deterioration of the ferroelectric substance generated in the step of forming the metal interconnection Wherein the ferroelectric memory device is a ferroelectric memory device. The method of claim 3, The plasma processing may include: And in a device for diffusing a plasma from the plasma generating region to the process progressing region by a downstream method. 5. The method of claim 4, The plasma processing may include: Wherein the ferroelectric memory device is implemented in an apparatus of a microwave or radio frequency (RF) downstream system. 5. The method of claim 4, The plasma processing may include: A gas mixture of O ₂ and N ₂ or a gas obtained by further mixing at least one of Ar, Cl ₂ , He, CF ₄ , H ₂ O, CHF ₃ and NH ₃ gas is used for the mixed gas Wherein the ferroelectric memory device is a ferroelectric memory device. 5. The method of claim 4, The plasma processing may include: Wherein the ferroelectric memory device is carried out in a state in which the source power is applied and the bias power is not applied.