KR20000026631A - Method for manufacturing capacitor of ferroelectric ram - Google Patents
Method for manufacturing capacitor of ferroelectric ram Download PDFInfo
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- KR20000026631A KR20000026631A KR1019980044245A KR19980044245A KR20000026631A KR 20000026631 A KR20000026631 A KR 20000026631A KR 1019980044245 A KR1019980044245 A KR 1019980044245A KR 19980044245 A KR19980044245 A KR 19980044245A KR 20000026631 A KR20000026631 A KR 20000026631A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000012790 adhesive layer Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000004380 ashing Methods 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 13
- 239000007789 gas Substances 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- -1 argon ions Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 FeRAM의 캐패시터 제조방법에 관한 것으로서, 특히 하부 절연기판 상부에 접착층과 하부전극용 Pt막을 형성한 다음, 상기 하부전극용 Pt막 상부에 전하저장전극으로 예정되는 부분을 보호하는 감광막 패턴을 형성한 후, RIE 플라즈마 소오스를 사용하여 상기 감광막 패턴을 소정 두께 제거하여 높이를 낮춤으로써 후속 식각공정시 상기 감광막 패턴의 측벽에 상기 Pt막의 식각잔류물로 형성되는 펜스의 높이를 낮추어 후속 공정을 용이하게 하고 그에 따른 소자의 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of FeRAM, and in particular, to form an adhesive layer and a lower electrode Pt film on the lower insulating substrate, and then to protect the portion intended as a charge storage electrode on the lower electrode Pt film. After forming, by lowering the height by removing a predetermined thickness of the photoresist pattern by using a RIE plasma source to lower the height of the fence formed of the etching residue of the Pt film on the sidewall of the photoresist pattern during the subsequent etching process to facilitate the subsequent process To improve the characteristics and reliability of the device accordingly.
일반적으로, 반도체소자의 고집적화가 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 전하저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다. 이를 해결하기 위한 방안 중의 하나로서 높은 유전상수를 갖는 물질을 적용하려는 시도가 이루어지고 있다.In general, as the high integration of semiconductor devices increases, a fixed capacitance of a capacitor is required. In order to solve this problem, a method of using a material having a high dielectric constant of a capacitor, reducing the thickness of a dielectric film, or increasing the surface area of a charge storage electrode has emerged. In order to solve this problem, attempts have been made to apply a material having a high dielectric constant.
상기와 같이 유전상수가 높은 물질인 강유전체막은 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remainent polarization) 상태를 갖는 강유전체로 박막화하여 전원이 꺼진 상태에서도 데이타를 기억하는 비휘발성(nonvolatile)메모리인 FeRAM 소자 개발에 적용되고 있다.The ferroelectric film, which is a material having a high dielectric constant, is nonvolatile that stores data even when the power is turned off by thinning a ferroelectric film having a dielectric constant ranging from several hundreds to thousands at room temperature and having two stable polarization states. It is applied to the development of FeRAM device which is a memory.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 FeRAM의 캐패시터 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a capacitor of FeRAM according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c 는 종래기술에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도이고, 도 1d 및 도 1e 는 종래기술에 따른 FeRAM의 캐패시터 제조방법을 도시한 상태도이다.1A to 1C are cross-sectional views illustrating a capacitor manufacturing method of a FeRAM according to the prior art, and FIGS. 1D and 1E are state diagrams illustrating a capacitor manufacturing method of a FeRAM according to the prior art.
먼저, 소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택을 구비하는 층간절연막(11)을 형성한다.First, an interlayer insulating film 11 having a storage electrode contact is formed on a semiconductor substrate on which a predetermined lower structure is formed.
다음, 상기 층간절연막(11) 상부에 Ti 막 등을 사용하여 접착층(13)을 형성하고, 상기 접착층(13) 상부에 하부전극용 Pt막(15)을 형성한다.Next, an adhesive layer 13 is formed on the interlayer insulating layer 11 by using a Ti film, and a Pt film 15 for lower electrodes is formed on the adhesive layer 13.
그 다음, 상기 하부전극용 Pt막(15) 상부에 전하저장전극으로 예정되는 부분을 보호하는 감광막 패턴(17)을 형성한다. (도 1a참조)Next, a photoresist layer pattern 17 is formed on the lower electrode Pt layer 15 to protect a portion of the lower electrode Pt layer 15. (See FIG. 1A)
다음, 상기 감광막 패턴(17)을 식각마스크로 사용하여 상기 하부전극용 Pt막(15)과 접착층(13)을 식각한다. 이때, 상기 하부전극용 Pt막(15)은 아르곤(Ar)과 Cl 가스를 이용하여 식각하되, 주로 상기 아르곤 이온에 의해 스퍼터방법으로 식각된다. 상기 하부전극용 Pt막(15)은 휘발성이 낮고 화학반응성이 낮으므로 거의 순수한 Pt가 식각잔류물(19)로 발생되어 식각면에 증착된다. (도 1b참조)Next, the lower electrode Pt film 15 and the adhesive layer 13 are etched using the photoresist pattern 17 as an etching mask. In this case, the lower electrode Pt film 15 is etched using argon (Ar) and Cl gas, but is mainly etched by the sputtering method by the argon ions. Since the lower electrode Pt film 15 has low volatility and low chemical reactivity, almost pure Pt is generated as an etching residue 19 and deposited on the etching surface. (See FIG. 1B)
그 다음, 상기 감광막 패턴(17)을 제거하면, 상기 감광막 패턴(17)을 제거한 후에도 상기 감광막 패턴(17)의 두께 만큼 식각잔류물(19)이 남아 있게 된다. (도 1c참조)Next, when the photoresist pattern 17 is removed, the etch residue 19 remains as much as the thickness of the photoresist pattern 17 even after the photoresist pattern 17 is removed. (See FIG. 1C)
한편, 도 1f 는 종래기술에 따른 FeRAM의 캐패시터 제조방법에서 감광막의 두께에 따른 CD의 손실비율을 도시한 그래프도로서, 감광막이 두꺼울수록 CD(critical dimension)가 많이 손실되는 것을 도시한다.Meanwhile, FIG. 1F is a graph showing the loss ratio of CD according to the thickness of the photoresist film in the method of manufacturing a capacitor of FeRAM according to the prior art, and the thicker the photoresist film, the more the CD (critical dimension) is lost.
상기와 같이 종래기술에 따른 FeRAM의 캐패시터 제조방법은, 전극물질인 Pt막이 휘발성과 화학 반응성이 낮기 때문에 주로 아르곤이온에 의한 스퍼터방법으로 식각되는데, 식각후 식각잔류물로는 거의 순수한 Pt가 발생되어 Pt막과 감광막 패턴의 식각면에 증착되고, 식각마스크로 사용된 상기 감광막 패턴을 제거한 후에도 상기 식각잔류물은 제거되지 않고 ⓐ 부분과 같은 펜스가 남아 있기 때문에 후속 절연막 형성공정시 크랙(crack)을 발생시켜 소자의 특성을 저하시키므로, 상기 펜스를 제거하기 위하여 상기 Pt막 상부에 상기 감광막 보다 두께가 얇은 TiN막을 형성한 다음, 상기 TiN막을 패터닝한 후, 상기 TiN막을 식각마스크로 사용하여 상기 Pt막을 식각함으로써 상기 펜스의 높이를 낮추려고 하지만 공정이 복잡해지고, 상기 TiN막이 상기 Pt막 상부에 남아 소자의 특성에 영향을 미친다. 상기 감광막은 감광막 자체의 고유점성으로 인하여 낮은 두께로 형성할 수 없으며, 기존의 마이크로웨이브 다운 스트림 타입(microwave down stream type)의 감광막 스트리퍼(stripper)에서 감광막을 부분적으로 제거하는 경우에는 제거된 감광막의 두께보다 2 ∼ 3 배 정도의 CD(critical dimension)의 손실이 발생되어 공정에 적용하기 어렵운 문제점이 있다. (도 1d, 도 1e참조)As described above, the capacitor manufacturing method of the FeRAM according to the prior art is mainly etched by a sputtering method using argon ions because the Pt film, which is an electrode material, has low volatility and chemical reactivity, and almost pure Pt is generated as an etching residue after etching. Etch residues are not removed even after removing the photoresist pattern, which is deposited on the etching surface of the Pt film and the photoresist pattern, and the same fence remains as part ⓐ. To reduce the characteristics of the device, a TiN film having a thickness thinner than that of the photoresist film is formed on the Pt film to remove the fence, and then the TiN film is patterned, and then the Pt film is used as an etching mask. By etching, the height of the fence is reduced, but the process is complicated, and the TiN film is formed on the Pt film Oh affect the characteristics of the device. The photoresist film cannot be formed to a low thickness due to the intrinsic viscosity of the photoresist film itself, and when the photoresist film is partially removed from a conventional microwave down stream type photoresist stripper, Loss of CD (critical dimension) of about 2 to 3 times the thickness occurs, which makes it difficult to apply to the process. (See FIG. 1D, FIG. 1E)
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, RIE 플라즈마 소오스를 사용하여 감광막 패턴의 두께를 소정 두께 제거한 다음, Pt막을 식각하여 식각잔류물 펜스의 높이를 낮춤으로써 소자의 특성 및 신뢰성을 향상시키는 FeRAM의 캐패시터 제조방법을 제공하는데 그 목적이 있다.The present invention improves the characteristics and reliability of the device by removing the predetermined thickness of the photoresist pattern by using a RIE plasma source, and then etching the Pt film to lower the height of the etching residue fence in order to solve the problems of the prior art. It is an object of the present invention to provide a capacitor manufacturing method of FeRAM.
도 1a 내지 도 1c 는 종래기술에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a capacitor of FeRAM according to the prior art.
도 1d 및 도 1e 는 종래기술에 따른 FeRAM의 캐패시터 제조방법을 도시한 상태도.1D and 1E are state diagrams illustrating a method of manufacturing a capacitor of FeRAM according to the prior art.
한편, 도 1f 는 종래기술에 따른 FeRAM의 캐패시터 제조방법에서 감광막의 두께에 따른 CD의 손실비율을 도시한 그래프도.1F is a graph showing the loss ratio of CD according to the thickness of the photosensitive film in the capacitor manufacturing method of the FeRAM according to the prior art.
도 2a 내지 도 2d 는 본 발명에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method for manufacturing a capacitor of FeRAM according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
11, 12 : 층간절연막 13, 14 : 접착층11, 12: interlayer insulating film 13, 14: adhesive layer
15, 16 : 하부전극용 Pt막 17, 18 : 감광막 패턴15, 16: Pt film for lower electrode 17, 18: Photosensitive film pattern
19, 20 : 식각잔류물19, 20: etching residue
이상의 목적을 달성하기 위하여 본 발명에 따른 FeRAM의 캐패시터 제조방법은,In order to achieve the above object, a capacitor manufacturing method of FeRAM according to the present invention,
FeRAM 의 캐패시터 제조방법에 있어서,In the capacitor manufacturing method of FeRAM,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택이 구비되는 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact on the semiconductor substrate on which a predetermined lower structure is formed;
상기 층간절연막 상부에 접착층 및 하부전극용 Pt막의 적층구조를 형성하는 공정과,Forming a stacked structure of an adhesive layer and a lower electrode Pt film on the interlayer insulating film;
상기 하부전극용 Pt막 상부에 전하저장전극으로 예정되는 부분을 보호하는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the lower electrode Pt film to protect a portion intended as a charge storage electrode;
상기 감광막 패턴을 RIE 플라즈마 소오스로 소정 두께 애싱하는 공정과,Ashing the photoresist pattern with a RIE plasma source for a predetermined thickness;
상기 감광막 패턴을 식각마스크로 사용하여 상기 적층구조를 식각하는 공정과,Etching the laminate structure using the photoresist pattern as an etching mask;
상기 감광막 패턴을 제거하는 공정을 포함하는 것을 특징으로 한다.It characterized in that it comprises a step of removing the photosensitive film pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of FeRAM according to the present invention.
먼저, 반도체기판(도시안됨) 상에 소자분리 산화막(도시안됨)과 게이트산화막(도시안됨)을 형성하고, 게이트전극(도시안됨)과 소오스/드레인전극(도시안됨)으로 구성되는 모스 전계효과 트랜지스터를 형성하고, 상기 구조 상부에 저장전극 콘택 플러그를 구비하는 층간절연막(12)을 형성한다.First, an MOS field effect transistor is formed on a semiconductor substrate (not shown), and a device isolation oxide film (not shown) and a gate oxide film (not shown) are formed and a gate electrode (not shown) and a source / drain electrode (not shown) are formed. And an interlayer insulating film 12 having a storage electrode contact plug on the structure.
다음, 상기 층간절연막(12) 상부에 Ti막으로 접착층(14)을 형성하여 후속공정으로 형성되는 하부전극용 Pt막(16)이 상기 층간절연막(12)에 잘 접착되도록 한다.Next, an adhesive layer 14 is formed on the interlayer insulating film 12 by using a Ti film so that the lower electrode Pt film 16 formed in a subsequent process is well adhered to the interlayer insulating film 12.
그 다음, 상기 접착층(14) 상부에 하부전극용 Pt막(16)을 형성한다.Next, a Pt film 16 for lower electrodes is formed on the adhesive layer 14.
그리고, 상기 하부전극용 Pt막(16) 상부에 전하저장전극으로 예정되는 부분을 보호하는 감광막 패턴(18)을 형성한다. (도 2a참조)A photoresist pattern 18 is formed on the lower electrode Pt layer 16 to protect a portion of the lower electrode as the charge storage electrode. (See Figure 2A)
다음, 상기 감광막 패턴(18)의 두께를 소정 두께 제거한다.Next, the thickness of the photoresist pattern 18 is removed.
상기 감광막 패턴(18)을 소정 두께 제거하는 애싱(ashing)공정은 다음과 같이 실시한다.An ashing process for removing the predetermined thickness of the photosensitive film pattern 18 is performed as follows.
먼저, 척(chuck)의 온도를 0 ∼ 80℃로 하고, H2O와 CF4혼합가스를 상기 혼합가스는 를 사용하여 실시하되, 상기 혼합가스는 1 ∼ 100sccm의 H2O가스와 1 ∼ 50 sccm의 CF4가스로 되어 있고, 0 ∼ 2kW의 RF 파워를 인가하여 1 ∼ 60 초간 실시한다. 이때, 상기 H2O 가스를 증가시킴에 따라 감광막 패턴(18)의 식각률 및 CD의 손실은 증가하고, 상기 CF4가스를 첨가함에 따라 식각률이 급격히 증가하지만 CD의 이득이 커지므로 미량을 첨가한다. (도 2b참조)First, the temperature of the chuck is 0 to 80 ° C., and the mixed gas is performed using H 2 O and CF 4 mixed gas, but the mixed gas is 1 to 100 sccm H 2 O gas and 1 to 50 sccm of CF 4 gas is applied, and RF power of 0 to 2 kW is applied for 1 to 60 seconds. In this case, as the H 2 O gas is increased, the etch rate of the photoresist pattern 18 and the loss of CD increase. As the CF 4 gas is added, the etch rate rapidly increases, but the gain of the CD increases, so a small amount is added. . (See Figure 2b)
다음, 상기 감광막 패턴(18)을 식각마스크로 사용하여 상기 하부전극용 Pt막(16)과 접착층(14)을 식각하되 과도식각을 하여 상기 층간절연막(12)도 소정 두께 제거되도록 한다. 상기 식각공정으로 상기 감광막 패턴(18)도 소정 두께 식각되어 두께가 더 얇아지고, 식각잔류물(20)이 식각면에 적층된다. (도 2c참조)Next, the Pt layer 16 and the adhesive layer 14 for the lower electrode are etched using the photoresist pattern 18 as an etching mask, and the interlayer insulating layer 12 is also removed to have a predetermined thickness. In the etching process, the photoresist pattern 18 is also etched by a predetermined thickness, so that the thickness is thinner, and the etching residue 20 is stacked on the etching surface. (See FIG. 2C)
그 다음, 상기 감광막 패턴(18)을 제거하면 식각잔류물(20)의 펜스의 높이를 최소화할 수 있다. (도 2d참조)Next, by removing the photoresist pattern 18, it is possible to minimize the height of the fence of the etch residue 20. (See FIG. 2D)
이상에서 설명한 바와 같이 본 발명에 따른 FeRAM의 캐패시터 제조방법은, 하부 절연기판과의 접착력을 증가시키기 위해 Ti막을 형성한 다음, 하부전극용으로 Pt막을 형성하고, 상기 하부전극용 Pt막 상부에 전하저장전극으로 예정되는 부분을 보호하는 감광막 패턴을 형성한 후, RIE 플라즈마 소오스를 사용하여 감광막 패턴의 두께를 소정 두께 애싱한 다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 하부전극용 Pt막 및 Ti막을 식각함으로써 상기 감광막 패턴을 제거한 후 식각잔류물로 형성된 펜스의 높이를 낮춰 후속 공정을 용이하게 하고 그에 따른 소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the capacitor manufacturing method of the FeRAM according to the present invention, a Ti film is formed to increase adhesion to the lower insulating substrate, and then a Pt film is formed for the lower electrode, and the charge is formed on the upper Pt film for the lower electrode. After forming the photoresist pattern protecting the portion intended as the storage electrode, the thickness of the photoresist pattern is ashed by using a RIE plasma source, and then the Pt film and Ti for the lower electrode are used as the etch mask. By etching the film, after removing the photoresist pattern, the height of the fence formed of the etch residue is lowered to facilitate the subsequent process, and thus, the device characteristics and reliability are improved.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980044245A KR20000026631A (en) | 1998-10-22 | 1998-10-22 | Method for manufacturing capacitor of ferroelectric ram |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980044245A KR20000026631A (en) | 1998-10-22 | 1998-10-22 | Method for manufacturing capacitor of ferroelectric ram |
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| Publication Number | Publication Date |
|---|---|
| KR20000026631A true KR20000026631A (en) | 2000-05-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980044245A KR20000026631A (en) | 1998-10-22 | 1998-10-22 | Method for manufacturing capacitor of ferroelectric ram |
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| Country | Link |
|---|---|
| KR (1) | KR20000026631A (en) |
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1998
- 1998-10-22 KR KR1019980044245A patent/KR20000026631A/en not_active Application Discontinuation
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