KR100324016B1 - Method for forming charge storage electrode of semiconductor device - Google Patents
Method for forming charge storage electrode of semiconductor device Download PDFInfo
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- KR100324016B1 KR100324016B1 KR1019980025985A KR19980025985A KR100324016B1 KR 100324016 B1 KR100324016 B1 KR 100324016B1 KR 1019980025985 A KR1019980025985 A KR 1019980025985A KR 19980025985 A KR19980025985 A KR 19980025985A KR 100324016 B1 KR100324016 B1 KR 100324016B1
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 28
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 10
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 9
- 229910052786 argon Inorganic materials 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 239000007789 gas Substances 0.000 abstract description 24
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011737 fluorine Substances 0.000 abstract description 4
- 239000007772 electrode material Substances 0.000 abstract description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 2
- 229910000457 iridium oxide Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
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Abstract
본 발명은 반도체소자의 전하저장전극 형성방법에 관한 것으로, FeRAM(ferroelectric RAM) 소자의 제조공정에서 전극 재료로 IrO2막을 형성한 다음, 저장전극용 마스크를 식각마스크로 사용하여 탄소(C)와 불소(F)를 포함하는 가스와 아르곤(Ar)가스가 혼합된 플라즈마를 사용하여 상기 IrO2막을 식각함으로써 식각율을 향상시켜 저장전극을 형성하기 위한 식각공정을 용이하게 실시하고, 식각잔류물의 발생이 적기 때문에 저장전극의 전기적 특성이 우수하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a semiconductor device, wherein an IrO 2 film is formed of an electrode material in a manufacturing process of a ferroelectric RAM (FeRAM) device, and then a carbon for the storage electrode is used as an etching mask. By etching the IrO 2 film by using a plasma containing a gas containing fluorine (F) and an argon (Ar) gas, an etching process for easily forming an storage electrode by improving an etching rate and generating an etching residue The present invention relates to a technique for improving electrical characteristics and reliability of semiconductor devices due to excellent electrical characteristics of the storage electrodes.
Description
본 발명은 반도체소자의 전하저장전극 형성방법에 관한 것으로서, 특히 IrO2막을 전극재료로 사용하는 경우에 상기 IrO2막을 Ar 가스와 탄소 또는 불소를 포함하는 가스를 이용하여 식각하여 소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a semiconductor device. In particular, when an IrO 2 film is used as an electrode material, the IrO 2 film is etched by using an Ar gas and a gas containing carbon or fluorine, and thus the characteristics and reliability of the device. It is about a technology that can improve.
일반적으로, 반도체소자의 고집적화가 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 전하저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다. 이를 해결하기 위한 방안 중의 하나로서 높은 유전상수를 갖는 물질을 적용하려는 시도가 이루어지고 있다.In general, as the high integration of semiconductor devices increases, a fixed capacitance of a capacitor is required. In order to solve this problem, a method of using a material having a high dielectric constant of a capacitor, reducing the thickness of a dielectric film, or increasing the surface area of a charge storage electrode has emerged. In order to solve this problem, attempts have been made to apply a material having a high dielectric constant.
상기와 같이 유전상수가 높은 물질로는 강유전체막이 있다.As a material having a high dielectric constant, there is a ferroelectric film.
상기 강유전체막은 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remainent polarization) 상태를 갖는 강유전체로서, 박막화하여 전원이 꺼진 상태에서도 데이타를 기억하는 비휘발성(nonvolatile)메모리인 FeRAM 소자 개발에 적용되고 있다.The ferroelectric film is a ferroelectric with a dielectric constant ranging from several hundreds to thousands at room temperature and having two stable polarization states. Is being applied.
그리고, 상기한 강유전체막을 사용하기 위하여 저장전극용 도전층으로 전도성 산화막을 사용하는 것을 검토하고 있다.In order to use the ferroelectric film described above, the use of a conductive oxide film as the conductive layer for the storage electrode has been studied.
그러나, 상기 이리듐산화막 ( IrO2) 은 현재 저장전극용 도전층으로 사용되지 않고 있는 실정이다.However, the iridium oxide film IrO 2 is not currently used as a conductive layer for a storage electrode.
본 발명은 종래에 언급된 바 없는 저장전극용 도전층으로서의 이리듐 산화막을 패터닝하는 것으로서, 탄소와 불소를 포함하는 가스와 Ar가스의 혼합가스를 사용하여 상기 IrO2막을 용이하게 식각하며 식각잔류물의 발생을 최소화함으로써 반도체 소자의 특성 및 신뢰성을 향상시키는 반도체소자의 전하저장전극 형성방법을 제공하는데 그 목적이 있다.The present invention is to pattern an iridium oxide film as a conductive layer for a storage electrode, which is not mentioned in the related art, and easily etches the IrO 2 film by using a mixed gas of carbon and fluorine-containing gas and Ar gas, and generates an etching residue. It is an object of the present invention to provide a method for forming a charge storage electrode of a semiconductor device, which improves the characteristics and reliability of the semiconductor device by minimizing the voltage.
도 1 내지 도 3 은 본 발명에 따른 반도체소자의 전하저장전극 형성방법을 도시한 단면도.1 to 3 are cross-sectional views showing a method for forming a charge storage electrode of a semiconductor device according to the present invention.
도 4 는 본 발명에 의해 CF4/Ar 혼합가스로 식각된 IrO2막의 식각상태도.Figure 4 is an etching state of the IrO 2 film etched with a CF 4 / Ar mixed gas in accordance with the present invention.
〈 도면의 주요 부분에 대한 부호 설명 〉〈Explanation of the Signs of Major Parts of Drawings〉
11 : 층간절연막 13 : IrO2막11 interlayer insulating film 13 IrO 2 film
15 : 감광막 패턴15 photosensitive film pattern
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 전하저장전극 형성방법은,In order to achieve the above object, the charge storage electrode forming method of a semiconductor device according to the present invention,
FeRAM 소자의 제조공정에 있어서,In the manufacturing process of the FeRAM device,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택 플러그를 구비하는 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate on which a predetermined lower structure is formed;
상기 층간절연막 상부에 저장전극용 IrO2막을 형성하는 공정과,Forming an IrO 2 film for a storage electrode on the interlayer insulating film;
상기 저장전극용 IrO2막 상부에 저장전극으로 예정되는 부분을 보호하는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the IrO 2 film for the storage electrode to protect a portion intended as a storage electrode;
상기 저장전극용 IrO2막을 상기 감광막 패턴을 식각마스크로 사용하여 C와 F를 포함하는 가스와 Ar가스의 혼합가스로 식각하여 저장전극을 형성하는 공정과,Forming a storage electrode by etching the storage electrode IrO 2 film with a mixed gas of a gas containing C and F and an Ar gas using the photoresist pattern as an etching mask;
상기 감광막 패턴을 제거하는 공정을 포함하는 것을 특징으로 한다.It characterized in that it comprises a step of removing the photosensitive film pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 3 은 본 발명에 따른 반도체소자의 전하저장전극 형성방법을 도시한 단면도이고, 도 4 는 본 발명에 의해 CF4/Ar 혼합가스로 식각된 IrO2막의 식각상태도이다.1 to 3 are cross-sectional views illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention, and FIG. 4 is an etching state diagram of an IrO 2 film etched with a CF 4 / Ar mixed gas according to the present invention.
먼저, 반도체기판(도시안됨) 상에 소자분리 산화막(도시안됨)과 게이트산화막(도시안됨)을 형성하고, 게이트전극(도시안됨)과 소오스/드레인전극(도시안됨)으로 구성되는 모스 전계효과 트랜지스터를 형성하고, 저장전극 콘택 플러그를 구비하는 층간절연막(11)을 형성한다.First, an MOS field effect transistor is formed on a semiconductor substrate (not shown), and an element isolation oxide film (not shown) and a gate oxide film (not shown) are formed and a gate electrode (not shown) and a source / drain electrode (not shown) are formed. And an interlayer insulating film 11 having a storage electrode contact plug is formed.
다음, 상기 층간절연막(11) 상부에 저장전극용 IrO2막(13)을 형성한다.Next, an IrO 2 film 13 for a storage electrode is formed on the interlayer insulating film 11.
그 다음, 상기 IrO2막(13) 상부에 저장전극으로 예정되는 부분을 보호하는 감광막 패턴(15)을 형성한다. (도 1참조)Next, a photoresist pattern 15 is formed on the IrO 2 film 13 to protect a portion intended as a storage electrode. (See Fig. 1)
다음, 상기 감광막 패턴(15)을 식각마스크로 사용하여 상기 IrO2막(13)을 식각한다. 이때, 상기 식각공정은 F를 포함하는 가스와 Ar가스의 혼합 가스를 사용하여 실시한다. 상기 F를 포함하는 가스와 Ar가스의 혼합가스의 유량은 10∼70sccm으로 이중 상기 Ar가스의 비는 30∼70%로 하고, 상기 F를 포함하는 가스는 CF4, SF6, NF3, CHF3등을 사용한다. 특히, C와 F를 포함하는 CF4가스를 사용하면 상기 감광막 패턴(15)과 IrO2막(13)의 식각선택비와 식각잔류물을 조절하기 용이하고, 도 4 는 CF4/Ar 혼합가스로 식각된 IrO2막의 식각상태도이다.Next, the IrO 2 film 13 is etched using the photoresist pattern 15 as an etching mask. In this case, the etching process is performed using a gas containing F and a gas mixture of Ar gas. The flow rate of the mixed gas of the gas containing F and Ar gas is 10 to 70 sccm, of which the ratio of Ar gas is 30 to 70%, and the gas containing F is CF 4 , SF 6 , NF 3 , CHF Use 3, etc. In particular, the use of CF 4 gas containing C and F makes it easy to control the etching selectivity and etching residues of the photoresist pattern 15 and the IrO 2 film 13, and FIG. 4 shows a CF 4 / Ar mixed gas. The etching state diagram of the IrO 2 film etched with.
그리고, 상기 IrO2막(13) 식각공정은 700∼1200W범위에서 적당하게는 1000W의 소오스 파워와 300∼700W범위에서 적당하게는 500W의 바이어스 파워를 사용한다. 또한, 상기 식각공정은 척(chuck)의 온도가 30∼50℃ 적당하게는 40℃이고, 1∼10mTorr 적당하게는 5mTorr의 압력인 식각조건에서 실시한다. (도 2, 도 4참조)In the etching process, the IrO 2 film 13 uses a source power of 1000 W in the range of 700 to 1200 W, and a bias power of 500 W in the range of 300 to 700 W. Further, the etching process is carried out under etching conditions in which the temperature of the chuck is 30 to 50 ° C., preferably 40 ° C., and 1 to 10 mTorr, 5 mTorr. (See Figs. 2 and 4)
그 다음, 상기 감광막 패턴(15)을 제거한다. (도 3참조)Next, the photoresist pattern 15 is removed. (See Fig. 3)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 전하저장전극 형성방법은, FeRAM 소자의 제조공정에서 전극 재료로 IrO2막을 형성한 다음, 저장전극용 마스크를 식각마스크로 사용하여 탄소(C)와 불소(F)를 포함하는 가스와 아르곤 (Ar)가스가 혼합된 가스로 상기 IrO2막을 식각함으로써 식각율을 향상시켜 저장전극을 형성하기 위한 식각공정을 용이하게 실시하고, 식각잔류물의 발생이 적기 때문에 저장전극의 전기적 특성이 우수하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of forming a charge storage electrode of a semiconductor device according to the present invention, an IrO 2 film is formed of an electrode material in the manufacturing process of a FeRAM device, and then a carbon (C) and a mask are used as an etching mask. By etching the IrO 2 film with a gas containing fluorine (F) and argon (Ar) gas, the etching process is easily performed to improve the etching rate to form a storage electrode, and the etching residues are generated less frequently. Therefore, the electrical characteristics of the storage electrode are excellent, and thus, there is an advantage of improving the characteristics and reliability of the semiconductor device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100495913B1 (en) * | 2000-12-30 | 2005-06-17 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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1998
- 1998-06-30 KR KR1019980025985A patent/KR100324016B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100495913B1 (en) * | 2000-12-30 | 2005-06-17 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR20000004541A (en) | 2000-01-25 |
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