KR20000024917A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20000024917A KR20000024917A KR1019980041720A KR19980041720A KR20000024917A KR 20000024917 A KR20000024917 A KR 20000024917A KR 1019980041720 A KR1019980041720 A KR 1019980041720A KR 19980041720 A KR19980041720 A KR 19980041720A KR 20000024917 A KR20000024917 A KR 20000024917A
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- tungsten silicide
- semiconductor device
- silicide layer
- component
- vapor deposition
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로서, 보다 상세하게는 화학기상증착법에 의해 텅스텐 실리사이드층을 형성할 때 텅스텐 소스 가스로 사용되는 WF6가스에 포함된 플루오르 성분이 후속 열공정에 의해 하부층으로 침투하는 것을 방지하여 소자특성을 향상시킬 수 있도록 하는 반도체소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form a tungsten silicide layer by chemical vapor deposition, the fluorine component contained in the WF 6 gas used as a tungsten source gas to the lower layer by a subsequent thermal process. The present invention relates to a method for manufacturing a semiconductor device that can prevent penetration and improve device characteristics.
반도체소자가 고집적화됨에 따라 배선으로 사용되는 금속을 되도록 얇은 두께로 낮은 비저항값과 면저항값을 갖는 특성을 원하게 된다.As semiconductor devices are highly integrated, the metals used for wiring are desired to have a low specific resistance and a sheet resistance as thin as possible.
현재, 64M DRAM 이상의 소자에서는 고속동작, 고집적화, 저전력소모를 위한 소자간 배선을 위해 대부분의 비트라인은 물론 워드라인에도 LPCVD(Low Pressure Chemical Vapor Deposition ) 방법을 이용하여 텅스텐 실리사이드막을 폴리사이드 구조로 사용하고 있다.Currently, tungsten silicide film is used as polyside structure using LPCVD (Low Pressure Chemical Vapor Deposition) method in most bit lines and word lines for inter-device wiring for high-speed operation, high integration, and low power consumption in devices larger than 64M DRAM. Doing.
도 1은 종래의 반도체소자의 제조방법을 설명하기 위한 텅스텐 실리사이드 게이트를 나타낸 단면도이다.1 is a cross-sectional view illustrating a tungsten silicide gate for explaining a method of manufacturing a conventional semiconductor device.
여기에서 보는 바와 같이 반도체 기판(10)을 형성한 다음, 게이트 산화막(20)과 도프드 폴리실리콘막(30)을 차례로 형성한 후, 텅스텐 실리사이드층 소스가스로 WF6가스를 사용하여 화학기상증착법으로 텅스텐 실리사이드층(40)을 형성한다.As shown here, after the semiconductor substrate 10 is formed, the gate oxide film 20 and the doped polysilicon film 30 are sequentially formed, followed by chemical vapor deposition using a WF 6 gas as a tungsten silicide layer source gas. The tungsten silicide layer 40 is formed.
이렇게 형성된 텅스텐 실리사이드층(40)에는 텅스텐 실리사이드층 소스가스로 사용되는 WF6가스에 포함된 플루오르성분이 증착과정에서 텅스텐 실리사이드층(40) 내부에 포함되어 있다가 600℃이상의 후속 고온 열공정을 진행하면서 도프드 폴리실리콘막(30)과 게이트 산화막(20)으로 확산되어 게이트 산화막(20)의 항복전압(Breadkdown Voltage)을 낮추게 되며, CCST(Contant Current Stressed dielectric breakdown Time)특성을 악화시켜 소자 특성을 열화시키게 된다.In the tungsten silicide layer 40 formed as described above, fluorine contained in the WF 6 gas used as the tungsten silicide layer source gas is included in the tungsten silicide layer 40 during the deposition process, and then a subsequent high temperature thermal process of 600 ° C. or higher is performed. While diffused into the doped polysilicon film 30 and the gate oxide film 20 to lower the breakdown voltage (Bkkdown Voltage) of the gate oxide film 20, and deteriorates the contact current stressed dielectric breakdown time (CCST) characteristics to improve the device characteristics Deteriorated.
이러한 문제점을 해결하기 위해 텅스텐 실리사이드층(40) 증착시의 조건 즉, 압력, 전력, 온도, 가스비율 등을 변화시켜 플루오르의 양을 줄이는 방법을 사용하고 있으나 이러한 방법도 플루오르가 남아있게 된다는 문제점이 있다.In order to solve this problem, a method of reducing the amount of fluorine is used by changing the conditions during deposition of the tungsten silicide layer 40, that is, pressure, power, temperature, and gas ratio, but such a method also causes fluorine to remain. have.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 화학기상증착법에 의해 텅스텐 실리사이드막 형성시 텅스텐 실리사이드막 내부에 포함되어있는 플루오르 성분을 외부로 방출시키기 위해 LPCVD장비로 N2나 Ar분위기에서 적정온도와 압력상태를 유지하여 일정 시간동안 열처리를 하여 플루오르 성분이 하부층으로 침투하는 것을 방지하고 방출시킬 수 있도록 하는 반도체소자의 제조 방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to use N as an LPCVD apparatus to release the fluorine component contained in the tungsten silicide layer to the outside when the tungsten silicide layer is formed by chemical vapor deposition. The present invention provides a method for fabricating a semiconductor device that maintains an appropriate temperature and pressure in an atmosphere of 2 or Ar to prevent heat from being released into a lower layer by performing heat treatment for a predetermined time.
도1은 종래의 반도체소자의 제조방법을 설명하기 위한 텅스텐 실리사이드 게이트를 나타낸 단면도이다.1 is a cross-sectional view showing a tungsten silicide gate for explaining a conventional method of manufacturing a semiconductor device.
도 2는 본 발명에 의한 반도체소자의 제조방법을 설명하기 위한 텅스텐 실리사이드 게이트를 나타낸 단면도이다.2 is a cross-sectional view illustrating a tungsten silicide gate for explaining a method of manufacturing a semiconductor device according to the present invention.
도 3은 종래의 반도체소자의 제조방법에 의한 텅스텐 실리사이드 게이트에서의 플루오르 분포도이다.3 is a fluorine distribution diagram of a tungsten silicide gate according to a conventional method for manufacturing a semiconductor device.
도4는 본 발명에 의한 반도체소자의 제조방법에 의한 텅스텐 실리사이드 게이트에서의 플루오르 분포도이다.4 is a fluorine distribution diagram of a tungsten silicide gate according to the method of manufacturing a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판10: substrate
20 : 게이트 산화막20: gate oxide film
30 : 폴리실리콘30: polysilicon
40 : 텅스텐 실리사이드40: tungsten silicide
상기와 같은 목적을 실현하기 위한 본 발명은 WF6가스를 텅스텐 실리사이드층 소스가스로 하여 화학기상증착법으로 텅스텐 실리사이드를 형성하는 반도체소자의 제조 방법에 있어서, 텅스텐 실리사이드를 형성한 후 LPCVD 장비를 이용하여 N2가스 분위기에서 플루오르 성분을 제거하기 위한 열처리 과정을 더 포함하여 이루어진 것을 특징으로 한다.In the present invention for realizing the above object, in the method of manufacturing a semiconductor device in which tungsten silicide is formed by chemical vapor deposition using WF 6 gas as the tungsten silicide layer source gas, after the tungsten silicide is formed, LPCVD equipment is used. It characterized in that it further comprises a heat treatment process for removing the fluorine component in the N 2 gas atmosphere.
상기와 같이 이루어진 반도체소자의 제조 방법은 WF6가스를 텅스텐 실리사이드층 소스가스로 하여 화학기상증착법으로 텅스텐 실리사이드를 형성한 후 LPCVD 장비를 이용하여 N2분위기에서 열처리를 수행하여 텅스텐 실리사이드 내부에 포함된 플루오르 성분을 효과적으로 제거할 수 있다.In the method of manufacturing a semiconductor device as described above, tungsten silicide is formed by chemical vapor deposition using a WF 6 gas as a tungsten silicide layer source gas, and heat treatment is performed in an N 2 atmosphere by using an LPCVD apparatus to include tungsten silicide. The fluorine component can be removed effectively.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 3은 본 발명에 의한 반도체소자 제조 방법으로 형성한 텅스텐 실리사이드 게이트를 나타낸 단면도이다.3 is a cross-sectional view showing a tungsten silicide gate formed by a method of manufacturing a semiconductor device according to the present invention.
여기에서 보는 바와 같이 반도체 기판(10)을 형성한 다음, 게이트 산화막(20)과 도프드 폴리실리콘막(30)을 차례로 형성한 후, 텅스텐 실리사이드층 소스가스로 WF6가스를 사용하여 화학기상증착법으로 텅스텐 실리사이드층(40)을 형성한다.As shown here, after the semiconductor substrate 10 is formed, the gate oxide film 20 and the doped polysilicon film 30 are sequentially formed, followed by chemical vapor deposition using a WF 6 gas as a tungsten silicide layer source gas. The tungsten silicide layer 40 is formed.
이후, 텅스텐 실리사이드층(40)에 분포된 플루오르 성분을 제거하기 위해 5℃/min ∼ 30℃/min의 속도로 온도를 올려 500℃ ∼ 900℃의 범위에서 LPCVD 장비를 이용하여 N2또는 Ar등의 불활성기체 분위기에서 10mtorr ∼ 100torr의 압력으로 10분 ∼ 150분 동안 열처리를 수행한다.Thereafter, in order to remove the fluorine component distributed in the tungsten silicide layer 40, the temperature was raised at a rate of 5 ° C./min to 30 ° C./min using N 2 or Ar using LPCVD equipment in the range of 500 ° C. to 900 ° C. Heat treatment is performed for 10 minutes to 150 minutes at a pressure of 10 mtorr to 100 torr in an inert gas atmosphere.
위와 같이 WF6가스를 사용하여 화학기상증착법으로 텅스텐 실리사이드층(40)을 증착한 후 LPCVD장비로 N2분위기에서 10mtorr ∼ 100torr의 압력으로 500℃ ∼ 900℃의 범위에서 10분 ∼ 150분 동안 열처리를 수행하여 텅스텐 실리사이드층(40)에 포함된 플루오르 성분을 제거한다.After depositing the tungsten silicide layer 40 by chemical vapor deposition using WF 6 gas as described above, heat treatment for 10 minutes to 150 minutes in a range of 500 ° C. to 900 ° C. at a pressure of 10 mtorr to 100 torr in an N 2 atmosphere with LPCVD equipment. Next, the fluorine component included in the tungsten silicide layer 40 is removed.
도 3과 도 4는 종래의 반도체소자의 제조방법에 의한 텅스텐 실리사이드 게이트에서의 플루오르의 분포도와 본 발명에 의한 텅스텐 실리사이드 게이트에서의 플루오르 분포도를 나타내었다.3 and 4 show a fluorine distribution in the tungsten silicide gate according to the conventional method of manufacturing a semiconductor device and a fluorine distribution in the tungsten silicide gate according to the present invention.
여기에서 보는 바와 같이 도 3과 도 4의 'A' 부분을 살펴보면 도 4의 프루오르 분포가 현저하게 감소되었음을 알 수 있다.As shown here, looking at the portion 'A' of FIGS. 3 and 4, it can be seen that the Fruor distribution of FIG. 4 is significantly reduced.
상기한 바와 같이 본 발명은 반도체소자에서 화학기상증착법으로 텅스텐 실리사이드층을 형성할 때 텅스텐 실리사이드층 소스가스로 사용되는 WF6가스에 의해 텅스텐 실리사이드층 내부에 포함된 플루오르 성분이 후속 열공정에 의해 하부층으로 침투하는 것을 방지하기 위해 LPCVD장비로 N2분위기에서 열처리를 하여 플루오르 성분을 제거하여 하부층의 특성저하를 방지하여 소자의 특성을 향상시킬 수 있다는 이점이 있다.As described above, according to the present invention, when the tungsten silicide layer is formed by chemical vapor deposition in a semiconductor device, the fluorine component contained in the tungsten silicide layer by the WF 6 gas, which is used as the tungsten silicide layer source gas, is formed by the subsequent thermal process. In order to prevent the infiltration into the LPCVD equipment by heat treatment in an N 2 atmosphere to remove the fluorine component has the advantage of preventing the deterioration of the characteristics of the lower layer to improve the device characteristics.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980041720A KR100313098B1 (en) | 1998-10-02 | 1998-10-02 | Method for manufacturing of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980041720A KR100313098B1 (en) | 1998-10-02 | 1998-10-02 | Method for manufacturing of semiconductor device |
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| KR20000024917A true KR20000024917A (en) | 2000-05-06 |
| KR100313098B1 KR100313098B1 (en) | 2002-01-15 |
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