KR100301808B1 - Method for fabrricating in semiconductor device - Google Patents
Method for fabrricating in semiconductor device Download PDFInfo
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- KR100301808B1 KR100301808B1 KR1019980040629A KR19980040629A KR100301808B1 KR 100301808 B1 KR100301808 B1 KR 100301808B1 KR 1019980040629 A KR1019980040629 A KR 1019980040629A KR 19980040629 A KR19980040629 A KR 19980040629A KR 100301808 B1 KR100301808 B1 KR 100301808B1
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- gate electrode
- semiconductor substrate
- forming
- metal layer
- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000002844 melting Methods 0.000 claims abstract description 8
- 230000008018 melting Effects 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 239000012159 carrier gas Substances 0.000 claims description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 abstract description 24
- 239000010937 tungsten Substances 0.000 abstract description 24
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 16
- 230000010354 integration Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- -1 tungsten nitride Chemical class 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 5
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- SKKJKSIXKUSLIE-UHFFFAOYSA-N oxotungsten;silicon Chemical compound [Si].[W]=O SKKJKSIXKUSLIE-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
Abstract
본 발명은 GOI(Gate Oxide Integration) 특성이 우수하며 저저항의 텅스텐 게이트 전극을 형성하도록 한 반도체 소자의 제조방법에 관한 것으로서, 반도체 기판상에 게이트 절연막을 형성하는 단계와, 상기 게이트 절연막상에 질소를 함유한 고융점 금속층을 형성하는 단계와, 상기 고융점 금속층 및 게이트 절연막을 선택적으로 제거하여 게이트 전극을 형성하는 단계와, 그리고 상기 게이트 전극을 포함한 반도체 기판에 급속 열처리로 선택 산화하는 단계를 포함하여 형성함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a high gate oxide integration (GOI) characteristic and to forming a low resistance tungsten gate electrode, the method comprising: forming a gate insulating film on a semiconductor substrate; Forming a high melting point metal layer containing the silicon oxide, selectively removing the high melting point metal layer and the gate insulating layer to form a gate electrode, and selectively oxidizing the semiconductor substrate including the gate electrode by rapid heat treatment. It is characterized by forming.
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 저저항의 게이트 전극을 형성하는데 적당한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for forming a low resistance gate electrode.
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래 기술의 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device of the prior art.
도 1a에 도시한 바와 같이, 필드 산화막(12)에 의해 활성영역이 구분된 반도체 기판(11)위에 열산화방식을 이용하여 약 65Å두께로 게이트 산화막(13)을 형성한다.As shown in FIG. 1A, the gate oxide film 13 is formed to a thickness of about 65 kHz on the semiconductor substrate 11 in which the active regions are divided by the field oxide film 12 using a thermal oxidation method.
이어, 상기 게이트 산화막(13)을 포함한 반도체 기판(11)의 전면에 LPCVD로 폴리 실리콘(14)을 약 2000Å두께로 증착한다.Subsequently, polysilicon 14 is deposited on the entire surface of the semiconductor substrate 11 including the gate oxide film 13 by LPCVD at a thickness of about 2000 kPa.
여기서 상기 폴리 실리콘(14)은 언도우프트 폴리 실리콘이고, NMOS 트랜지스터를 형성할 때는 As 또는 P 이온을 주입하고, PMOS 트랜지스터를 형성할 때는 B 또는 BF2이온을 주입한다.The polysilicon 14 is undoped polysilicon, and implants As or P ions when forming an NMOS transistor, and implants B or BF 2 ions when forming a PMOS transistor.
도 1b에 도시한 바와 같이, 상기 폴리 실리콘(14)상에 베리어 메탈층(15)을 증착하고, 상기 베리어 메탈층(15)상에 텅스텐막(16)을 약 1000Å두께로 증착한다.As shown in FIG. 1B, a barrier metal layer 15 is deposited on the polysilicon 14, and a tungsten film 16 is deposited on the barrier metal layer 15 with a thickness of about 1000 mW.
이어, 상기 텅스텐막(16)상에 절연막(17)을 약 2000Å 두께로 증착한다.Subsequently, an insulating film 17 is deposited on the tungsten film 16 to a thickness of about 2000 mW.
그리고 상기 절연막(17)상에 포토레지스트(18)를 도포한 후, 노광 및 현상공정을 실시하여 포토레지스트(18)를 패터닝하여 게이트 영역을 정의한다.After the photoresist 18 is coated on the insulating film 17, an exposure and development process is performed to pattern the photoresist 18 to define a gate region.
도 1c에 도시한 바와 같이, 상기 패터닝된 포토레지스트(18)를 마스크로 이용하여 상기 절연막(17), 텅스텐막(16), 베리어 메탈층(15), 폴리 실리콘(14), 게이트 산화막(13)을 선택적으로 패터닝하여 게이트 전극(19)을 형성한다.As shown in FIG. 1C, the insulating film 17, the tungsten film 16, the barrier metal layer 15, the polysilicon 14, and the gate oxide film 13 are formed by using the patterned photoresist 18 as a mask. ) Is selectively patterned to form the gate electrode 19.
도 1d에 도시한 바와 같이, 상기 포토레지스트(18)를 제거하고, 상기 게이트 전극(19)이 형성된 반도체 기판(11)에 선택 산화(Selective Oxidation)공정을 실시하여 게이트 전극(19)의 측면과 반도체 기판(11)의 표면에 산화막(20)을 형성한다.As shown in FIG. 1D, the photoresist 18 is removed, and a selective oxidation process is performed on the semiconductor substrate 11 on which the gate electrode 19 is formed. An oxide film 20 is formed on the surface of the semiconductor substrate 11.
여기서 상기 선택 산화는 텅스텐/폴리 구조의 게이트 전극(19)에서는 웨트-할로겐(Wet-hydrogen) 산화를 실시하고, 이 공정은 H2O/H2(여기서 H2O : H2= 1 : 1 정도)분위기에서 800~950℃ 온도로 실시한다.The selective oxidation is a wet-hydrogen oxidation in the tungsten / poly structure gate electrode 19, and this process is performed by H 2 O / H 2 (where H 2 O: H 2 = 1: 1). The temperature should be 800 ~ 950 ℃ in the atmosphere.
이때 상기 베리어 메탈층(15)의 약 50Å두께가 파괴되고, 상기 산화막(20)은 금속층의 표면에는 형성되지 않고 실리콘의 계면에만 형성된다.At this time, the thickness of the barrier metal layer 15 is about 50 GPa, and the oxide film 20 is not formed on the surface of the metal layer but is formed only at the interface of silicon.
도 1e에 도시한 바와 같이, 상기 게이트 전극(19)을 포함한 반도체 기판(11)의 전면에 절연막을 증착한 후, 전면에 에치백(Etch Back)공정을 실시하여 게이트 전극(19)의 양측면 및 패터닝된 절연막(17)의 양측면에 절연막 측벽(21)을 형성한다.As shown in FIG. 1E, an insulating film is deposited on the entire surface of the semiconductor substrate 11 including the gate electrode 19, and then an etch back process is performed on the entire surface to form both sides of the gate electrode 19 and An insulating film sidewall 21 is formed on both sides of the patterned insulating film 17.
한편, 상기 절연막 측벽(21)을 형성하기 전에 게이트 전극(19) 양측의 반도체 기판(11) 표면내에 LDD(Lightly Doped Drain) 영역을 형성하고, 상기 절연막 측벽(21)을 형성한 후에 전면에 소오스/드레인용 불순물 이온을 주입하여 상기 게이트 전극(19) 양측의 반도체 기판(11) 표면내에 LDD 구조를 갖는 소오스/드레인 불순물영역(22)을 형성한다.Meanwhile, before forming the insulating film sidewall 21, a lightly doped drain (LDD) region is formed in the surface of the semiconductor substrate 11 on both sides of the gate electrode 19, and after the insulating film sidewall 21 is formed, a source is formed on the entire surface. Source / drain impurity ions are implanted to form a source / drain impurity region 22 having an LDD structure in the surface of the semiconductor substrate 11 on both sides of the gate electrode 19.
참고문헌은 Y.Akaska, "Low-Resistivity Poly-Metal Gate Electrode Durablefor High-Temperature Processing", IEEE Trans.Electron Devices, Vol.43, pp.1864-1869, 1996이다.Reference is made to Y. Akaska, "Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing", IEEE Trans. Electron Devices, Vol. 43, pp. 1864-1869, 1996.
그러나 상기와 같은 종래 기술의 반도체 소자의 제조방법에 있어서 다음과 같은 문제점이 있었다.However, there is a problem in the method of manufacturing a semiconductor device of the prior art as described above.
첫째, 폴리 실리콘상에 텅스텐막을 증착하는 경우 베리어로 적용되는 베리어 메탈층의 열적인 불안정성으로 인해 800℃이상의 후속 열공정에서 텅스텐막과 폴리 실리콘의 계면에 실리사이드(Silicide)가 형성된다.First, when the tungsten film is deposited on polysilicon, silicide is formed at the interface between the tungsten film and the polysilicon in a subsequent thermal process of 800 ° C. or higher due to thermal instability of the barrier metal layer applied as a barrier.
둘째, 텅스텐/폴리 구조의 게이트 전극에 고온의 온도에서 선택 산화를 실시함으로써 베리어 메탈층의 분해 온도 이상으로 인하여 실리사이드션(Silicidation)에 기인하여 급격한 저항의 증가 및 GOI(Gate Oxide Integration) 특성저하가 된다.Second, the selective oxidation of the gate electrode of the tungsten / poly structure is performed at a high temperature so that the sudden increase in resistance and the decrease in the property of the gate oxide integration (GOI) are caused by the silicidation due to the decomposition temperature of the barrier metal layer. do.
셋째, 256M DRAM 이상의 소자에서 게이트 산화막 두께가 60Å이하로 감소함에 따라 폴리 실리콘의 B 이온이 게이트 산화막을 통과해 소자 특성의 열화가 발생한다.Third, as the gate oxide film thickness decreases below 60 microseconds in devices of 256M DRAM or more, B ions of polysilicon pass through the gate oxide film, causing deterioration of device characteristics.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 GOI 특성이 우수하며 저저항의 텅스텐 게이트 전극을 형성하도록 한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device having excellent GOI characteristics and forming a low resistance tungsten gate electrode.
도 1a 내지 도 1e는 종래 기술의 반도체 소자의 제조방법을 나타낸 공정단면도1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device of the prior art.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 3은 텅스텐-실리콘-산소의 3성분계 상태도3 is a three-component state diagram of tungsten-silicon-oxygen
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
31 : 반도체 기판 32 : 필드 산화막31 semiconductor substrate 32 field oxide film
33 : 게이트 산화막 34 : 질화 텅스텐막33 gate oxide film 34 tungsten nitride film
34a : 게이트 전극 35 : 포토레지스트34a: gate electrode 35: photoresist
36 : 산화막 37 : 절연막 측벽36 oxide film 37 insulating film sidewall
38 : 소오스/드레인 불순물영역38 source / drain impurity region
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조방법은 반도체 기판상에 게이트 절연막을 형성하는 단계와, 상기 게이트 절연막상에 질소를 함유한 고융점 금속층을 형성하는 단계와, 상기 고융점 금속층 및 게이트 절연막을 선택적으로 제거하여 게이트 전극을 형성하는 단계와, 그리고 상기 게이트 전극을 포함한 반도체 기판에 급속 열처리로 선택 산화하는 단계를 포함하여 형성함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate insulating film on a semiconductor substrate, forming a high melting point metal layer containing nitrogen on the gate insulating film, And selectively removing the melting point metal layer and the gate insulating film to form a gate electrode, and selectively oxidizing the semiconductor substrate including the gate electrode by rapid heat treatment.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 도 2a에 도시한 바와 같이, 필드 산화막(32)에 의해 활성영역이 구분된 반도체 기판(31)위에 열산화방식을 이용하여 약 65Å두께를 갖는 게이트 산화막(33)을 형성한다.First, as shown in FIG. 2A, a gate oxide film 33 having a thickness of about 65 kHz is formed on the semiconductor substrate 31 whose active region is divided by the field oxide film 32 using a thermal oxidation method.
도 2b에 도시한 바와 같이, 상기 게이트 산화막(33)을 포함한 반도체 기판(31)의 전면에 질화 텅스텐(WNx)막(34)을 1000Å두께로 증착한다.As shown in FIG. 2B, a tungsten nitride (WNx) film 34 is deposited on the entire surface of the semiconductor substrate 31 including the gate oxide film 33 at a thickness of 1000 mW.
여기서 상기 질화 텅스텐막(34)의 질소 함유량은 5~55%이다.Here, the nitrogen content of the tungsten nitride film 34 is 5 to 55%.
이어, 상기 질화 텅스텐막(34)상에 포토레지스트(35)를 도포한 후, 노광 및 현상공정을 실시하여 포토레지스트(35)를 패터닝하여 게이트가 형성될 영역을 정의한다.Subsequently, after the photoresist 35 is coated on the tungsten nitride film 34, exposure and development processes are performed to pattern the photoresist 35 to define a region in which a gate is to be formed.
도 2c에 도시한 바와 같이, 상기 패터닝된 포토레지스트(35)를 마스크로 이용하여 상기 질화 텅스텐막(34)과 게이트 산화막(33)을 선택적으로 패터닝하여 게이트 전극(34a)을 형성한다.As shown in FIG. 2C, the tungsten nitride film 34 and the gate oxide film 33 are selectively patterned using the patterned photoresist 35 as a mask to form a gate electrode 34a.
도 2d에 도시한 바와 같이, 상기 반도체 기판(31)에 급속 열처리에 의한 선택 산화 공정을 실시하여 상기 게이트 산화막(33)이 제거된 반도체 기판(31)의 표면에 산화막(36)을 형성한다.As shown in FIG. 2D, an oxide film 36 is formed on the surface of the semiconductor substrate 31 from which the gate oxide film 33 is removed by performing a selective oxidation process by rapid heat treatment on the semiconductor substrate 31.
여기서 상기 급속 열처리에 의한 선택 산화 공정은 800~950℃의 온도에서 10~120초간 실시하는데, H2O/H2(여기서 H2O : H2= 1 : 1 정도)분위기에서 1E-6~1의 분압으로 실시하며, 캐리어 가스(Carrier Gas)로 N2와 Ar을 사용한다.Wherein the selective oxidation process by rapid heat treatment is carried out for 10 to 120 seconds at a temperature of 800 ~ 950 ℃, H 2 O / H 2 (where H 2 O: H 2 = 1: 1) in the atmosphere 1E-6 ~ A partial pressure of 1 is used, and N 2 and Ar are used as carrier gases.
한편, 800℃ 이상의 급속 열처리에 의해 질화 텅스텐막(34)이 텅스텐(W)과 과잉질소로 분해되고, 1500~2000Å의 그레인 사이즈(Grain Size)를 갖는 게이트 전극(34a)이 형성된다.On the other hand, the tungsten nitride film 34 is decomposed into tungsten (W) and excess nitrogen by rapid heat treatment at 800 占 폚 or higher, and a gate electrode 34a having a grain size of 1500 to 2000 kPa is formed.
도 2e에 도시한 바와 같이, 상기 포토레지스트(35)를 제거하고, 상기 게이트 전극(34a)을 포함한 반도체 기판(31)의 전면에 절연막을 증착한 후, 전면에 에치백(Etch Back)공정을 실시하여 게이트 전극(34a)의 양측면에 절연막 측벽(37)을 형성한다.As shown in FIG. 2E, the photoresist 35 is removed, an insulating film is deposited on the entire surface of the semiconductor substrate 31 including the gate electrode 34a, and an etch back process is performed on the entire surface. The insulating film sidewall 37 is formed on both sides of the gate electrode 34a.
여기서 상기 에치백 공정시 상기 산화막(36)도 선택적으로 제거된다.In this case, the oxide layer 36 may be selectively removed during the etch back process.
한편, 상기 절연막 측벽(37)을 형성하기 전에 게이트 전극(34a) 양측의 반도체 기판(31) 표면내에 LDD(Lightly Doped Drain) 영역을 형성하고, 상기 절연막 측벽(37)을 형성한 후에 전면에 소오스/드레인용 불순물 이온을 주입하여 상기 게이트 전극(34a) 양측의 반도체 기판(31) 표면내에 LDD 구조를 갖는 소오스/드레인 불순물영역(38)을 형성한다.Meanwhile, before forming the insulating film sidewall 37, a lightly doped drain (LDD) region is formed in the surface of the semiconductor substrate 31 on both sides of the gate electrode 34a, and the source is formed on the entire surface of the insulating film sidewall 37. Source / drain impurity ions are implanted to form source / drain impurity regions 38 having an LDD structure in the surface of the semiconductor substrate 31 on both sides of the gate electrode 34a.
도 3은 텅스텐-실리콘-산소의 3성분계 상태도이다.3 is a three-component state diagram of tungsten-silicon-oxygen.
도 3에서와 같이 텅스텐의 일함수(Work Function)가 4.67eV로 실리콘의 미드 갭(Mid Gap) 부근이며, 텅스텐과 산화막(SiO2)이 열역학적으로 안정하므로 게이트 산화막(33)상에 텅스텐막을 바로 증착하는 텅스텐 게이트의 적용을 고려할 수 있다. 그리고 질화 텅스텐막(WNx)(34)이 800℃이상에서 텅스텐(W)과 과잉질소로 분해되어 실리콘-질소 본드(Si-N Bond)를 형성함으로써 선택 산화 공정중에 게이트 산화막(33)의 특성 저하를 방지할 수 있다.As shown in FIG. 3, the work function of tungsten is 4.67 eV, which is near the mid gap of silicon, and the tungsten and the oxide film (SiO 2 ) are thermodynamically stable, so the tungsten film is directly placed on the gate oxide film 33. Application of a tungsten gate to deposit may be considered. The tungsten nitride film (WNx) 34 is decomposed into tungsten (W) and excess nitrogen at 800 ° C. or higher to form a silicon-nitrogen bond (Si-N bond), thereby deteriorating the characteristics of the gate oxide film 33 during the selective oxidation process. Can be prevented.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 제조방법에 있어서 다음과 같은 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention has the following effects.
첫째, 질화 텅스텐막이 800℃이상에서 텅스텐(W)과 과잉질소로 분해되어 실리콘-질소 본드를 형성하므로 선택 산화 공정중에 게이트 산화 특성의 저하를 방지할 수 있다.First, since the tungsten nitride film is decomposed into tungsten (W) and excess nitrogen at 800 ° C. or higher to form a silicon-nitrogen bond, deterioration of the gate oxidation characteristic can be prevented during the selective oxidation process.
둘째, 급속 열처리에 의해 1500~2000Å의 그레인 사이즈를 갖는 게이트 전극을 형성함으로써 게이트 전극의 저항을 감소할 수 있다.Second, the resistance of the gate electrode can be reduced by forming a gate electrode having a grain size of 1500 to 2000 kV by rapid heat treatment.
따라서 급속 열처리에 의한 선택 산화를 통해 공정단순화와 게이트 저항 감소 및 소자 특성을 향상시킬 수 있다.Therefore, process oxidation, gate resistance reduction, and device characteristics can be improved through selective oxidation by rapid heat treatment.
Claims (9)
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