KR20000018723A - Method for forming metal wire of semiconductor device - Google Patents
Method for forming metal wire of semiconductor device Download PDFInfo
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- KR20000018723A KR20000018723A KR1019980036463A KR19980036463A KR20000018723A KR 20000018723 A KR20000018723 A KR 20000018723A KR 1019980036463 A KR1019980036463 A KR 1019980036463A KR 19980036463 A KR19980036463 A KR 19980036463A KR 20000018723 A KR20000018723 A KR 20000018723A
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- film
- metal
- pattern
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- semiconductor device
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 100
- 239000002184 metal Substances 0.000 title claims abstract description 100
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000010936 titanium Substances 0.000 claims abstract description 5
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000006396 nitration reaction Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로서, 보다 상세하게는 금속배선의 패턴(Pattern)의 형성시 브리지마진(Bridge Margin) 등을 용이하게 확보할 수 있는 반도체소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a method for forming metal wirings in a semiconductor device which can easily secure a bridge margin or the like when forming a pattern of metal wirings. It is about.
일반적으로 반도체소자는 상기 반도체소자로 제조할 수 있는 웨이퍼(Wafer) 즉, 반도체기판 상에 절연막 또는 금속막 등과 같은 막(Film)을 형성시킨 후, 상기 막을 반도체소자의 특성에 따른 패턴 등으로 형성시킴으로써 제조된다.In general, a semiconductor device is formed on a wafer that can be manufactured with the semiconductor device, that is, a film such as an insulating film or a metal film on a semiconductor substrate, and then the film is formed into a pattern according to the characteristics of the semiconductor device. It is prepared by making.
그리고 상기 반도체소자는 고집적화에 따른 디자인룰(Design Rule)의 미세화로 상기 반도체기판 상에 형성시키는 막들의 단차가 커져가고 있는 추세이다.In addition, the semiconductor device has a tendency of increasing the level of the film formed on the semiconductor substrate due to the miniaturization of the design rule according to the high integration.
여기서 상기 막 중에서 금속배선의 패턴으로 이루어지는 금속막은 그 단차 뿐만 아니라 전기적 저항 등을 낮추어야 하는 등의 난제를 동시에 해결해야 하는 문제를 내포하고 있다.In this case, the metal film formed of the pattern of the metal wiring has a problem of simultaneously solving the difficulties such as lowering the electric resistance and the like, as well as the step.
이러한 금속막은 그 전기적 저항 등을 낮추기 위하여 그 두께를 두껍게 형성시키는데, 상기 금속배선의 패턴인 바(Bar)형태의 패턴의 형성시 상기 바형태의 패턴과 패턴 사이의 스페이스(Space)인 브리지마진을 어느 정도로 확보하여야 하지만, 종래에는 상기 금속배선의 패턴의 하부에서 발생하는 풋(Foot)으로 인하여 상기 브리지마진을 용이하게 확보하지 못하였다.The metal film is formed to have a thick thickness in order to lower its electrical resistance, and the like. When forming a bar-shaped pattern which is a pattern of the metal wiring, a bridge margin, which is a space between the pattern and the bar-shaped pattern, is formed. Although it should be secured to some extent, the bridge margin has not been easily secured due to the foot generated under the pattern of the metal wiring.
또한 최근에는 막들간의 접착력의 향상을 위하여 경계금속막을 대부분의 반도체소자의 제조에 이용하기 때문에 그 두께가 더욱 두꺼워짐으로써 상기 브리지마진의 확보가 더욱 더 힘들었다.In addition, in recent years, since the boundary metal film is used in the manufacture of most semiconductor devices in order to improve the adhesion between the films, the thickness thereof becomes even thicker, thus making it difficult to secure the bridge margin.
이러한 금속배선의 패턴인 바형태의 패턴의 형성을 도1을 참조하여 살펴보면 먼저, 반도체기판(10) 상에 산화막 등과 같은 절연막(12)을 형성시킨 후, 상기 절연막(12)을 콘택홀(Contact Hole) 등을 포함하는 패턴으로 형성시킨다.Referring to FIG. 1, the formation of the bar-shaped pattern, which is a pattern of the metallization, is described below. First, an insulating film 12 such as an oxide film is formed on the semiconductor substrate 10, and then the insulating film 12 is contact hole. Hole) or the like.
그리고 상기 반도체기판(10)의 절연막(12) 상에 경계금속막(14) 및 금속막(16)을 순차적으로 형성시킨 후, 바형태의 금속배선의 패턴이 형성되도록 포토레지스트(Photoresist)(18)를 식각마스크로 이용하여 상기 금속막(16) 및 경계금속막(14)을 계속적으로 제거시킨다.After the boundary metal film 14 and the metal film 16 are sequentially formed on the insulating film 12 of the semiconductor substrate 10, a photoresist 18 is formed such that a pattern of a bar metal wiring is formed. ), The metal film 16 and the boundary metal film 14 are continuously removed.
여기서 상기 금속막(16) 및 경계금속막(14)의 계속적인 제거 즉, 상기 금속막(16) 및 경계금속막(14)의 식각선택비를 이용한 공정의 수행으로 인하여 종래에는 도1에 도시된 바와 같이 금속배선의 패턴의 하부(Ⅰ)에는 풋이 발생하였다.Here, due to the continuous removal of the metal film 16 and the boundary metal film 14, that is, performing a process using an etching selectivity of the metal film 16 and the boundary metal film 14, it is conventionally shown in FIG. As shown, a foot was generated in the lower part (I) of the pattern of metal wiring.
이러한 풋으로 인하여 상기 금속배선의 패턴과 패턴 사이의 브리지마진을 용이하게 확보하지 못하는 것이었다.Due to such a foot, it was not easy to secure the bridge margin between the pattern and the pattern of the metallization.
따라서 종래에는 금속배선의 패턴의 형성시 브리지마진 등을 용이하게 확보하지 못함에 따른 불량의 발생 등으로 인하여 반도체소자의 신뢰도가 저하되는 문제점이 있었다.Therefore, in the related art, reliability of a semiconductor device is deteriorated due to defects caused by failure to easily secure a bridge margin when forming a metal wiring pattern.
본 발명의 목적은, 금속배선의 패턴의 형성시 브리지마진 등을 용이하게 확보하여 이에 따른 불량의 발생을 최소화시킴으로써 반도체소자의 신뢰도를 향상시키기 위한 반도체소자의 금속배선 형성방법을 제공하는 데 있다.An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device for improving the reliability of the semiconductor device by easily securing the bridge margin, etc. when the pattern of the metal wiring pattern is formed, thereby minimizing the occurrence of defects.
도1은 종래의 반도체소자의 금속배선 형성방법에 따라 제조되는 반도체소자를 나타내는 단면도이다.1 is a cross-sectional view showing a semiconductor device manufactured by a metal wiring forming method of a conventional semiconductor device.
도2는 본 발명에 따른 반도체소자의 금속배선 형성방법의 일 실시예에 따라 제조되는 반도체소자를 나타내는 단면도이다.2 is a cross-sectional view illustrating a semiconductor device manufactured according to an embodiment of the method for forming metal wirings of the semiconductor device according to the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10, 20 : 반도체기판 12, 22 : 절연막10, 20: semiconductor substrate 12, 22: insulating film
14, 24 : 경계금속막 16, 26 : 금속막14, 24: boundary metal film 16, 26: metal film
18, 28 : 포토레지스트18, 28: photoresist
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 형성방법은, 콘택홀 등을 포함하는 패턴이 기 형성된 반도체기판의 절연막 상에 금속배선의 패턴으로 이루어질 경계금속막 및 금속막을 순차적으로 형성시키는 단계; 및 상기 금속배선의 패턴이 형성되도록 상기 금속막을 제거시킨 후, 상기 금속막의 제거로 노출되는 경계금속막은 등방성모드로 이루어지도록 상기 경계금속막을 제거시키는 단계를 구비하여 이루어지는 것을 특징으로 한다.In the method of forming a metal wiring of a semiconductor device according to the present invention for achieving the above object, a boundary metal film and a metal film formed of a pattern of a metal wiring are sequentially formed on an insulating film of a semiconductor substrate on which a pattern including a contact hole is formed. Making a step; And removing the boundary metal film such that the boundary metal film exposed by removing the metal film is in an isotropic mode after removing the metal film to form the pattern of the metal wiring.
여기서 상기 경계금속막은 티타늄막 및 질화티타늄막이 순차적으로 형성되는 다층막인 것이 그리고 상기 금속막은 알루미늄막인 것이 바람직하다.The boundary metal film is preferably a multilayer film in which a titanium film and a titanium nitride film are sequentially formed, and the metal film is an aluminum film.
이하, 본 발명의 구체적인 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2는 본 발명에 따른 반도체소자의 금속배선 형성방법의 일 실시예에 따라 제조되는 반도체소자를 나타내는 단면도이다.2 is a cross-sectional view illustrating a semiconductor device manufactured according to an embodiment of the method for forming metal wirings of the semiconductor device according to the present invention.
먼저, 도2는 반도체기판(20) 상에 산화막 등으로 이루어지는 절연막(22)이 형성되어 있고, 상기 절연막(22)의 상부에 금속배선의 패턴으로 이루어지는 경계금속막(24) 및 금속막(26)이 순차적으로 형성되어 있는 상태를 나타내고 있다.2, an insulating film 22 made of an oxide film or the like is formed on the semiconductor substrate 20, and the boundary metal film 24 and the metal film 26 made of a metal wiring pattern on the insulating film 22 are formed. ) Shows a state in which they are sequentially formed.
여기서 상기 경계금속막(24)은 티타늄막(Ti Film) 및 질화티타늄막(TiN Film)을 순차적으로 형성시킬 수 있고, 상기 금속막(26)은 알루미늄막(Al Film)을 형성시킬 수 있다.Here, the boundary metal film 24 may sequentially form a titanium film and a titanium nitride film, and the metal film 26 may form an aluminum film.
여기서 상기 경계금속막(24) 및 금속막(26)의 두께는 반도체소자의 특성 등을 고려하여 작업자가 임의로 결정할 수 있다.Here, the thickness of the boundary metal film 24 and the metal film 26 may be arbitrarily determined by the worker in consideration of characteristics of the semiconductor device.
이러한 구성으로 이루어지는 본 발명의 반도체소자의 금속배선의 패턴의 형성을 살펴보면, 먼저 반도체기판(20) 상에 산화막 등으로 이루어지는 절연막(22)을 형성시킨 후, 상기 절연막(22)을 콘택홀 등을 포함하는 패턴으로 형성시킨다.Looking at the formation of the pattern of the metal wiring of the semiconductor device of the present invention having such a configuration, first forming an insulating film 22 made of an oxide film or the like on the semiconductor substrate 20, and then contacting the insulating film 22 with a contact hole or the like. It forms in the pattern it contains.
그리고 상기 콘택홀 등을 포함하는 패턴으로 이루어진 절연막(22) 상에 금속배선의 패턴으로 이루어질 경계금속막(24) 및 금속막(26)을 순차적으로 형성시킨다.In addition, the boundary metal film 24 and the metal film 26 formed of the metal wiring pattern are sequentially formed on the insulating film 22 having the pattern including the contact hole.
계속해서 포토레지스트(28)를 식각마스크로 이용하여 상기 금속막(26)이 금속배선의 패턴으로 형성되도록 상기 금속막(26)을 식각 즉, 제거시킨다.Subsequently, using the photoresist 28 as an etching mask, the metal film 26 is etched, that is, removed so that the metal film 26 is formed in a pattern of metal wiring.
그리고 상기 금속배선의 패턴의 형성을 위한 금속막(26)의 제거로 노출이 이루어지는 경계금속막(24) 또한 상기와 같은 금속배선의 패턴이 형성되도록 포토레지스트(28)를 식각마스크로 이용하여 제거시킨다.The boundary metal film 24 exposed by the removal of the metal layer 26 for forming the pattern of the metal interconnection is also removed by using the photoresist 28 as an etching mask to form the pattern of the metal interconnection as described above. Let's do it.
여기서 본 발명은 상기 경계금속막(24)의 제거시 상기 경계금속막(24)이 등방성모드로 이루어지도록 제거시키는데, 이는 상기 경계금속막(24)의 제거시 그 특성을 이용하는 것이다.The present invention removes the boundary metal film 24 in isotropic mode when the boundary metal film 24 is removed, which uses its characteristics when the boundary metal film 24 is removed.
즉, 도2에 도시된 바와 같이 금속배선의 패턴의 하부(Ⅱ)에 형성되어 있는 경계금속막(24)을 리세스(Recess)시키는 것이다.That is, as shown in Fig. 2, the boundary metal film 24 formed in the lower portion II of the pattern of the metal wiring is recessed.
이에 따라 상기 금속막(26) 및 경계금속막(24)의 제거로써 금속배선의 패턴이 이루어지는데, 본 발명에서는 금속막(26) 및 경계금속막(24)의 식각선택비를 이용한 제거가 아니라 상기 경계금속막(24)의 제거에 따른 특성을 이용하여 등방성모드로 형성시키는 것이다.Accordingly, the metal wiring pattern is formed by removing the metal layer 26 and the boundary metal layer 24. In the present invention, the metal layer 26 and the boundary metal layer 24 are not removed using the etching selectivity. It is formed in the isotropic mode by using the characteristics of the removal of the boundary metal film 24.
따라서 본 발명은 상기 금속배선의 패턴의 형성시 상기 경계금속막(24)을 등방성모드로 형성시킴으로써, 상기 금속배선의 패턴 즉, 바형태의 패턴과 패턴 사이의 스페이스인 브리지마진을 용이하게 확보할 수 있다.Accordingly, in the present invention, the boundary metal film 24 is formed in an isotropic mode when the pattern of the metal wiring is formed, thereby easily securing the bridge margin, that is, the space between the pattern and the pattern of the bar wiring pattern. Can be.
즉, 본 발명은 상기 금속배선의 패턴의 형성에 따른 경계금속막(24)을 그 특성을 이용하여 등방성모드로 형성시킴으로써 종래의 금속배선의 패턴의 하부에 형성되는 풋을 제거시킬 수 있기 때문에 브리지마진을 용이하게 확보할 수 있는 것이다.That is, in the present invention, since the boundary metal film 24 according to the formation of the metal wiring pattern is formed in the isotropic mode by using the characteristics thereof, the foot formed under the pattern of the conventional metal wiring can be removed. The margin can be easily secured.
이에 따라 본 발명은 금속배선의 패턴으로 형성시키기 위한 경계금속막(24)의 제거시 그 특성을 이용하여 등방성모드로 형성시켜 브리지마진을 용이하게 확보함에 따라 상기 브리지마진 등으로 인한 불량의 발생을 최소화시킬 수 있다.Accordingly, in the present invention, when the boundary metal film 24 for forming the metal wiring pattern is removed, it is formed in an isotropic mode by using the characteristics thereof to easily secure the bridge margin, thereby preventing the occurrence of defects due to the bridge margin. It can be minimized.
따라서, 본 발명에 의하면 금속배선의 패턴의 형성시 브리지마진 등을 용이하게 확보하여 이에 따른 불량의 발생을 최소화시킴으로써 반도체소자의 신뢰도가 향상되는 효과가 있다.Therefore, according to the present invention, it is possible to easily secure a bridge margin when forming a pattern of the metal wiring, thereby minimizing the occurrence of defects, thereby improving the reliability of the semiconductor device.
이상에서 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980036463A KR20000018723A (en) | 1998-09-04 | 1998-09-04 | Method for forming metal wire of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980036463A KR20000018723A (en) | 1998-09-04 | 1998-09-04 | Method for forming metal wire of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000018723A true KR20000018723A (en) | 2000-04-06 |
Family
ID=19549581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980036463A KR20000018723A (en) | 1998-09-04 | 1998-09-04 | Method for forming metal wire of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000018723A (en) |
-
1998
- 1998-09-04 KR KR1019980036463A patent/KR20000018723A/en not_active Application Discontinuation
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