KR20000004510A - Method for manufacturing mos field effect transistors - Google Patents
Method for manufacturing mos field effect transistors Download PDFInfo
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- KR20000004510A KR20000004510A KR1019980025954A KR19980025954A KR20000004510A KR 20000004510 A KR20000004510 A KR 20000004510A KR 1019980025954 A KR1019980025954 A KR 1019980025954A KR 19980025954 A KR19980025954 A KR 19980025954A KR 20000004510 A KR20000004510 A KR 20000004510A
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000005669 field effect Effects 0.000 title abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- -1 E13 ion Chemical class 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 9
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 9
- 230000005465 channeling Effects 0.000 abstract description 5
- 230000000873 masking effect Effects 0.000 abstract 4
- 238000000137 annealing Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 50
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical group 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
Description
본 발명은 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOS FET라 칭함)의 제조방법에 관한 것으로서, 특히 게이트전극 패턴닝시 도전층의 일부 두께를 남겨둔 상태에서 엘.디.디(lightly doped drain; 이하 LDD라 칭함) 이온주입을 실시하고 후속 공정을 진행하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 MOSFET의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a metal oxide semiconductor field effect transistor (hereinafter, referred to as a MOS FET), and particularly, in the state of leaving some thickness of the conductive layer during the gate electrode patterning, lightly. doped drain (hereinafter referred to as LDD) The present invention relates to a method for manufacturing a MOSFET capable of improving the process yield and device reliability by performing ion implantation and subsequent processes.
반도체소자가 고집적화되어 감에 따라 소자의 크기를 감소시키기 위하여 MOSFET의 게이트전극이나 소오스/드레인영역 및 이들과의 콘택등 공정 전반의 디자인 룰이 감소되고 있으나, 게이트전극의 폭과 전기저항은 비례 관계에 있어 폭이 N배 줄어들면 전기 저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다. 따라서 게이트전극의 저항을 감소시키기 위하여 가장 안정적인 MOSFET 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조인 폴리사이드가 저 저항 게이트로서 사용하기도 한다.As semiconductor devices become more integrated, the overall design rules such as gate electrodes, source / drain regions of MOSFETs, and contacts with them are decreasing to reduce the size of the devices, but the width and electrical resistance of the gate electrodes are proportional to each other. When the width is reduced by N times, the electrical resistance is increased by N times, which causes a problem of lowering the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, the polysilicon, which is a laminated structure of the polysilicon layer and the silicide, may be used as the low resistance gate by using the characteristics of the polysilicon layer / oxide layer interface having the most stable MOSFET characteristics.
또한 p 또는 n형 반도체기판에 n 또는 p형 불순물로 형성되는 pn 접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다. 따라서 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면 확산에 의한 짧은채널효과(short channel effect)를 방지하기 위하여 접합깊이를 얕게 형성하여야 하며, 드레인으로의 전계 집중에 의한 접합 파괴 방지와 열전하효과에 의한 문턱전압 변화를 방지하기 위하여 소오스/드레인 영역을 저농도 불순물 영역을 갖는 LDD 구조로 형성하는 등의 방법이 사용된다.In addition, a pn junction formed of n or p type impurity on a p or n type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in the semiconductor device with reduced channel width, the junction depth should be shallow to prevent short channel effect due to side diffusion from the diffusion region. In order to prevent the threshold voltage change due to the lowering effect, a method such as forming a source / drain region into an LDD structure having a low concentration impurity region is used.
종래의 기술에 따른 nMOSFET의 제조방법을 살펴보면 다음과 같다.Looking at the manufacturing method of the nMOSFET according to the prior art as follows.
먼저, p형 실리콘 웨이퍼 반도체 기판상에 게이트산화막을 형성하고, 상기 게이트산화막상에 절연층 패턴인 마스크 산화막이 중첩되어 있는 다결정실리콘층 패턴으로된 게이트전극을 형성한 후, 상기 구조의 반도체기판을 열처리하여 반도체기판과 게이트전극의 표면에 열산화막을 형성한다. 상기 열산화막은 LDD 이온주입에 따른 채널링 현상을 방지하기 위한 것으로서, 접합의 깊이가 얕아지고, 게이트산화막의 두께가 얇아짐에 따른 이온주입 조절층으로 사용되는 것이다.First, a gate oxide film is formed on a p-type silicon wafer semiconductor substrate, and a gate electrode having a polysilicon layer pattern in which a mask oxide film as an insulating layer pattern is overlapped is formed on the gate oxide film. The thermal treatment forms a thermal oxide film on the surfaces of the semiconductor substrate and the gate electrode. The thermal oxide film is used to prevent the channeling phenomenon due to LDD ion implantation. The thermal oxide film is used as an ion implantation control layer as the junction depth becomes shallower and the gate oxide film becomes thinner.
그다음 상기 게이트전극 양측의 반도체기판에 LDD 영역이 되는 저농도 불순물영역을 형성하고, 상기 게이트전극의 측벽에 산화막 스페이서를 형성한 후, 상기 산화막 스페이서 양측의 반도체기판에 고농도 불순물로 소오스/드레인 영역을 형성한다.A low concentration impurity region serving as an LDD region is formed on the semiconductor substrates on both sides of the gate electrode, and an oxide spacer is formed on the sidewalls of the gate electrode, and then source / drain regions are formed on the semiconductor substrates on both sides of the oxide spacer with high concentration impurities. do.
상기와 같은 종래 기술에 따른 MOSFET의 제조방법은 게이트전극 패턴닝 후에 기판을 장시간, 예를들어 1∼10시간 열처리하여 기판과 다결정실리콘층의 표면에 LDD 이온주입 조절층으로서의 열산화막을 형성하고 LDD 이온주입을 실시하여 채널링을 방지하고 있으나, 상기의 열처리 공정이 장시간 필요하므로 공정수율이 떨어지고, 기판의 표면이 산화되므로 접합 두께가 감소하여 트랜지스터의 특성을 저하시키며, 게이트전극을 실리사이드, 예를들어 텅스텐 실리사이드로 형성하면, 열처리 공정시 텅스텐 실리사이드가 비정상적으로 성장하여 스파이킹등에 의해 소자의 신뢰성이 떨어지는 등의 문제점이 있다.In the method of manufacturing a MOSFET according to the prior art as described above, the substrate is heat-treated for a long time, for example, for 1 to 10 hours after the gate electrode patterning to form a thermal oxide film as an LDD ion implantation control layer on the surface of the substrate and the polysilicon layer, and LDD Although ionization is performed to prevent channeling, the above heat treatment process is required for a long time, so the yield of the process decreases, and the surface of the substrate is oxidized, so that the junction thickness decreases, thereby degrading the characteristics of the transistor and silicide, for example, the gate electrode. If it is formed of tungsten silicide, there is a problem that the tungsten silicide grows abnormally during the heat treatment process and the reliability of the device is lowered due to spiking.
본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 LDD 이온주입시의 조절층으로서 게이트전극 패턴닝시 일부 두께가 남겨진 다결정실리콘층을 사용함으로써, LDD 이온주입시의 채널링을 방지함은 물론 열공정에 따른 시간을 감소시켜 공정수율을 향상시키고, 접합 깊의 감소를 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 MOSFET의 제조방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to prevent channeling at the time of LDD ion implantation by using a polysilicon layer having some thickness remaining at the gate electrode patterning as a control layer at the time of LDD ion implantation. In addition, to improve the process yield by reducing the time according to the thermal process, and to provide a method of manufacturing a MOSFET that can improve the process yield and the reliability of the device operation by preventing the reduction of the junction depth.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 MOSFET의 제조공정도.1A to 1E are diagrams illustrating a manufacturing process of a MOSFET according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
10 : 반도체 기판 12 : 게이트절연막10 semiconductor substrate 12 gate insulating film
13 : 다결정실리콘층 14 : 텅스텐실리사이드층13: polycrystalline silicon layer 14: tungsten silicide layer
15 : 산화막 16 : 산화질화막15 oxide film 16 oxynitride film
18 : 감광막패턴 20 : 저농도 불순물영역18: photoresist pattern 20: low concentration impurity region
상기 목적을 달성하기 위한 본 발명에 따른 MOSFET 제조방법의 특징은,Features of the MOSFET manufacturing method according to the present invention for achieving the above object,
반도체기판상에 게이트절연막을 형성하는 공정과,Forming a gate insulating film on the semiconductor substrate;
상기 게이트절연막상에 도전층과 마스크 산화막을 형성하는 공정과,Forming a conductive layer and a mask oxide film on the gate insulating film;
상기 마스크 산화막상에 게이트 패턴닝 마스크를 형성하는 공정과,Forming a gate patterning mask on the mask oxide film;
상기 게이트 패턴닝 마스크에 의해 노출되어있는 마스크 산화막을 제거하여 도전층을 노출시키는 마스크 산화막 패턴을 형성하는 공정과,Removing a mask oxide film exposed by the gate patterning mask to form a mask oxide film pattern exposing a conductive layer;
상기 게이트 패턴닝 마스크를 제거하고, 마스크 산화막 패턴에 의해 노출되어있는 도전층을 식각하되, 상기 도전층의 일정 두께가 남도록하는 공정과,Removing the gate patterning mask and etching the conductive layer exposed by the mask oxide layer pattern to leave a predetermined thickness of the conductive layer;
상기 일정두께가 남은 도전층 하부의 반도체기판에 LDD 저농도 이온주입을 실시하는 공정과,Performing LDD low concentration ion implantation into the semiconductor substrate under the conductive layer having the predetermined thickness;
상기 남아 있는 두께의 도전층을 제거하여 도전층 패턴으로된 게이트전극을 형성하는 공정과,Removing the remaining conductive layer to form a gate electrode having a conductive layer pattern;
상기 게이트전극과 마스크 산화막 패턴의 측벽에 절연 스페이서를 형성하는 공정과,Forming an insulating spacer on sidewalls of the gate electrode and the mask oxide film pattern;
상기 절연 스페이서 양측의 반도체기판에 고농도 불순물을 주입하여 소오스/드레인영역을 형성하는 공정을 구비함에 있다.And forming a source / drain region by injecting high concentration impurities into the semiconductor substrates on both sides of the insulating spacer.
이하, 첨부된 도면을 참조하여 본 발명에 따른 MOSFET의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a MOSFET according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 MOSFET의 제조 공정도이다.1A to 1E are process diagrams for fabricating a MOSFET according to an embodiment of the present invention.
먼저, 실리콘 웨이퍼로된 제1도전형 , 예를들어 p형의 반도체기판(10)상에 산화막이나 질화막 또는 산화막-질화막의 게이트 절연막(12)을 50∼150Å 정도 두께로 형성하고, 상기 게이트절연막(12)상에 다결정실리콘층(13)과 텅스텐 실리사이드층(14), 산화막(15) 및 산화질화막(16)을 순차적으로 형성한다. 여기서 상기 다결정실리콘층(13)과 텅스텐 실리사이드층(14)은 도전층으로서 저저항 게이트가 되는데, 텅스텐실리사이드 대신 Ti, Ta, Cr, Mo 또는 Sn등의 실리사이드 가능한 금속층으로 형성할 수 있으며, 상기 다결정실리콘층(13) 대신 비정질 실리콘층으로 형성할 수도 있고, 다결정실리콘 단일층으로서 형성할 수도 있으며, 다결정실리콘층과 비정질실리콘층은 500∼800℃에서 형성하며, 상기 산화막(15)과 산화질화막(16)은 마스크 산화막과 반사방지막으로서 어느 하나의 절연막으로 형성하거나 순서를 바꾸어 형성할 수도 있다. (도 1a 참조).First, a gate insulating film 12 of an oxide film, a nitride film, or an oxide film-nitride film is formed to a thickness of about 50 to 150 상 에 on a first conductive type, for example, a p-type semiconductor substrate 10 made of a silicon wafer, and the gate insulating film Polycrystalline silicon layer 13, tungsten silicide layer 14, oxide film 15 and oxynitride film 16 are sequentially formed on (12). Here, the polycrystalline silicon layer 13 and the tungsten silicide layer 14 serve as a low resistance gate as a conductive layer. Instead of tungsten silicide, the polycrystalline silicon layer 13 and the tungsten silicide layer 14 may be formed of a silicide capable metal layer such as Ti, Ta, Cr, Mo, or Sn. Instead of the silicon layer 13, an amorphous silicon layer may be formed, or a polysilicon single layer may be formed. The polysilicon layer and the amorphous silicon layer may be formed at 500 to 800 ° C, and the oxide film 15 and the oxynitride film ( 16 is a mask oxide film and an anti-reflection film, and may be formed of any one of insulating films or in a reversed order. (See FIG. 1A).
그다음 상기 산화질화막(16)상에 게이트 패턴닝 마스크인 감광막패턴(18)을 형성하고, (도 1b 참조), 상기 감광막패턴(18)에 의해 노출되어있는 산화질화막(16)에서 다결정실리콘층(13)까지 순차적으로 식각하되, 상기 다결정실리콘층(13)은 일부두께, 예를들어 20∼100Å 정도가 남도록 하여 남아 있는 부분이 이온주입 조절층이 되도록한다. 여기서 상기에서는 감광막패턴(18)을 계속적인 식각마스크로 사용하였으나, 다른 방법으로서 감광막패턴(18)을 마스크로 산화질화막(16)과 산화막(15)을 식각한 후에는 감광막패턴(18)을 제거하고, 산화질화막(16) 패턴을 하드마스크로하여 나머지층을 식각할 수도 있다. (도 1c 참조).Next, a photoresist pattern 18 as a gate patterning mask is formed on the oxynitride layer 16 (see FIG. 1B), and a polysilicon layer (in the oxynitride layer 16 exposed by the photoresist pattern 18) is formed. 13) are sequentially etched, but the polysilicon layer 13 has a part thickness, for example, about 20 to 100Å, so that the remaining part becomes an ion implantation control layer. Here, the photoresist pattern 18 is used as a continuous etching mask. Alternatively, after the photoresist pattern 18 is etched using the photoresist pattern 18 as a mask, the photoresist pattern 18 is removed. The remaining layer may be etched using the oxynitride film 16 pattern as a hard mask. (See FIG. 1C).
그후, 상기 감광막패턴(18)을 제거한 후, 상기 다결정실리콘층(13)이 일부 남아 있는 부분 하부의 반도체기판(10)에 제2도전형, 예를들어 n형 불순물을 10∼30keV, 0.5∼2.0E13 ion/㎠의 도우즈로 주입하여 LDD의 저농도 불순물영역(20)을 형성하고, (도 1d 참조), 상기 산화질화막(16) 패턴과 다결정실리콘층(13)의 식각선택비차를 이용하여저농도 불순물영역위에 남아 있는 다결정실리콘층(13)을 제거하여 텅스텐 실리사이드층(14)과 다결정실리콘층(13) 패턴이 적층되어있는 구조의 최종 게이트전극을 형성한다. (도 1e 참조).Thereafter, after the photoresist layer pattern 18 is removed, a second conductive type, for example, n-type impurity, is contained in the semiconductor substrate 10 under the part where the polysilicon layer 13 remains, 10 to 30 keV, 0.5 to A low concentration impurity region 20 of LDD is formed by implanting into a dose of 2.0E13 ion / cm 2 (see FIG. 1D), and using the etching selectivity difference between the oxynitride layer 16 pattern and the polysilicon layer 13. The polysilicon layer 13 remaining on the low concentration impurity region is removed to form a final gate electrode having a structure in which a tungsten silicide layer 14 and a polysilicon layer 13 pattern are stacked. (See FIG. 1E).
그다음 도시되어 있지는 않으나, 상기 게이트전극과 그 상부의 절연막 패턴들의 측벽에 테오스나 비피에스지산화막등으로된 절연 스페이서를 형성하고, 절연 스페이서 양측의 반도체기판에 n형 고농도 불순물로 소오스/드레인영역을 형성한다.Next, although not shown, an insulating spacer made of a theos or BPS oxide film is formed on the sidewalls of the gate electrode and the insulating layer patterns thereon, and source / drain regions are formed on the semiconductor substrate on both sides of the insulating spacer with n-type high concentration impurities. do.
상기한 바와같이 본 발명에 따른 MOSFET의 제조방법은 게이트전극 패턴닝시 도전층의 일부 두께를 남겨둔 상태에서 이온주입 조절층으로 사용하여 LDD를 위한 저농도 이온주입을 실시하고, 후속 공정에서 남겨진 도전층을 제거하고 MOSFET를 형성하였으므로, LDD 이온주입에 따른 채널링을 방지함을 물론 종래 장시간에 걸친 열처리 공정이 제거되어 수율이 향상되고, 열산화에 따른 접합 깊이의 감소도 방지되어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the MOSFET manufacturing method according to the present invention, a low-concentration ion implantation for LDD is performed by using an ion implantation control layer in a state in which a part of the conductive layer is left in the gate electrode patterning, and the conductive layer left in a subsequent process Since MOSFETs are formed and MOSFETs are formed, not only channeling due to LDD ion implantation is prevented, but also the conventional heat treatment process for a long time is eliminated, and the yield is improved, and the reduction of the junction depth due to thermal oxidation is also prevented. There is an advantage to improve the reliability.
Claims (8)
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| KR1019980025954A KR20000004510A (en) | 1998-06-30 | 1998-06-30 | Method for manufacturing mos field effect transistors |
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| KR1019980025954A KR20000004510A (en) | 1998-06-30 | 1998-06-30 | Method for manufacturing mos field effect transistors |
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