KR20000027642A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20000027642A KR20000027642A KR1019980045598A KR19980045598A KR20000027642A KR 20000027642 A KR20000027642 A KR 20000027642A KR 1019980045598 A KR1019980045598 A KR 1019980045598A KR 19980045598 A KR19980045598 A KR 19980045598A KR 20000027642 A KR20000027642 A KR 20000027642A
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- Prior art keywords
- forming
- semiconductor substrate
- source
- gate electrode
- insulating spacer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 125000006850 spacer group Chemical group 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOS FET라 칭함) 제조시 두차례에 거친 스페이서 형성 및 엘.디.디(lightly doped drain; 이하 LDD라 칭함) 이온주입으로 채널 폭이 감소되어도 소오스/드레인간 펀치를 방지하고, 게이트전극과 소오스/드레인 콘택플러그와의 누설전류를 억제하며, 인접 소자와의 펀치를 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and in particular, to fabricating a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET), two times of spacer formation and lightly doped drain; LDD) Ion implantation prevents source / drain punches even when the channel width is reduced, suppresses leakage current between gate electrodes and source / drain contact plugs, and prevents punches between adjacent devices, resulting in process yield and device The present invention relates to a semiconductor device manufacturing method capable of improving the reliability of the operation.
반도체소자가 고집적화되어 감에 따라 소자의 크기를 감소시키기 위하여 MOSFET의 게이트전극이나 소오스/드레인영역 및 이들과의 콘택등 공정 전반의 디자인 룰이 감소되고 있으나, 게이트전극의 폭과 전기저항은 비례 관계에 있어 폭이 N배 줄어들면 전기 저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다. 따라서 게이트전극의 저항을 감소시키기 위하여 가장 안정적인 MOSFET 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조인 폴리사이드가 저 저항 게이트로서 사용하기도 한다.As semiconductor devices become more integrated, the overall design rules such as gate electrodes, source / drain regions of MOSFETs, and contacts with them are decreasing to reduce the size of the devices, but the width and electrical resistance of the gate electrodes are proportional to each other. When the width is reduced by N times, the electrical resistance is increased by N times, which causes a problem of lowering the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, the polysilicon, which is a laminated structure of the polysilicon layer and the silicide, may be used as the low resistance gate by using the characteristics of the polysilicon layer / oxide layer interface having the most stable MOSFET characteristics.
또한 p 또는 n형 반도체기판에 n 또는 p형 불순물로 형성되는 pn 접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다. 따라서 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면 확산에 의한 짧은채널효과(short channel effect)를 방지하기 위하여 접합깊이를 얕게 형성하여야 하며, 드레인으로의 전계 집중에 의한 접합 파괴 방지와 열전하효과에 의한 문턱전압 변화를 방지하기 위하여 소오스/드레인 영역을 저농도 불순물 영역을 갖는 LDD 구조로 형성하는 등의 방법이 사용된다.In addition, a pn junction formed of n or p type impurity on a p or n type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in the semiconductor device with reduced channel width, the junction depth should be shallow to prevent short channel effect due to side diffusion from the diffusion region. In order to prevent the threshold voltage change due to the lowering effect, a method such as forming a source / drain region into an LDD structure having a low concentration impurity region is used.
종래의 기술에 따른 MOSFET의 제조방법을 살펴보면 다음과 같다.Looking at the MOSFET manufacturing method according to the prior art as follows.
먼저, p형 실리콘 웨이퍼 반도체 기판상에 게이트산화막을 형성하고, 상기 게이트산화막상에 절연층 패턴인 마스크 산화막이 중첩되어 있는 다결정실리콘층 패턴으로된 게이트전극을 형성한 후, 상기 게이트전극 양측의 반도체기판에 LDD 영역이 되는 저농도 불순물영역을 형성하고, 상기 게이트전극의 측벽에 산화막 스페이서를 형성한 후, 상기 산화막 스페이서 양측의 반도체기판에 고농도 불순물로 소오스/드레인 영역을 형성한다.First, a gate oxide film is formed on a p-type silicon wafer semiconductor substrate, and a gate electrode having a polysilicon layer pattern in which a mask oxide film as an insulating layer pattern is overlapped is formed on the gate oxide film, and then semiconductors on both sides of the gate electrode are formed. A low concentration impurity region serving as an LDD region is formed on the substrate, and an oxide spacer is formed on sidewalls of the gate electrode, and then source / drain regions are formed on the semiconductor substrates on both sides of the oxide spacer with high concentration impurities.
상기와 같은 종래 기술에 따른 MOSFET의 제조방법은 채널폭이 작아지면, LDD 영역 형성을 위한 이온주입시 소오스/드레인간 펀치가 일어나거나, 게이트전극과 소오스/드레인 콘택 플러그간의 누설전류가 증가되는 등의 문제점이 있어 이를 방지하기 위하여 게이트전극 패터닝후 반도체기판을 열처리하여 반도체기판과 게이트전극의 표면에 열산화막을 형성하고, 이온주입을 실시하는데, 상기 열산화막은 LDD 이온주입에 따른 채널링 현상을 방지하기 위한 것으로서, 접합의 깊이가 얕아지고, 게이트산화막의 두께가 얇아짐에 따른 이온주입 조절층으로 사용되고 있으나, 상기의 얼처리 공정이 장시간 필요하므로 공정수율이 떨어지고, 기판의 표면이 산화되므로 접합 두께가 감소하여 트랜지스터의 특성을 저하시키며, 게이트전극을 실리사이드, 예를들어 텅스텐 실리사이드로 형성하면, 열처리 공정시 텅스텐 실리사이드가 비정상적으로 성장하여 스파이킹등에 의해 소자의 신뢰성이 떨어지는 등의 다른 문제점이 있다.In the method of manufacturing a MOSFET according to the related art as described above, when the channel width decreases, source / drain punches occur during ion implantation to form an LDD region, or leakage current between the gate electrode and the source / drain contact plug increases. In order to prevent this problem, heat-treat the semiconductor substrate after patterning the gate electrode to form a thermal oxide film on the surface of the semiconductor substrate and the gate electrode, and perform ion implantation. The thermal oxide film prevents channeling due to LDD ion implantation. It is to be used as an ion implantation control layer as the depth of the junction becomes shallower and the gate oxide film becomes thinner, but the process yield is lowered because the above-mentioned anneal process is necessary for a long time, and the surface of the substrate is oxidized so that the junction thickness Decreases the transistor's properties, and the gate electrode suicides, When formed of tungsten silicide, there are other problems such as abnormal growth of tungsten silicide during the heat treatment process, resulting in poor reliability of the device due to spiking.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 게이트전극의 측벽에 일차로 절연 스페이서를 형성하고, LDD 이온주입을 실시한 후에 이차 절연 스페이서를 형성하고, 후속공정을 진행하여, 채널폭 감소에 의한 LDD 이온주입에 따른 소오스/드레인간 판치나 게이트전극과 소오스/드레인 콘택 플러그간 누설전류를 방지하고, 인접한 트랜지스터간의 펀치도 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to form an insulating spacer first on the sidewall of the gate electrode, and after the LDD ion implantation to form a secondary insulating spacer, to proceed to the subsequent process, It is possible to improve process yield and device operation reliability by preventing source / drain plate separation or leakage current between gate electrode and source / drain contact plug due to LDD ion implantation by reducing channel width and preventing punch between adjacent transistors. The present invention provides a method for manufacturing a semiconductor device.
도 1a 내지 도 1d은 본 발명의 실시예에 따른 반도체소자의 제조공정도.1A to 1D are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 반도체 기판 12 : 게이트절연막10 semiconductor substrate 12 gate insulating film
13 : 다결정실리콘층 14 : 실리사이드막13 polysilicon layer 14 silicide film
15 : 마스크 산화막 16 : 질화막15 mask oxide film 16 nitride film
17 : 감광막패턴 18 : 제1절연스페이서17 photosensitive film pattern 18: the first insulating spacer
19 : 저농도 불순물영역 20 : 제2절연스페이서19: low concentration impurity region 20: second insulating spacer
21 : 제2다결정실리콘층 22 : 제3다결정실리콘층21: second polycrystalline silicon layer 22: third polycrystalline silicon layer
23 : 소오스/드레인영역23: source / drain area
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은,Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
제1도전형의 반도체기판상에 게이트절연막을 형성하는 공정과,Forming a gate insulating film on the first conductive semiconductor substrate;
상기 게이트절연막상에 마스크 절연막 패턴과 중첩되어있는 게이트전극을 형성하는 공정과,Forming a gate electrode overlapping the mask insulating film pattern on the gate insulating film;
상기 마스크절연막 패턴 및 게이트전극의 측벽에 제1절연스페이서를 형성하는 공정과,Forming a first insulating spacer on sidewalls of the mask insulating film pattern and the gate electrode;
상기 제1절연스페이서 양측의 반도체기판에 제2도전형 불순물로 LDD 저농도불순물영역을 형성하는 공정과,Forming an LDD low concentration impurity region as a second conductive impurity in the semiconductor substrates on both sides of the first insulating spacer;
상기 제1절연스페이서의 바깥쪽에 제2절연스페이서를 형성하는 공정과,Forming a second insulating spacer on an outer side of the first insulating spacer;
상기 반도체기판의 소오스/드레인영역으로 예정되어 있는 부분과 접촉되는 콘택플러그를 형성하되, 진성 다결정실리콘층과 제2도전형의 불순물이 고농도로 도핑된 다결정실리콘층 패턴의 적층 구조로 형성하는 공정과,Forming a contact plug in contact with a predetermined portion of the semiconductor substrate as a source / drain region, and forming a stacked structure of an intrinsic polysilicon layer and a polysilicon layer pattern doped with a high concentration of impurities of a second conductivity type; ,
상기 구조의 반도체기판을 열처리하여 반도체기판에 고농도불순물로된 소오스/드레인영역을 형성하는 공정을 구비함에 있다.And heat-treating the semiconductor substrate having the above structure to form a source / drain region of high concentration impurity on the semiconductor substrate.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 미세패턴 제조방법에 대하여 상세히 설명하기로 한다.Hereinafter, a method for manufacturing a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체소자의 제조공정도이다.1A to 1D are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.
먼저, 제1도전형, 예를들어 P형 실리콘 반도체기판(10)상에 산화막, 질화막 또는 산화막/질화막 적층 구조의 게이트절연막(12)을 형성하고, 상기 게이트절연막(12)상에 제1다결정실리콘층(13)과 실리사이드막(14), 마스크산화막(15) 및 질화막(16)을 순차적으로 형성한다. 상기 제1다결정실리콘층(13)과 실리사이드막(14)은 게이트전극이 되는 도전층으로서, 실리사이드는 Ti, Cr, Mo, Sn, Ta, W등으로 형성하며, 상기 질화막(16)은 후속 공정을 위한 반사방지막 및 식각장벽 역할을 한다.First, a gate insulating film 12 having an oxide film, a nitride film, or an oxide / nitride film stacked structure is formed on a first conductive type, for example, a P-type silicon semiconductor substrate 10, and a first polycrystal is formed on the gate insulating film 12. The silicon layer 13, the silicide film 14, the mask oxide film 15, and the nitride film 16 are sequentially formed. The first polysilicon layer 13 and the silicide layer 14 are conductive layers serving as gate electrodes. The silicide layer is formed of Ti, Cr, Mo, Sn, Ta, W, and the like, and the nitride layer 16 is a subsequent process. It acts as an anti-reflection film and etch barrier.
그다음 상기 질화막(16)상에 게이트 패터닝 마스크인 감광막패턴(17)을 형성하고, 상기 감광막패턴(17)에 의해 노출되어있는 질화막(16)에서 다결정실리콘층(13)까지를 순차적으로 제거하여 제1다결정실리콘층(13)과 실리사이드막(14) 패턴으로된 게이트전극과 그 상부에 적층되어 있는 마스크산화막(15) 및 질화막(16) 패턴을 형성한다. (도 1a 참조).Next, a photoresist pattern 17 as a gate patterning mask is formed on the nitride layer 16, and the polysilicon layer 13 is sequentially removed from the nitride layer 16 exposed by the photoresist layer pattern 17. A gate electrode composed of a single polysilicon layer 13 and a silicide film 14 pattern and a mask oxide film 15 and a nitride film 16 stacked thereon are formed. (See FIG. 1A).
그후, 상기 감광막패턴(17)을 제거하고, 상기 패턴들의 측벽에 통상의 스페이서 형성방법으로 제1절연스페이서(18)를 산화막 재질로 형성한 후, 상기 제1절연스페이서 양측의 반도체기판(10)에 제2도전형, 예를들어 n형 불순물로 LDD 구조의 저농도 불순물영역(19)을 형성한다. (도 1b 참조).Thereafter, the photoresist layer pattern 17 is removed, and a first insulating spacer 18 is formed of an oxide film on a sidewall of the patterns by a conventional spacer forming method, and then the semiconductor substrates 10 on both sides of the first insulating spacer are formed. The low concentration impurity region 19 of the LDD structure is formed of a second conductive type, for example, an n-type impurity. (See FIG. 1B).
그다음 상기 제1절연스페이서(18)의 외부벽에 제2절연스페이서(20)를 산화막 재질로 형성하고, 상기 구조의 전표면에 제2다결정실리콘층(21)과 제3다결정실리콘층(22)을 순차적으로 도포하되, 상기 제2다결정실리콘층(21)은 비교적 얇은 두께로서 도핑되지 않은 진성 다결정실리콘이고, 제3다결정실리콘층(22)은 두껍게 형성하며, n형 불순물이 충분한 농도로 도핑되어있다. (도 1c 참조).Then, a second insulating spacer 20 is formed on the outer wall of the first insulating spacer 18 by an oxide film material, and the second polycrystalline silicon layer 21 and the third polycrystalline silicon layer 22 are formed on the entire surface of the structure. Is applied sequentially, the second polysilicon layer 21 is a relatively thin thickness of undoped intrinsic polysilicon, the third polysilicon layer 22 is formed thick, the n-type impurities are doped to a sufficient concentration have. (See FIG. 1C).
그후, 상기 게이트전극 상부의 제3 및 제2다결정실리콘층(22,21)을 순차적으로 제거하여 반도체기판(10)과 접촉되는 제2 및 제3다결정실리콘층(21,22) 패턴으로된 콘택플러그를 형성한 후, 상기 기판을 열처리하여 상기 제3다결정실리콘층(22) 패턴내의 불순물을 반도체기판(10)에 확산시켜 n+소오스/드레인영역(23)을 형성한다. 여기서 상기 스페이서가 두 번에 걸쳐 두껍게 형성되고, 제2다결정실리콘층(21)이 도핑되지 않았으므로 게이트전극과 콘택 플러그간의 누설전류가 억제되며, 도핑되지 않은 제2다결정실리콘층(21)에 의해 소오스/드레인간의 펀치 발생 가능성이 감소되며, 확산에 의해 소오스/드레인영역이 형성되므로 저농도 부분을 침투하는 것이나 인접소자간의 펀치도 방지한다. (도 1d 참조).Thereafter, the third and second polysilicon layers 22 and 21 on the gate electrode are sequentially removed to contact the second and third polysilicon layers 21 and 22 to be in contact with the semiconductor substrate 10. After the plug is formed, the substrate is heat-treated to diffuse impurities in the third polysilicon layer 22 pattern onto the semiconductor substrate 10 to form n + source / drain regions 23. In this case, the spacer is formed thick twice, and since the second polysilicon layer 21 is not doped, the leakage current between the gate electrode and the contact plug is suppressed, and the second polycrystalline silicon layer 21 is not doped. The possibility of punch generation between the source and drain is reduced, and since source / drain regions are formed by diffusion, penetration of low concentration portions and punching between adjacent elements are also prevented. (See FIG. 1D).
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 게이트전극의 측벽에 제1절연스페이서를 형성하고, 기판에 LDD 이온주입을 실시한 후, 제2절연 스페이서를 형성하고, 고농도로 도핑된 다결정실리콘층패턴으로 소오스/드레인영역으로 예정된 반도체기판과 접촉되는 콘택 플러그를 형성하고, 열처리에 의해 불순물을 확산시켜 소오스/드레인의 고농도 불순물영역을 형성하였으므로, 미세한 채널폭을 갖는 MOSFET를 형성하여도 소오스/드레인간 펀치가 방지되며, 두 개의 스페이서로 인하여 게이트전극과 콘택플러그간의 누설전류는 감소되고, 콘택 플러그의 구성을 도핑되지 않은 다결정실리콘층과 고농도 도핑된 다결정실리콘층으로 구성하여 게이트전극과 콘택플러그간 누설전류 감소 효과 뿐만아니라 고농도 이온주입에 의한 저농도 부분의 침투가 방지되고 인접소자와의 펀치를 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a first insulating spacer is formed on sidewalls of a gate electrode, LDD ion implantation is performed on a substrate, a second insulating spacer is formed, and is heavily doped. A contact plug in contact with a semiconductor substrate, which is intended as a source / drain region, was formed using a polysilicon layer pattern, and impurities were diffused by heat treatment to form a high concentration impurity region of the source / drain. Thus, a MOSFET having a fine channel width was formed. The source / drain punch is prevented, and the two spacers reduce the leakage current between the gate electrode and the contact plug, and the contact plug consists of an undoped polysilicon layer and a highly doped polysilicon layer. In addition to reducing leakage current between contact plugs, There is an advantage that the penetration of the concentration portion is prevented and the punch with the adjacent element is prevented to improve the process yield and the reliability of the element operation.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045598A KR20000027642A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045598A KR20000027642A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR20000027642A true KR20000027642A (en) | 2000-05-15 |
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| KR1019980045598A KR20000027642A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing semiconductor device |
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| KR (1) | KR20000027642A (en) |
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1998
- 1998-10-28 KR KR1019980045598A patent/KR20000027642A/en not_active Application Discontinuation
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