KR20000000858A - Self-aligned silicide transistor and method therof - Google Patents

Abstract

PURPOSE: A self-aligned silicide transistor having a shallow junction depth and method thereof are provided to reduce a drain parasitic resistance and a junction leakage current using double gate spacer. CONSTITUTION: The self-aligned silicide transistor comprises a gate electrode(10) formed on a semiconductor substrate(50); a gate oxide layer(18) formed at lower part of the gate electrode; a first spacer(21,22) formed at both sidewalls of the gate electrode; a second spacer(23,24) formed at both sidewalls of the first spacer; heavily doped source and drain regions(41,42) formed in the semiconductor substrate and self-aligned to the first spacer(21,22); and a silicide layer(71,72) formed on the heavily doped source and drain regions and self-aligned to the second spacer(23,24).

Description

Self-aligned silicide process using double spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a shallow junction, a semiconductor device applicable to the manufacturing process thereof, and a method of manufacturing the same.

As the minimum feature size applied to a semiconductor integrated circuit process is reduced, a metal oxide semiconductor field effect transistor (MOSFET) having a fine gate length may have a source and drain depletion region (A) as an applied drain voltage increases. The length of the depletion region increases relative to each other. As a result, the potential barrier between the source and the channel is lowered, causing the FET to exhibit punchthrough, while at the same time reducing the source-drain breakdown voltage, reducing the threshold voltage (V _T ), and threshold power. Typical short channel effects, such as increased subthreshold swing, are seen.

As a solution for suppressing such a short channel effect, a shallow junction forming technique is used, which keeps the depth of the source / drain N ⁺ / P ⁺ junction of the MOSFET shallow. When the source / drain of the shallow junction is used, the area occupancy of the source / drain is relatively reduced, so that the depletion length of the source / drain is reduced, and the short channel effect is improved to increase the punch-through breakdown voltage.

However, the shallow junction technique must be used to suppress the short channel effect, but there are a number of technical problems that must be solved in order to exhibit good device performance. That is, a shallow junction has a small depth of the junction, so ohmic contact is not easy, and sheet resistance increases rapidly. In particular, in the case of a semiconductor on insulator (SOI) device, the problem becomes more serious when the thickness of the active silicon is only 400 mW. Moreover, the amount of etch is generally increased to form a good contact hole profile, in which case the silicon may be excessively etched, which makes it difficult to expect good ohmic contact.

In order to improve the ohmic contact problem, a metal silicide process using a metal of Group VIII or refractory metal of the periodic table is used. That is, by depositing a metal such as titanium or cobalt on the silicon surface and performing a heat treatment at a specific temperature, a good suicide ohmic contact, which is a compound of several μΩ · cm of silicon and a metal material, can be obtained. One method of such silicide process techniques is disclosed in U.S. Patent No. 4,949,136, Volume 2 of "Silicon Processing for the VLSI Era" by S. Wolf, published in 1990 by Lattice Press. Pages 177 to 177 describe techniques related to silicide processes.

However, the shallow bonding technique has a very small thermal budget since it must maintain a shallow junction depth in subsequent processes. That is, since the silicide process proceeds at a low temperature to heal the implantation damage caused by the ion implantation process performed to form the source and drain junctions, the damaged silicon cannot be sufficiently annealed, resulting in junction leakage current. Junction leakage current is increased. In addition, during the silicidation process, metals and silicon are inevitably consumed because new compounds are formed by chemical action.

Therefore, in deep sub-half-micron integrated circuit processes with shallow junction technology, the depth of junction is shallow and the depth of the diffusion layer of N ⁺ / P ⁺ is very small, such as hundreds of microns, so that the source / drain Silicide penetrates into the channel and occupies all of the N ⁺ / P ⁺ diffusion layer regions, resulting in a significant increase in the parasitic resistance of the transistor at the drain region boundary. In other words, excessive consumption of silicon due to silicidation for shallow junctions leads to an increase in leakage current, drain parasitic resistance, and drain contact resistance of the junction, and at the same time, the drain current driving ability.

In particular, when the thickness of the source / drain active silicon of the SOI device is about 400 GPa or less, the silicided thickness occupies both N ⁺ / P ⁺ diffusion layers and meets the buried oxide at the bottom. In addition, the silicon atoms diffused into the deposited metal layer may be silicidated in the horizontal direction to penetrate the sidewall of the sidewall. As an example, during the 600 ° C. titanium silicide forming process, silicon atoms diffuse into and penetrate into the titanium layer to form titanium silicide in the horizontal direction on the side of the oxide spacer, thereby preventing leakage between the gate and the source / drain. S. Wolf points out the problem of current generation in the book "Silicon Processing for the VLSI Era", point 37, line 42 to line 42.

Accordingly, a first object of the present invention is to provide a semiconductor device in which a silicided ohmic contact region exists in the source and drain diffusion regions even when the source and drain diffusion layers of the MOSFET are shallow.

The second object of the present invention is, in addition to the first object, a semiconductor device having good source / drain ohmic contact and low leakage current characteristics even when the silicidation process is performed at a low temperature to secure a shallow junction depth. To provide.

The third object of the present invention is that in addition to the first object, even when the depth of the diffusion layer of the N ⁺ / P ⁺ source and drain of the lightly doped drain (LDD) MOSFET is shallow, the metal silicide layer advanced in the horizontal direction is moved to the LDD region. It is to provide a semiconductor device having a property of preventing penetration.

A fourth object of the present invention is, in addition to the first object, in the case of a MOSFET fabricated on a semiconductor (SOI) substrate on an insulator having a small thickness of an active silicon layer, a silicided ohmic contact is formed in the source and drain diffusion regions. It is to provide a semiconductor device to be present.

A fifth object of the present invention is to provide an efficient manufacturing method of a semiconductor device having the good silicide ohmic contact and the parasitic resistance component having a good drain current driving capability.

1 is a cross sectional view showing a main part of a semiconductor device according to a first embodiment of the present invention;

2A to 2G are process flowcharts showing a method of forming a semiconductor device according to a first embodiment of the present invention.

3A to 3F are process flowcharts showing a method of forming a semiconductor device according to a second embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

10, 20: polycrystalline silicon gate electrode

11, 12, 21, 22: first spacer

18: gate oxide film

23, 24: second spacer

30: first insulating film

41, 42: high conductivity impurity diffusion layer of the second conductivity type

50: first conductivity type semiconductor substrate

71, 72: silicide layer

76, 77: nitride film layer

80: shallow trench isolation (STI)

90 photoresist mask

170: a silicide layer formed on the gate according to the second embodiment

183 and 184: low concentration diffusion layer region according to the second embodiment

185 and 186: high concentration diffusion layer region according to the second embodiment

A: memory cell core area

B: peripheral circuit area

In order to achieve the above object, the present invention provides a transistor of a high integration device formed on a first conductivity type semiconductor substrate, comprising: a gate electrode formed on the semiconductor substrate; A gate insulating film having a predetermined thickness under the gate electrode; First spacers having a width of a first thickness formed on both sidewalls of the gate; A second spacer adjacent to the first spacer and having a width of a second thickness formed on both sidewalls; A second conductivity type impurity diffusion layer self-aligned with the first spacer and formed on the semiconductor substrate; A silicide layer self-aligned with the second spacer and formed on the second conductive impurity diffusion layer; Provided is a semiconductor device comprising a silicide layer formed on an upper portion of the gate electrode.

In order to achieve the above another object, the present invention comprises the steps of forming a gate oxide film on the first conductive substrate; Forming a gate electrode on the gate oxide layer; Forming first spacers on both sidewalls of the gate; Forming a second conductivity type impurity diffusion layer using the first spacer as a mask; Applying a second insulating film to the entire surface of the first conductive substrate; Forming a second spacer on both sidewalls of the first spacer from the second insulating layer; And forming a silicide layer on the second conductive type high concentration impurity diffusion layer and on the gate electrode using the second spacer as a mask in a self-aligned manner.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will now be described in detail with reference to the accompanying drawings.

1 is a diagram showing a semiconductor device according to a first embodiment of the present invention. Referring to FIG. 1, first, a gate insulating film 18 is formed on a first conductive semiconductor substrate, and a gate electrode 10 is formed on the gate insulating film. The first conductive channel region is formed in the lower semiconductor substrate of the gate insulating layer, and the first spacers 21 and 22 and the second spacers 23 and 24 are formed on both sidewalls of the gate electrode. It is formed adjacent to a double.

In addition, the silicon substrate under the first spacers 21 and 22 is formed with a self-aligned second conductive type doped source 41 and drain 42 layers, and the second spacers 23, 24) Self-aligned silicide layers 71 and 72 are formed on the lower silicon substrate. In addition, a nitride film layer is formed on the gate electrode 76.

2A to 2G are process flowcharts showing a method for manufacturing a semiconductor device according to the first embodiment. The first embodiment of the present invention is a preferred embodiment for the DRAM manufacturing process, the semiconductor manufacturing process shown in the left A portion of the drawing shows a cross-sectional manufacturing for the core of the memory cell, the cross-sectional view shown in the right B portion A diagram showing a manufacturing procedure of a transistor for a circuit. Meanwhile, a shallow trench isolation (STI) or local oxidation of silicon (LOCOS) may be used as a preferred embodiment for the isolation of each semiconductor device.

2A illustrates a process of forming the gate oxide film 18 and the gate electrodes 10 and 20. First, the gate oxide film 18 and the silicon gates 10 and 20 having a predetermined thickness are formed on the first conductive substrate 50. After forming the doped polycrystalline silicon and nitride film layers 76 and 77 for formation, a gate electrode of a desired size is formed through a process such as photoresist coating, mask exposure and development. Subsequently, the second conductive type low concentration impurity is implanted on the entire surface of the semiconductor wafer by self-alignment with the gate electrode.

FIG. 2B illustrates a process of forming the first insulating film 30, for example, a nitride film, on the entire surface of the resultant after the process of FIG. 2A.

FIG. 2C illustrates a process of forming the first spacers 11, 12, 21, and 22 as a result of the etch back process of the first insulating layer, and is formed on both sidewalls of the gate electrodes 10 and 20. To form a spacer having a width of. As a preferred embodiment, in order to form the first spacers 11, 12, 21, and 22, the nitride film may be coated at about 500 kPa in the deposition process of the first insulating film 30 shown in FIG. 2B.

FIG. 2D illustrates a process of forming the second conductivity-type high concentration diffusion layer after the process of FIG. 2C. First, the memory cell core portion of the transistor for a peripheral circuit is formed with the photoresist 90 masked. The source 41 and the drain 42 are formed by self-aligning the first spacers 11, 12, 21, and 22 formed in the above-mentioned second c process by ion implantation with a high concentration of the second conductivity type impurity. In a preferred embodiment, the second conductivity type impurity as a source and a drain of an N-type MOSFET can ion implant arsenic (As) with an energy of 5 to 20 KeV. Here, in order to improve the refresh characteristics of a DRAM (dynamic random access memory (DRAM) cell), a cell core is applied to the photoresist 90 to apply a silicide process to a source and a drain of only a peripheral region device. It is desirable to mask the portion ("A" region).

FIG. 2E illustrates a process of applying a second insulating film 60, for example, a nitride film, to the entire surface of the resultant after the process of FIG. 2D. As a preferred embodiment, the second insulating film may be coated with about 100 to 300 microseconds of nitride film to control the width of the second spacers 23 and 24 shown in FIG. 2f to about 100 to 300 microseconds.

FIG. 2F is a step of forming the second spacer only through the etch back process in the region "B" after the process of FIG. 2E. Since the region "A" is masked by the photoresist 90, the second spacer is not formed. .

FIG. 2G illustrates a process of forming silicides 71 and 72 in the source 41 and drain 42 regions, in which a memory cell core portion (“A” region) is formed by masking the second nitride layer 60. In one state, a predetermined metal for forming the silicide film is applied to the entire surface of the resultant source 41 and the drain 42 of the transistor ("B" region) for the peripheral circuit (periphery). Preferred examples of the silicide metal to be applied include platinum (Pt), platium (Pd), cobalt (Co), nickel (Ni), thallium (Ta), tungsten (W), molybdenum (Mo), titanium ( Ti) can be used.

Subsequently, when the heat treatment is performed at a predetermined temperature, the metal in contact with silicon causes a chemical reaction to form silicide films 71 and 72. At this time, the metals on the insulating film not subjected to the silicide reaction are removed by a predetermined solution.

Here, in the case of DRAM cells, silicide processes are not preferable for the source 43 and the drain 44 of the cell transistor because of memory refresh problems. Therefore, in the present invention, the second insulating film covering the cell transistor using the photoresist 90 after application of the second insulating film of FIG. 2e is not etched, and the source 41 and the drain 42 of the transistor for the peripheral circuit are not etched. Only the silicide process proceeds. In the first embodiment of the present invention, since the nitride film is formed on the gate electrode, the silicide layer is not formed on the gate electrode during the silicide process of FIG.

3A to 3F are process flowcharts showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention. According to the second embodiment of the present invention, the technical features of the first embodiment may be extended to self-align the lightly doped drain LDDs 181, 182, 183, and 184 self-aligned to the gate electrode and the first spacer. In a lightly doped drain (LDD) semiconductor fabrication apparatus having a heavily doped drain (185, 186, 187, 188), a technique is provided for forming good silicide ohmic contact at the gate electrode as well as the source and drain.

A second embodiment of the present invention discloses a method for manufacturing a semiconductor device that can be applied to a system logic manufacturing process such as a central process unit (CPU).

3A illustrates a process of forming the gate oxide film 118, the gate electrode 120, and the lightly doped diffusion layers 183 and 184. First, a gate having a predetermined thickness on the first conductive substrate 150 is formed. After the doped polycrystalline silicon is formed for the oxide film 118 and the silicon gate 120, a gate electrode 120 having a desired size is formed by performing photoresist coating, mask exposure, and development. Subsequently, a low concentration drain (LDD) 183 and 184 may be formed by injecting a low-concentration second conductivity type impurity such as arsenic (As) onto the entire surface of the process resultant.

3B illustrates a process of forming the first insulating layer 130, for example, a nitride film, on the entire surface of the resultant after the process of FIG. 3A. FIG. 3C illustrates a process of forming the first spacers 121 and 122 as a result of the etch back process of the first insulating layer, and has a width of a predetermined thickness on both sidewalls of the gate electrode 120. Form a spacer. In an embodiment, in order to form the first spacers 121 and 122, the nitride film may be coated with about 500 GPa in the deposition process of the first insulating film 130 shown in FIG. 3B.

FIG. 3d illustrates a process of forming a second conductivity-type high-doped diffusion layer after the process of FIG. 3c, and self-alignment with the first spacers 121 and 122 formed in the process of FIG. It is formed by ion implantation.

The semiconductor fabrication process sequence of FIGS. 3e and 3f proceeding after the process of FIG. 3d is the same as the semiconductor fabrication step disclosed in FIGS. 2e and 2f showing the first embodiment of the present invention described above. The description replaces the technical content of the first embodiment. However, in the second embodiment of the present invention, since the nitride layer applied in the first embodiment does not exist on the gate electrode 120, the silicide layer 170 is formed on the gate electrode when the silicide process is performed.

Meanwhile, referring to FIG. 3F, since the self-aligned silicide layers 171 and 172 are sufficiently overlapped in the high concentration diffusion layers 185 and 186, the low concentration diffusion layers 183 and 184 due to penetration in the horizontal direction during the silicide formation process are performed. Overlap can be prevented.

The foregoing has outlined rather broadly the features and technical advantages of the present invention to better understand the claims of the invention which will be described later. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously changed, substituted, and changed without departing from the spirit or scope of the invention described in the claims.

As described above, the semiconductor device according to the present invention has a structure for solving the problem of the conventional silicidation process of the shallow junction transistor, and the present invention uses a double gate spacer, and the high concentration diffusion layer of the source and drain sufficiently fills the silicide layer. By ensuring that it can overlap, it is possible to prevent the silicide layer from penetrating into the channel and to prevent the high concentration of source and drain from being encroached by the silicide layer to increase the parasitic resistance component.

In addition, another effect of the present invention is to suppress the leakage of the current due to the bridge phenomenon with the gate electrode by suppressing the formation of the horizontal silicide, and in the case of SOI devices, the silicided source and drain regions are buried oxide layer (buried oxide layer) ) Can be prevented.

Therefore, when the source and drain silicides are formed using the double gate spacer of the present invention, gate, source and drain electrodes having a very low contact resistance can be formed in a self-aligned manner, and in the case of a transistor having a shallow junction, the diffusion layer It is possible to manufacture a good deep-sub-half-micrometer device without deterioration of transconductance g _m , drain drive current Idsat, and drain parasitic resistance R _d due to erosion.

Claims (14)

In the transistor of the highly integrated element formed on the first conductivity type semiconductor substrate, A gate electrode formed on the semiconductor substrate; A gate insulating film having a predetermined thickness under the gate electrode; First spacers having a predetermined width formed on both sidewalls of the gate; A second spacer adjacent to the first spacer and having a predetermined width formed on both sidewalls; A second conductivity type source and drain region self-aligned with the first spacer and formed on the semiconductor substrate; Comprising a silicide layer self-aligned to the second spacer and formed on the second conductive source and drain region A semiconductor device, characterized in that. 2. The semiconductor device of claim 1, further comprising a second conductivity type low concentration source and drain region self-aligned to the gate electrode and formed on the first conductivity type semiconductor substrate. The semiconductor device according to claim 1, further comprising a silicide layer on the gate electrode. The semiconductor device according to claim 1, further comprising a nitride film layer on the gate electrode. The semiconductor device according to claim 1, wherein the semiconductor substrate comprises a substrate formed on a semiconductor substrate (SOI) on an insulator. Forming a gate oxide film on the first conductivity type semiconductor substrate; Forming a gate electrode on the gate oxide layer; Applying a first insulating film to the entire surface of the semiconductor substrate; Forming first spacers on both sidewalls of the gate from the first insulating layer; Forming a second conductivity type source and drain region using the first spacer as a mask; Applying a second insulating film to the entire surface of the semiconductor substrate; Forming a second spacer on both sidewalls of the first spacer from the second insulating layer; Self-aligning to the second spacer to form a predetermined silicide layer on top of the exposed silicon region on the semiconductor substrate Method for manufacturing a semiconductor device comprising a. 7. The semiconductor device according to claim 6, further comprising preventing the formation of the second spacer and the silicide layer by masking a predetermined portion on the semiconductor substrate after applying the second insulating film. Method of preparation. 7. The method of claim 6, further comprising self-aligning the gate electrode to form a second conductivity type low concentration source and drain region. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the thickness of the first spacer is 500 microseconds. The method of manufacturing a semiconductor device according to claim 6, wherein the second spacer has a thickness of 100 to 300 GPa. The method of manufacturing a semiconductor device according to claim 6, wherein the second conductivity type impurity is implanted at an energy of 5 to 20 KeV. The method of claim 6, wherein the silicide layer is platinum (Pt), platinum (Pd), cobalt (Co), nickel (Ni), thallium (Ta), tungsten (W), molybdenum (Mo), titanium (Ti) Or a silicide film is formed using any one of the methods. The method of claim 6, further comprising forming a nitride film on the gate electrode. 8. The method of claim 7, wherein the predetermined masking portion on the first conductivity type semiconductor substrate comprises memory cell portions in a DRAM semiconductor manufacturing process.