KR20000004360A - Method for manufacturing semiconductor devices - Google Patents
Method for manufacturing semiconductor devices Download PDFInfo
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- KR20000004360A KR20000004360A KR1019980025792A KR19980025792A KR20000004360A KR 20000004360 A KR20000004360 A KR 20000004360A KR 1019980025792 A KR1019980025792 A KR 1019980025792A KR 19980025792 A KR19980025792 A KR 19980025792A KR 20000004360 A KR20000004360 A KR 20000004360A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 이중 SOG막을 층간평탄화막으로서 이용하는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a double SOG film as an interlayer planarization film.
최근 반도체 소자의 제조기술이 향상되면서 고집적화 및 고속화가 급속히 진행되고 있다. 이에 따라, 배선 설계가 자유롭고 배선저항 및 전류용량 등의 설정을 여유롭게 할 수 있는 다층 금속배선 기술에 관한 연구가 활발히 진행되고 있다. 이러한, 다층 금속배선 공정 중 상층 금속배선과의 극심한 단차를 감소시키면서 기판 표면을 평탄화하기 위하여, 금속층간 평탄화막으로서 SOG(Spin-On-Glass)막을 이용한다. 이러한 SOG는 산소, 수소 및 탄소의 결합으로 이루어진 유기화합물로서, 유동성이 크고, 실록산 또는 실리케이트와 알콜 용제로 구성된 액상물질로서, 절연층의 보이드를 제거할 수 있는 장점이 있다. 또한, 공정이 간단하고 가격이 저렴하기 때문에, 평탄화막으로서 많이 이용되고, 최근에는 금속 층간의 평탄화를 더욱더 용이하게 하기 위하여 SOG막을 이중으로 도포한다.Recently, as the manufacturing technology of semiconductor devices is improved, high integration and high speed are rapidly progressing. Accordingly, studies on multilayer metal wiring technology that can freely design wiring and allow setting of wiring resistance and current capacity, etc., have been actively conducted. In order to planarize the substrate surface while reducing the extreme step with the upper metal wiring during the multilayer metal wiring process, a spin-on-glass film (SOG) is used as the planarization film between the metal layers. The SOG is an organic compound composed of a combination of oxygen, hydrogen, and carbon, has a high fluidity, and is a liquid material composed of siloxane or silicate and an alcohol solvent, and has an advantage of removing voids from the insulating layer. In addition, since the process is simple and inexpensive, it is widely used as a planarization film, and in recent years, an SOG film is applied twice in order to make planarization between metal layers even easier.
그러나, 층간평탄화막으로서 이중 SOG막을 이용하게 되면, 도 1에 도시된 바와 같이, 제 1 SOG막(11)의 도포후 기판(10)의 가장자리로부터 약 6㎜ 지점(A)에서 제 1 SOG막(11)의 EBR(Edge Bead Removal) 단차가 상승한다. 또한, 제 2 SOG막(12)의 도포 후에는 기판(10)의 가장자리로부터 약 4㎜ 지점(B)에서 EBR 단차는 더욱더 상승하게 되어, 심하게는 약 2㎛ 까지 단차가 상승하게 된다. 이러한 EBR 단차에 의해 후속 공정의 진행시 마스크 및 금속막이 들뜨는 현상이 발생되어, 배선의 신뢰성을 저하시킬 뿐만 아니라 파티클을 유발하여 장비 오염등의 심각한 문제를 야기시킨다.However, when a double SOG film is used as the interlayer planarization film, as shown in FIG. 1, the first SOG film is about 6 mm from the edge A of the substrate 10 after the application of the first SOG film 11. (11) EBR (Edge Bead Removal) step increases. In addition, after the application of the second SOG film 12, the EBR step becomes even higher at a point B about 4 mm from the edge of the substrate 10, and the step is raised to about 2 m. Due to the EBR step, the mask and the metal film are lifted up during the subsequent process, which not only lowers the reliability of the wiring but also causes particles, causing serious problems such as equipment contamination.
따라서, 본 발명은 SOG막의 EBR 단차로 인한 마스크 및 금속막의 들뜸 현상을 방지하여 배선의 신뢰성을 향상시키면서 파티클 유발을 억제할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing particle generation while improving the reliability of wiring by preventing the lifting phenomenon of the mask and the metal film due to the EBR step of the SOG film.
도 1은 이중 SOG막이 적용된 종래의 반도체 소자를 나타낸 단면도.1 is a cross-sectional view showing a conventional semiconductor device to which a double SOG film is applied.
도 2은 본 발명의 실시예에 따른 이중 SOG막이 적용된 반도체 소자의 제조방법을 설명하기 위한 단면도.2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device to which a double SOG film is applied according to an embodiment of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
20 : 반도체 기판 21, 22 : SOG막20: semiconductor substrate 21, 22: SOG film
23 : 감광막23: photosensitive film
상기 목적을 달성하기 위한 본 발명에 따른 SOG막을 이용한 반도체 소자는 다음과 같이 제조한다. 먼저, 상부에 EBR이 생성된 SOG막이 도포된 반도체 기판을 제공하고, SOG막 상에 상기 SOG막의 EBR의 최상부로부터 약 2 내지 4㎜ 정도 이격되도록 감광막을 도포한다. 그런 다음, 감광막을 패터닝하여 마스크 패턴을 형성한 후, 마스크 패턴을 이용하여 상기 기판의 일부가 노출되도록 상기 SOG막을 식각하여 콘택홀을 형성한다. 그리고 나서, 마스크 패턴을 제거함과 동시에 SOG막의 EBR을 제거한다.The semiconductor device using the SOG film according to the present invention for achieving the above object is manufactured as follows. First, a semiconductor substrate is coated with an SOG film having an EBR formed thereon, and a photosensitive film is coated on the SOG film so as to be spaced apart by about 2 to 4 mm from the top of the EBR of the SOG film. Next, after the photoresist is patterned to form a mask pattern, the SOG film is etched to expose a portion of the substrate using the mask pattern to form a contact hole. Then, while removing the mask pattern, the EBR of the SOG film is removed.
또한, SOG막은 이중막으로 도포하고, 마스크 패턴 및 SOG막의 EBR은 O2플라즈마를 이용하여 제거한다.The SOG film is applied as a double film, and the mask pattern and the EBR of the SOG film are removed using an O 2 plasma.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2는 본 발명의 실시예에 따른 이중 SOG막이 적용된 반도체 소자의 제조방법을 설명하기 위한 단면도로서, 기판의 가장자리 부분을 나타낸다.2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device to which a double SOG film is applied according to an embodiment of the present invention, and shows edge portions of a substrate.
도 2를 참조하면, 상부에 하부층 배선(미도시)이 형성된 반도체 기판(20) 상에 배선 층간의 평탄화 및 절연을 위하여 제 1 및 제 2 SOG막(21, 22)을 도포한다. 이때, 종래와 마찬가지로 기판(20)의 가장자리에 제 1 및 제 2 SOG막(21, 22)의 높은 EBR 단차가 생성된다. 그런 다음, 제 2 SOG막(22) 상에 콘택홀 형성을 위한 마스크 패턴을 형성하기 위하여 감광막(23)을 도포한다. 이때, 감광막(23)은 제 2 SOG막(22)의 EBR의 최상부로부터 소정 거리(C), 바람직하게 약 2 내지 4㎜ 정도 이격되도록 도포한다. 그런 다음, 도시되지는 않았지만, 감광막(23)을 노광 및 현상하여 마스크 패턴을 형성하고, 상기 마스크 패턴을 이용하여 제 2 및 제 1 SOG막(22, 21)을 상기 하부층 배선이 노출되도록 식각하여 콘택홀을 형성한다. 그 후, O2플라즈마를 이용하여 마스크 패턴을 제거함과 동시에 SOG막(21, 22)의 EBR을 제거하고, 상기 하부층 배선과 콘택하는 상부층 배선을 형성한다.Referring to FIG. 2, first and second SOG films 21 and 22 are coated on the semiconductor substrate 20 having lower layer wirings (not shown) thereon to planarize and insulate the wiring layers. At this time, as in the prior art, a high EBR step of the first and second SOG films 21 and 22 is generated at the edge of the substrate 20. Then, a photosensitive film 23 is applied to form a mask pattern for forming a contact hole on the second SOG film 22. At this time, the photosensitive film 23 is applied so as to be spaced apart from the top of the EBR of the second SOG film 22 by a predetermined distance C, preferably about 2 to 4 mm. Then, although not shown, the photoresist film 23 is exposed and developed to form a mask pattern, and the second and first SOG films 22 and 21 are etched to expose the lower layer wirings using the mask pattern. A contact hole is formed. Thereafter, the mask pattern is removed using an O 2 plasma, and at the same time, the EBR of the SOG films 21 and 22 is removed, and an upper layer wiring in contact with the lower layer wiring is formed.
상기한 본 발명에 의하면, 이중 SOG막을 이용한 층간 평탄화막의 형성 후, 감광막을 SOG막의 EBR 지점에서 소정 부분 이격시켜 도포하고, 감광막의 제거시 SOG막의 EBR을 동시에 제거함으로써, EBR에 의한 마스크 패턴 및 금속막의 들뜸 현성이 방지된다. 이에 따라, 배선의 신뢰성이 향상될 뿐만 아니라, 파티클 발생이 억제되어 장비 오염문제가 방지됨으로써, 결국 소자의 작업처리량(throughput)이 증가된다.According to the present invention described above, after the formation of the interlayer planarization film using the double SOG film, the photoresist film is applied at a predetermined portion spaced apart from the EBR point of the SOG film, and when the photoresist film is removed, the EBR of the SOG film is simultaneously removed, thereby removing the mask pattern and the metal by the EBR. Lifting manifestation of the membrane is prevented. This not only improves the reliability of the wiring, but also prevents particle generation and prevents equipment contamination, thereby increasing throughput of the device.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025792A KR100312648B1 (en) | 1998-06-30 | 1998-06-30 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025792A KR100312648B1 (en) | 1998-06-30 | 1998-06-30 | Manufacturing method of semiconductor device |
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| Publication Number | Publication Date |
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| KR20000004360A true KR20000004360A (en) | 2000-01-25 |
| KR100312648B1 KR100312648B1 (en) | 2002-04-24 |
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| KR1019980025792A KR100312648B1 (en) | 1998-06-30 | 1998-06-30 | Manufacturing method of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100668729B1 (en) * | 2001-06-28 | 2007-01-26 | 주식회사 하이닉스반도체 | Method for Fabricating of Semiconductor Device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940027089A (en) * | 1993-05-31 | 1994-12-10 | 김주용 | Spin-on-glass film edge bead removal |
| JPH08222550A (en) * | 1995-02-16 | 1996-08-30 | Sony Corp | Planarization of coating insulating film |
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1998
- 1998-06-30 KR KR1019980025792A patent/KR100312648B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100668729B1 (en) * | 2001-06-28 | 2007-01-26 | 주식회사 하이닉스반도체 | Method for Fabricating of Semiconductor Device |
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