KR20000004190A - Align key for photo-mask - Google Patents

Abstract

PURPOSE: An align key used for photo-mask is provided to prevent a damage of films and a penetration of particles into the damaged films through variation of line-width of the align key. CONSTITUTION: The align key(22) comprises square frame structure having square through hole, wherein the line-width of the align key(22) is sufficiently short compared to the line-width of the conventional align key(12). The line-width of the align key(22). has 2.5-3.5 micrometers. The square through hole has big size compared to the align key formed on a wafer.

Description

Align key for photo mask

The present invention relates to an alignment key for a photo mask, and more particularly, to prevent process defects caused by the alignment key during photolithography through a change in the line width of the alignment key. It relates to an alignment key for a photo mask.

Application of photolithography using a photo mask is essential when the film patterning process is performed to form a high breakdown voltage semiconductor device. In order to form a desired pattern by applying such an optical etching process, it is most important to accurately align the center points of the alignment key formed on the photo mask and the alignment key formed on the wafer before performing the etching process. This is because if the etching process is performed while the alignment between the alignment keys is not precise, the desired pattern may not be properly formed due to misalignment.

1A and 1B show a diagram illustrating an alignment key structure for a conventional photo mask directly related to the present invention. 1A shows a plan view from above of the photo mask, and FIG. 1B shows a cross-sectional view showing the X-X 'cutaway structure of FIG. 1A.

1A and 1B, the conventional alignment key 12 for a photo mask is configured to have a square frame structure having a rectangular hollow hole, and one edge portion on the glass 10 constituting the photo mask. It can be seen that it is formed in. The portion indicated by dotted lines in FIG. 1A indicates the position where the alignment key formed on the wafer is to be aligned when aligning the alignment key on the photo mask and the alignment key on the wafer.

At this time, the rectangular hollow hole is formed to have a size larger than the alignment key formed on the wafer, the rectangular frame is formed of a light-shielding material of chromium material, the line width (d2) is formed to have a size of 10㎛. Normally, when the align key formed on the wafer has the size indicated by the dotted line in Fig. 1A, the rectangular hollow hole further extends the distance d1 (d1 = 5 mu m) to the four sides of the portion indicated by the dotted line, respectively. It is assumed to have a size.

Therefore, in the case of forming a high breakdown voltage semiconductor device using a photo mask provided with the alignment key 22 having the above structure, the alignment and etching process between the alignment keys is performed in the following manner. Here, as an example, the process of forming the glass passivation layer of the bipolar transistor will be described with reference to the process purity shown in FIGS. 2A and 2B. For the sake of convenience, the process is divided into two stages.

As a first step, as shown in FIG. 2A, first, a p-type second semiconductor layer 102 serving as a base is formed inside an n-type first semiconductor layer 100 serving as a collector, and a second An n + type third semiconductor layer 104 serving as an emitter is formed in the semiconductor layer 102, and is formed on the top surface of the first semiconductor layer 100 at a predetermined distance from the second semiconductor layer 102. A shape-aligned key 106 is formed, and a wafer having a structure in which an insulating film 108 and a negative photosensitive film 110 are sequentially formed on the entire surface of the resultant is prepared. Next, a photo mask on which the mask pattern 14 and the alignment key 12 to be formed are designed is prepared. Then, the alignment key 12 of the photo mask and the alignment key 106 on the wafer are positioned, irradiated with light onto the mask and developed to remove the photosensitive film 110 under the mask pattern 14. The trench t is formed in the semiconductor layer 100 by etching the insulating layer 108 and a portion of the first semiconductor layer 100 using the etched photoresist layer 110 as a mask.

As a second step, as shown in FIG. 2B, the etched photoresist film 110 is removed, glass is formed on the insulating film 108 including the trench t, and then cured at a temperature of 800 to 880 ° C. Let it be. Subsequently, the glass is partially etched to expose the surface of the insulating film 108 around the trench t using a photolithography process to form a mesa structured glass passivation layer 112, thereby completing the process.

However, when the glass passivation layer forming process is performed using the photo mask provided with the alignment mark 12 of FIG. 1A, the following problem occurs during the photolithography process due to the alignment key 12. .

In the first step, if the exposure and development processes are performed while the alignment key 12 on the photo mask and the alignment key 106 on the wafer are aligned, as described above, Only the photoresist film 110 should be etched, but when the process is in progress, as shown, the photoresist film 110 under the alignment key 12 is also etched.

This phenomenon occurs because the photoresist film of this portion is also etched during the exposure and development process due to the relationship that the line width d2 of the alignment key 12 on the photomask has a size of 10 μm. 12) When the lower photoresist layer 110 is etched, the film quality 108 and 100 are etched together at this time when the insulating layer 108 and the first semiconductor layer 100 are etched, and the glass passivation is performed. During the formation of the layer 112, a defect in which the glass 112a is filled in the first semiconductor layer 100 under the alignment key 12 may occur.

When the defect occurs, the glass 112a filled in the first semiconductor layer 100 under the alignment key 12 acts as a particle to lower the overall breakdown voltage of the bipolar transistor during the subsequent process. This is urgently required.

Accordingly, an object of the present invention is to form the line width of the alignment key formed in the photo mask to a size of 2.5 ~ 3.5㎛, it is possible to eliminate the process defects caused by the alignment key when manufacturing a high breakdown voltage semiconductor device To provide an alignment key for a photo mask.

1A and 1B illustrate a conventional alignment key structure for a photo mask.

1a is a plan view thereof;

FIG. 1B is a cross-sectional view showing the X-X 'cross section of FIG. 1A;

2A and 2B are process flowcharts illustrating a method of manufacturing a bipolar transistor using the photomask provided with the alignment key of FIG. 1;

3A and 3B illustrate an alignment key structure for a photo mask according to the present invention.

3a is a plan view thereof;

FIG. 3B is a cross-sectional view illustrating a cross-sectional view taken along line X-X 'of FIG. 3A;

4A and 4B are process flowcharts illustrating a method of manufacturing a bipolar transistor using the photo mask provided with the alignment key of FIG. 3.

In the present invention, in order to achieve the above object, in the alignment key for a photo mask having a rectangular frame structure provided with a rectangular hollow hole, the line width of the alignment key is formed in a size of 2.5 ~ 3.5㎛ A mask alignment key is provided.

When the alignment key for the photomask is manufactured to have the above structure, the line width of the alignment key has a size of 2.5 to 3.5 μm, which prevents etching of the photoresist film on the wafer due to phosphorus during the exposure and development processes. Will be.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The present invention is to change the line width of the alignment key for the photo mask to a size of 2.5 ~ 3.5㎛ from the existing 10㎛, to focus on preventing the process defects caused by the alignment key during the photolithography process Technology.

3A and 3B are diagrams showing the alignment key structure for the photomask proposed in the present invention. 3A shows a top view of the photo mask from above, and FIG. 3B shows a cross-sectional view showing the X-X 'cutaway structure of FIG. 3A.

3A and 3B, the alignment key 22 for the photomask proposed in the present invention is configured to have a rectangular frame structure having a rectangular hollow hole. 12) and the same basic structure, but it can be seen that the line width (d4) has a difference in that it is manufactured to have a size of 2.5 ~ 3.5㎛ instead of 10㎛. In FIG. 3A, reference numeral 20 denotes a glass constituting a photo mask, and a portion indicated by a dotted line indicates a position at which an alignment key formed on a wafer is to be aligned when the alignment key on the photo mask is aligned with the alignment key on the wafer. .

At this time, the rectangular hollow hole is formed to have a size larger than the alignment key formed on the wafer, the rectangular frame is formed of a light-shielding material of chromium material, the alignment key formed on the wafer is usually the size indicated by the dotted line of Figure 1a When viewed as having a rectangular hollow hole, it can be regarded as having a size that is further extended with a distance d3 (d1 = 5 mu m) with respect to the slope of the portion indicated by the dotted line, respectively.

Therefore, when fabricating a high breakdown voltage semiconductor device using an etch mask having the alignment key 22 of the above structure, the alignment and etching processes are performed in the following manner. Here, as an example, the process of forming the glass passivation layer of the bipolar transistor will be described with reference to the process purity shown in FIGS. 4A and 4B. For the sake of convenience, the process is divided into two stages.

As a first step, as shown in FIG. 4A, first, a p-type second semiconductor layer 202 serving as a base is formed inside an n-type first semiconductor layer 200 serving as a collector, and a second In the semiconductor layer 202, an n + type third semiconductor layer 204 serving as an emitter is formed, and a quadrangle is formed on the top surface of the first semiconductor layer 200 at a predetermined distance from the second semiconductor layer 202. A shaped alignment key 206 is formed, and a wafer having a structure in which an insulating film 208 and a negative photosensitive film 210 are sequentially formed on the entire surface of the resultant is prepared. Next, a photo mask on which the mask pattern 24 and the alignment key 22 to be formed are designed is prepared. Next, the alignment key 22 of the photo mask and the alignment key 206 on the wafer are aligned, and an exposure and development process is performed to remove the photosensitive film 210 under the mask pattern 24, and then etch the same. Using the photoresist film 210 as a mask, a portion of the insulating film 208 and the first semiconductor layer 200 are etched to form a trench t in the semiconductor layer 100.

In this case, since the line width of the alignment key 22 is only 2.5 to 3.5 μm, the surface of the photoresist film 210 under the alignment key 22 is formed at a predetermined portion (a portion indicated by a dotted line on the drawing) by an exposure and developing process. Although only a portion of the surface side thereof is developed, the insulating film 208 and the first semiconductor layer 100 are not etched together during the etching process.

As a second step, as shown in FIG. 4B, the etched photoresist film 210 is removed, glass is formed on the insulating film 208 including the trench t, and then cured at a temperature of 800 to 880 ° C. Let it be. Subsequently, the glass is partially etched to expose the surface of the insulating film 208 around the trench t by using the photolithography process to form a glass passivation layer 112 having a mesa structure, thereby completing the process.

As such, when the photolithography process is performed using the etch mask provided with the alignment key of FIG. 3A, even if the photoresist film 210 is partially developed in the first step by the exposure and development processes, the insulating film 208 is etched. Since the phenomenon does not occur, defects in which the glass is stacked inside the first semiconductor layer 200 around the alignment key 206 formed on the wafer may be prevented when the glass passivation layer 212 is formed.

As described above, according to the present invention, since the line width of the alignment key formed on the photo mask is formed to a size of 2.5 to 3.5 μm, process defects caused by the alignment key in manufacturing a high breakdown voltage semiconductor device (for example, It is possible to eliminate the film quality damage around the alignment key formed on the wafer or the defect that the particle component (glass) is laminated into the damaged film quality).

Claims (3)

An alignment key for a photo mask having a rectangular frame structure having a rectangular hollow hole, wherein an alignment key has a line width of 2.5 to 3.5 μm. The alignment key for a mask according to claim 1, wherein the alignment key is made of a light blocking material. The alignment key for a mask according to claim 2, wherein the light blocking material is chromium.