KR20000003454A - Method of fabricating semiconductor device using high density plasma oxide film as interfacial insulation film - Google Patents

Method of fabricating semiconductor device using high density plasma oxide film as interfacial insulation film Download PDF

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Publication number
KR20000003454A
KR20000003454A KR1019980024696A KR19980024696A KR20000003454A KR 20000003454 A KR20000003454 A KR 20000003454A KR 1019980024696 A KR1019980024696 A KR 1019980024696A KR 19980024696 A KR19980024696 A KR 19980024696A KR 20000003454 A KR20000003454 A KR 20000003454A
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South Korea
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oxide film
film
density plasma
high density
plasma oxide
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KR1019980024696A
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Korean (ko)
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손현철
이상화
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김영환
현대전자산업 주식회사
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Priority to KR1019980024696A priority Critical patent/KR20000003454A/en
Publication of KR20000003454A publication Critical patent/KR20000003454A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: The method prevents Ar gas contained in a High Density Plasma(HDP) oxide film by a high temperature process from degassing into an open aperture when burying a conduction film in the open aperture formed through the HDP oxide film. CONSTITUTION: The method improves the burying characteristics in depositing a conduction film such as an aluminum film by covering the side wall part of a contact hole with a barrier insulation spacer such as a silicon nitride film(12) and a silicon oxide film preventing Ar from degassing into the contact hole, after forming the contact hole(or via hole) after depositing a high density plasma(HDP) oxide film(11).

Description

고밀도 플라즈마 산화막을 층간 절연막으로 사용하는 반도체 장치 제조방법Method of manufacturing semiconductor device using high density plasma oxide film as interlayer insulating film

본 발명은 반도체 기술 분야에 관한 것으로, 특히 고밀도 플라즈마(High Density Plasma, HDP) 산화막을 층간 절연막으로 사용하는 반도체 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor technology, and more particularly, to a method of manufacturing a semiconductor device using a high density plasma (HDP) oxide film as an interlayer insulating film.

반도체 장치의 고집적화에 따라 반도체 장치의 다층화는 일반화되어 있다. 따라서, 전도층간의 전기적 연결을 위한 콘택홀(또는 비아홀)의 형성 및 매립 공정은 반도체 장치의 신뢰도와 수율을 결정하는 요인 중의 하나로 부각되고 있다.BACKGROUND ART With the increasing integration of semiconductor devices, multilayering of semiconductor devices has become common. Therefore, the process of forming and filling contact holes (or via holes) for electrical connection between conductive layers has emerged as one of factors determining reliability and yield of semiconductor devices.

통상적으로, 다층 금속배선 공정에서 좁은 금속배선 사이의 간극 매립시 우수한 단차피복성을 얻기 위하여 금속층간 절연막으로서 고밀도 플라즈마(HDP) 산화막을 사용하고 있다. 이러한 고밀도 플라즈마 산화막은 SiH4가스, O2가스 및 Ar 가스 등을 사용하여 증착하는데, 증착후 막 내부에 Ar 가스를 함유하게 된다. 그런데, 이러한 고밀도 플라즈마 산화막의 내부에 포함된 Ar 가스는 비아홀 식각후 상부금속막 매립 공정시의 고온 분위기에서 비아홀 내로 방출되어 상부금속막의 매립 특성을 저하시키고, 이로 인하여 비아홀 보이드(void)를 유발하는 문제점이 있었다.In general, a high density plasma (HDP) oxide film is used as an interlayer insulating film in order to obtain excellent step coverage in filling gaps between narrow metal wirings in a multilayer metal wiring process. The high-density plasma oxide film is deposited using SiH 4 gas, O 2 gas, Ar gas, and the like, and the Ar gas is contained in the film after deposition. However, the Ar gas contained in the high density plasma oxide film is discharged into the via hole in a high temperature atmosphere during the upper metal film embedding process after the via hole etching, thereby lowering the buried characteristics of the upper metal film, thereby causing the via hole voids. There was a problem.

그럼에도 불구하고, Ar 가스는 고밀도 플라즈마 산화막 증착시 없어서는 않되는 필수적인 가스이기 때문에 Ar 가스의 방출에 따른 상부금속막 매립 특성의 저하를 피할 수 없었다.Nevertheless, since the Ar gas is an indispensable gas for high-density plasma oxide film deposition, deterioration of the upper metal film embedding characteristics due to the release of Ar gas was inevitable.

이러한 문제점은 비단 다층 금속배선 공정에서만 유발되는 것이 아니라 HDP 산화막을 층간 절연막으로 사용하는 다른 수직 배선 공정에서도 유발되고 있다.This problem is not only caused by the multi-layer metallization process but also by other vertical interconnection processes using an HDP oxide film as an interlayer insulating film.

본 발명은 HDP 산화막을 관통하여 형성된 개구부에 전도막 매립시, 고온 공정에 의해 HDP 산화막 내에 포함된 Ar 가스 등이 개구부 내로 탈기되는 것을 방지하는 반도체 장치 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which prevents degassing of Ar gas and the like contained in the HDP oxide film by the high temperature process when the conductive film is embedded in the opening formed through the HDP oxide film.

도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 이층 금속배선 형성 공정도.1a to 1d is a two-layer metallization process diagram according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 하부 금속배선 11 : HDP 산화막10: lower metal wiring 11: HDP oxide film

12 : 실리콘 질화막 12a : 바아홀 측벽 스페이서12 silicon nitride film 12a bar hole sidewall spacer

13 : 상부 금속배선13: upper metal wiring

상기 목적을 달성하기 위하여 본 발명으로부터 제공되는 특징적인 반도체 장치 제조방법은 소정의 하부층이 형성된 전체구조 상부에 고밀도 플라즈마 산화막을 형성하는 제1 단계; 상기 고밀도 플라즈마 산화막을 선택 식각하여 상기 하부층을 노출시키는 개구부를 형성하는 제2 단계; 상기 고밀도 플라즈마 산화막 내에 포함된 Ar 가스의 탈기를 방지하기 위하여 상기 개구부 측벽 부분을 덮는 베리어 절연막 스페이서를 형성하는 제3 단계; 및 상기 개구부를 매립하는 전도막을 형성하는 제4 단계를 포함하여 이루어진다.A characteristic semiconductor device manufacturing method provided from the present invention for achieving the above object comprises a first step of forming a high-density plasma oxide film on top of the entire structure, the predetermined lower layer is formed; Selectively etching the dense plasma oxide layer to form an opening exposing the lower layer; Forming a barrier insulating layer spacer covering the sidewall portion of the opening to prevent degassing of the Ar gas contained in the high density plasma oxide film; And a fourth step of forming a conductive film filling the opening.

즉, 본 발명은 HDP 산화막 증착후 콘택홀(또는 비아홀)을 형성한 다음, 실리콘 질화막, 실리콘 산화막과 같이 Ar 등의 콘택홀로의 탈기를 방지하는 베리어 절연막 스페이서로 콘택홀 측벽 부분을 덮어 후속 전도막(예를 들어, 알루미늄막) 증착시 매립 특성을 향상시킨다.That is, the present invention forms a contact hole (or via hole) after the HDP oxide film is deposited, and then covers the contact hole sidewall portion with a barrier insulating layer spacer that prevents degassing into contact holes such as Ar, such as a silicon nitride film and a silicon oxide film. (E.g., aluminum film) Improves the embedding characteristics during deposition.

이하, 본 발명의 용이한 실시를 도모하기 위하여 본 발명의 바람직한 실시예를 소개한다.Hereinafter, preferred embodiments of the present invention will be introduced to facilitate easy implementation of the present invention.

첨부된 도면 도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 반도체 장치의 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.1A to 1D illustrate a process of forming metal wirings in a semiconductor device according to an embodiment of the present invention, and the process will be described below with reference to the drawings.

우선, 도 1a에 도시된 바와 같이 소정의 하부층 및 하부 금속배선(10)이 형성된 전체구조 상부에 금속층간 절연막으로서 HDP 산화막(11)을 증착하고, 이를 선택 식각하여 하부 금속배선을 노출시키는 비아홀을 형성한다.First, as shown in FIG. 1A, an HDP oxide film 11 is deposited as an intermetallic insulating layer on an entire structure in which a predetermined lower layer and a lower metal wiring 10 are formed, and then selectively etched to expose a via hole exposing the lower metal wiring. Form.

다음으로, 도 1b에 도시된 바와 같이 전체구조 표면을 따라 실리콘 질화막(12)을 증착한다. 이때, 실리콘 질화막(12)을 대신하여 실리콘 산화막을 증착할 수도 있으며, 이러한 실리콘 질화막(12) 및 실리콘 산화막 등은 HDP 산화막 형성시 그 내부에 포함되는 Ar 가스 등이 금속 매립시의 고온 공정에 의해 비아홀 내로 탈기(outgassing) 되는 것을 막아 주는 베리어로 작용한다.Next, as shown in FIG. 1B, a silicon nitride film 12 is deposited along the entire structure surface. In this case, a silicon oxide film may be deposited in place of the silicon nitride film 12, and the silicon nitride film 12 and the silicon oxide film may be formed by a high temperature process in which Ar gas or the like is contained in the HDP oxide film. It acts as a barrier to prevent outgassing into via holes.

계속하여, 도 1c에 도시된 바와 같이 실리콘 질화막(12)을 비등방성 전면 식각하여 바아홀 측벽 스페이서(12a)를 형성한다.Subsequently, as shown in FIG. 1C, the silicon nitride film 12 is anisotropically etched to form the bar hole sidewall spacers 12a.

이어서, 도 1d에 도시된 바와 같이 장벽 금속을 포함하는 상부 금속배선(13)을 형성한다. 이때, 주 금속배선 재료로는 알루미늄을 사용할 수 있으며, 텅스텐 플러그를 사용할 수도 있다.Subsequently, as shown in FIG. 1D, the upper metal wiring 13 including the barrier metal is formed. In this case, aluminum may be used as the main metal wiring material, and a tungsten plug may be used.

전술한 일 실시예에서는 이층 금속배선 형성 공정을 일례로 하여 설명하였으나, 본 발명은 HDP 산화막을 층간 절연막으로 사용하는 다른 수직 배선 공정에도 적용할 수 있다.In the above-described embodiment, the two-layer metal wiring forming process is described as an example, but the present invention can be applied to other vertical wiring processes using the HDP oxide film as the interlayer insulating film.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

이상에서와 같이 본 발명은 금속배선 공정을 안정화하는 효과가 있으며, 이로 인하여 반도체 장치의 신뢰도 및 수율을 향상시키는 효과가 있다. 또한, 본 발명을 실시하면 금속 매립 특성이 향상되기 때문에 종래와 같은 텅스텐 플러그를 사용하지 않고 알루미늄만으로 금속배선을 형성할 수 있어 공정 단순화의 부수적인 효과가 있다.As described above, the present invention has the effect of stabilizing the metallization process, thereby improving the reliability and yield of the semiconductor device. In addition, since the metal buried property is improved by implementing the present invention, a metal wiring can be formed only by aluminum without using a tungsten plug as in the prior art, which has an additional effect of simplifying the process.

Claims (2)

소정의 하부층이 형성된 전체구조 상부에 고밀도 플라즈마 산화막을 형성하는 제1 단계;A first step of forming a high density plasma oxide film over the entire structure in which a predetermined lower layer is formed; 상기 고밀도 플라즈마 산화막을 선택 식각하여 상기 하부층을 노출시키는 개구부를 형성하는 제2 단계;Selectively etching the dense plasma oxide layer to form an opening exposing the lower layer; 상기 고밀도 플라즈마 산화막 내에 포함된 Ar 가스의 탈기를 방지하기 위하여 상기 개구부 측벽 부분을 덮는 베리어 절연막 스페이서를 형성하는 제3 단계; 및Forming a barrier insulating layer spacer covering the sidewall portion of the opening to prevent degassing of the Ar gas contained in the high density plasma oxide film; And 상기 개구부를 매립하는 전도막을 형성하는 제4 단계A fourth step of forming a conductive film filling the opening 를 포함하여 이루어진 반도체 장치 제조방법.A semiconductor device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 베리어 절연막 스페이서가 실리콘 질화막 또는 실리콘 산화막으로 이루어진 반도체 장치 제조방법.And the barrier insulating film spacer is formed of a silicon nitride film or a silicon oxide film.
KR1019980024696A 1998-06-29 1998-06-29 Method of fabricating semiconductor device using high density plasma oxide film as interfacial insulation film KR20000003454A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505451B1 (en) * 2000-05-31 2005-08-04 주식회사 하이닉스반도체 Method for forming metal wire of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505451B1 (en) * 2000-05-31 2005-08-04 주식회사 하이닉스반도체 Method for forming metal wire of semiconductor device

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