KR100314742B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100314742B1 KR100314742B1 KR1019950065693A KR19950065693A KR100314742B1 KR 100314742 B1 KR100314742 B1 KR 100314742B1 KR 1019950065693 A KR1019950065693 A KR 1019950065693A KR 19950065693 A KR19950065693 A KR 19950065693A KR 100314742 B1 KR100314742 B1 KR 100314742B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다층 금속 배선 구조에서 금속층간 절연막의 평탄화막으로 사용되는 SOG 막의 수분 흡수 억제 및 후속공정에서의 수분 방출을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of suppressing moisture absorption of an SOG film used as a planarization film of an intermetallic insulating film in a multi-layered metal wiring structure and preventing water from being released in a subsequent step. It is about.
금속층간 절연막으로 쓰이는 SOG막은 간극 매립 특성과 평탄성이 우수할 뿐만 아니라 공정이 단순하여 금속층간 절연막의 평탄화막으로 널리 쓰이고 있다. 그러나 SOG막은 막내에 다량의 수분을 함유하고 있고, 또한 친수성이 강한관계로 수분 제거를 위한 열처리후에도 외부로 부터 수분을 흡수하기 때문에 소자가 고집적화될 수록 많은 문제점을 유발하고 있다. 소자의 고집적화로 인해 트랜지스터 격 리 간격이 좁아지면 SOG막내의 수분이 기판쪽으로 확산되어 접합과 접합간 격리 불량 현상이 유발될 가능성이 커지게 되는데, 비아 콘택 형성시 측면벽에 노출된 SOG막으로의 수분 유입은 이러한 문제를 더욱 심화시키고 있다. 또한 소자의 고집적화는 비아홀 크기의 축소로 금속배선 재료의 증착시 충덮힘성이 저하되는 문제를 유발하는데, 금속배선 재료의 고온 증착시 SOG막으로 부터 외방확산된 다량의 수분은 금속층막의 충덮힘성을 더욱 저하시키는 한편 금속배선을 부식시키기도 한다. 이를 제 1A 및 1B 도를 참조하여 설명하면 다음과 같다.The SOG film used as the interlayer insulating film not only has excellent gap filling characteristics and flatness, but also has a simple process and is widely used as a flattening film for intermetallic insulating films. However, since the SOG film contains a large amount of water in the film and has a strong hydrophilicity, and absorbs moisture from the outside even after heat treatment for water removal, the higher the density of the device, the more problems are caused. If the transistor isolation interval is narrowed due to the high integration of the device, the moisture in the SOG film diffuses toward the substrate, which increases the possibility of poor isolation between the junction and the junction, which leads to the SOG film exposed on the sidewalls when the via contact is formed. Water inflow is exacerbating this problem. In addition, the high integration of the device causes a decrease in via hole size, resulting in a problem of deterioration of the covering properties during the deposition of the metallization material. It can also degrade and corrode metallization. This will be described with reference to FIGS. 1A and 1B as follows.
제 1A 및 1B 도는 종래 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도이다.1A and 1B are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.
제 1A 도를 참조하면, 폴리-금속 층간절연막(2)이 실리콘 기판(1)상에 형성되고, 폴리-금속 층간절연막(2)상에는 금속배선공정을 통해 하부 금속배선(3)이 형성된다. 하부 금속배선(3)을 포함한 층간 절연막(2)상에 제 1 절연막(4), SOG막(5) 및 제 2 절연막(6)이 순차적으로 형성된다. 비아콘택 마스크를 사용한 습식 및 건식식각방식으로 제 2 절연막(6), SOG막(5) 및 제 1 절연막(4)을 순차적으로 식각함에 의해 비아홀(7)이 형성된다.Referring to FIG. 1A, a poly-metal interlayer insulating film 2 is formed on a silicon substrate 1, and a lower metal wiring 3 is formed on a poly-metal interlayer insulating film 2 through a metal wiring process. The first insulating film 4, the SOG film 5, and the second insulating film 6 are sequentially formed on the interlayer insulating film 2 including the lower metal wiring 3. The via hole 7 is formed by sequentially etching the second insulating film 6, the SOG film 5, and the first insulating film 4 by wet and dry etching using a via contact mask.
상기에서, 제 1 및 2 절연막(4 및 6)각각은 플라즈마 화학기상증착법에 의해 TEOS 산화막, SiH4산화막 또는 실리콘 과다 산화막등으로 형성되며, 이들 막(4 및 6)은 SOG막(5)에 함유된 수분이 외방확산되는 것을 방지하면서 금속배선간을 전기적으로 절연시킨다. SOG막(5)은 하부 금속배선(3)이 조밀하게 형성됨에 의해 생기는 갭(gap)을 매우기 위해 스핀방식으로 제 1 절연막(4)상에 형성된다.In the above, each of the first and second insulating films 4 and 6 is formed of a TEOS oxide film, a SiH 4 oxide film, or an excessive silicon oxide film by plasma chemical vapor deposition, and these films 4 and 6 are formed on the SOG film 5. Electrically insulates the metal wires while preventing the moisture from spreading outward. The SOG film 5 is formed on the first insulating film 4 in a spin manner in order to fill gaps caused by the lower metal wiring 3 being densely formed.
잘알려진 바와같이 SOG막은 막 자체내에 다량의 수분이 함유되어 있어 SOG막 도포후 수분 제거를 위한 열처리공정을 실시한다. 그러나 SOG막내의 수분을 완전히 제거하기는 어렵다. 이상태에서 비아 콘택 공정을 통해 SOG막(5)이 비아홀(7)의 측벽으로 노출되면, 노출된 SOG막(5)을 통해 수분(H2O)이 유입되어 이미 SOG막(5) 내에 함유되어 있던 수분과 더불어 SOG막(5)에는 수분함량이 증가된다. 다량의 수분은 기판쪽으로의 확산 이동으로 접합과 접합간 격리 불량 현상을 심화시키는 요인으로 작용한다.As is well known, the SOG film contains a large amount of water in the film itself, so that the SOG film is subjected to a heat treatment process for water removal after application of the SOG film. However, it is difficult to completely remove the moisture in the SOG film. In this state, when the SOG film 5 is exposed to the sidewall of the via hole 7 through the via contact process, moisture (H 2 O) flows through the exposed SOG film 5 and is already contained in the SOG film 5. In addition to the moisture present, the moisture content of the SOG film 5 increases. A large amount of moisture acts as a factor to deepen the poor adhesion between the junction and the junction by the diffusion movement toward the substrate.
제 1B 도는 금속배선 공정을 통해 상부 금속배선(8)을 형성한 것이 도시되는데 상부 금속배선(8)형성공정 동안에 비아홀(7)의 측벽으로 노출된 SOG막(5)으로 부터 외방확산되는 수분은 금속막이 비아홀(7)안으로 채워지지 못하게 하여 금속배선이 단선되는 현상을 유발시키거나, 증착되는 금속막을 부식시켜 하부 금속배선(3)사이의 계면부에 부식층(10)이 형성되므로 인하여 접합 불량을 유발시키는 원인이 되기도 한다. 또한 금속막이 비아홀(7)안으로 채워지더라도 층덮힘성이 좋지않기 때문에 소자의 동작시 금속원자의 이동현상으로 인해 금속배선이 단선될 가능성이 크므로 소자의 신뢰성을 저하시킨다.FIG. 1B shows the formation of the upper metal wiring 8 through the metallization process. Moisture diffused outward from the SOG film 5 exposed to the sidewall of the via hole 7 during the formation of the upper metallization 8 is formed. This prevents the metal film from filling into the via hole 7 and causes a disconnection of the metal wiring or corrodes the deposited metal film to form a corrosion layer 10 at the interface between the lower metal wirings 3. It can also be a cause. In addition, even if the metal film is filled in the via hole 7, the layer covering property is not good, so that the metal wiring is likely to be disconnected due to the movement of metal atoms during the operation of the device, thereby reducing the reliability of the device.
상술한 바와같이 종래의 방법에 의하면, SOG막이 비아홀와 측벽으로 노출됨에 의해 수분의 외방확산으로 인하여 금속배선을 부식시켜 저항을 증가시키고, 또한 금속막의 층덮힘 불량으로 금속배선의 단선을 유발시키거나 후속공정을 어렵게 하는등의 문제점이 있다.As described above, according to the conventional method, the SOG film is exposed to the via holes and the sidewalls to corrode the metal wiring due to the outward diffusion of moisture, thereby increasing the resistance, and also causing the disconnection of the metal wiring due to poor layer covering of the metal film or subsequent There are problems such as making the process difficult.
따라서, 본 발명은 다층 금속배선 구조에서 금속층간 절연막의 평탄화막으로 사용되는 SOG막의 수분 흡수 억제 및 후속공정에서의 수분 방출을 방지하여 금속배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a method of manufacturing a semiconductor device which can improve the reliability of metal wiring by preventing moisture absorption of SOG film used as a planarization film of an intermetallic insulating film in a multi-layer metal wiring structure and preventing water release in a subsequent process. Has its purpose.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 폴리-금속 층간절연막상에 하부 금속배선이 형성된 실리콘 기판이 제공되고, 상기 하부 금속배선을 포함한 상기 폴리-금속 층간절연막상에 제 1 절연막, SOG막 및 제 2 절연막을 순차적으로 형성하는 단계; 비아 콘택 마스크를 사용한 식각공정으로 상기 제 2 절연막, 상기 SOG막 및 상기 제 1 절연막을 순차적으로 식각함에 의해 비아홀이 형성되는 단계; 급속열처리를 실시하여 상기 비아홀의 측벽에 노출된 상기 SOG막의 표면에 경화층이 형성되는 단계; 및 상기 비아홀을 포함한 상기 제 2 절연막상에 상부 금속배선을 형성하는 단계로 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is provided with a silicon substrate having a lower metal wiring formed on the poly-metal interlayer insulating film, a first insulating film on the poly-metal interlayer insulating film including the lower metal wiring Sequentially forming a SOG film and a second insulating film; Forming a via hole by sequentially etching the second insulating film, the SOG film, and the first insulating film by an etching process using a via contact mask; Performing a rapid heat treatment to form a cured layer on the surface of the SOG film exposed on the sidewalls of the via hole; And forming an upper metal wiring on the second insulating layer including the via hole.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 2A 및 2B 도는 본 발명의 실시예에 의한 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도이다.2A and 2B are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device according to the embodiment of the present invention.
제 2A 도를 참조하면, 폴리-금속 층간절연막(12)이 실리콘 기판(11)상에 형성되고, 폴리-금속 층간절연막(12)상에는 금속배선공정을 통해 하부 금속배선(13)이 형성된다. 하부 금속배선(13)을 포함한 충간 절연막(12)상에 제 1 절연막(14), SOG막(15) 및 제 2 절연막(16)이 순차적으로 형성된다. 비아 콘택 마스크를 사용한 습식 및 건식식각방식으로 제 2 절연막(16), SOG막(15) 및 제 1 절연막(14)을 순차적으로 식각함에 의해 비아홀(17)이 형성된다. 비아홀(17)의 측벽에는 SOG막(17)의 일부가 노출되는데, SOG막(15)의 수분 흡수 억제 및 후속공정에서의 수분 방출을 방지하기 위하여, SOG막(15)의 노출된 부분에 경화층(20)을 형성한다. 경화층(20)은 급속열처리(RTP)를 실시함에 의해 형성되는데, 급속열처리는 N2나 진공상태로 600 내지 800℃의 온도범위에서 5 내지 60초간 실시한다. 이때, SOG막(15)내의 수분중 일부가 비아홀(17)을 통해 외방확산되며, 이로인하여 SOG막(15)내의 수분함량을 감소시키는 효과를 얻을 수 있다. 또한 비아홀(17)의, 측벽면에 노출된 SOG막(15)은 치밀화되어 경화층(20)이 형성된다. 본 발명에서는 600 내지 800℃의 고온에서 급속열처리를 하여야하기 때문에 하부 금속배선(13)을 형성하기 위한 재료로 쓰이는 금속은 용융점이 높은 텅스텐 및 구리와 같은 내화 금속(refractory metal)을 사용하여야 한다. 이렇게 형성된 경화층(20)은 SOG막(15)내부로 더 이상의 수분이 유입되는 현상을 억제하고, 고온에서 금속막 증착을 실시할 경우 측벽면에 노출된 SOG막(15)으로부터 수분이 방출되는 현상을 억제하는 방지막 역할을 하게 된다.Referring to FIG. 2A, a poly-metal interlayer insulating film 12 is formed on the silicon substrate 11, and a lower metal wiring 13 is formed on the poly-metal interlayer insulating film 12 through a metal wiring process. The first insulating film 14, the SOG film 15, and the second insulating film 16 are sequentially formed on the interlayer insulating film 12 including the lower metal wiring 13. The via hole 17 is formed by sequentially etching the second insulating film 16, the SOG film 15, and the first insulating film 14 by wet and dry etching using a via contact mask. A portion of the SOG film 17 is exposed on the sidewall of the via hole 17, and is cured on the exposed portion of the SOG film 15 in order to suppress moisture absorption of the SOG film 15 and to prevent moisture release in a subsequent process. Form layer 20. The hardened layer 20 is formed by performing rapid heat treatment (RTP), which is performed for 5 to 60 seconds in a temperature range of 600 to 800 ° C. in N 2 or vacuum. At this time, some of the moisture in the SOG film 15 is diffused outward through the via hole 17, thereby reducing the water content in the SOG film 15 can be obtained. In addition, the SOG film 15 exposed on the sidewall surface of the via hole 17 is densified to form a hardened layer 20. In the present invention, since the rapid heat treatment must be performed at a high temperature of 600 to 800 ° C, a metal used as a material for forming the lower metal wiring 13 should use a refractory metal such as tungsten and copper having a high melting point. The cured layer 20 formed as described above suppresses the inflow of further moisture into the SOG film 15, and when the metal film is deposited at a high temperature, water is released from the SOG film 15 exposed on the sidewall surface. It acts as a barrier to suppress the phenomenon.
상기에서, 제 1 및 2 절연막(14 및 16) 각각은 플라즈마 화학기상증착법에 의해 TEOS 산화막, SiH4산화막 또는 실리콘 과다 산화막등으로 형성되며, 이들 막(14 및 16)은 SOG막(15)에 함유된 수분이 외방확산되는 것을 방지하면서 금속배선간을 전기적으로 절연시킨다. SOG막(15)은 하부 금속배선(13)이 조밀하게 형성됨에 의해 생기는 갭(gap)을 매우기 위해 스핀방식으로 제 1 절연막(14)상에 형성된다.In the above, each of the first and second insulating films 14 and 16 is formed of a TEOS oxide film, an SiH 4 oxide film or an excessive silicon oxide film by plasma chemical vapor deposition, and these films 14 and 16 are formed on the SOG film 15. Electrically insulates the metal wires while preventing the moisture from spreading outward. The SOG film 15 is formed on the first insulating film 14 in a spin manner in order to fill gaps caused by the densely formed lower metal wiring 13.
제 2B 도는 금속배선 공정을 통해 비아홀(17)을 포함한 제 2 절연막(16)상에 상부 금속배선(18)을 형성한 것이 도시된다. 종래와는 달리 비아홀(17)의 측벽으로 노출된 SOG막(15)의 표면에 경화층(20)을 형성하므로 SOG막(15)으로 부터의 수분 방출이 억제되어 양호한 층덮힘성을 가지게 하므로 단선으로 인한 불량을 최소화시킨다. 또한 우수한 층덮힘성을 가진 금속배선 구조는 소자의 동작시 금속원자의 이동현상으로 인한 단선불량현상을 억제할 수 있으므로 소자의 신뢰성을 향상시킬 수 있다.2B or the upper metal wiring 18 is formed on the second insulating film 16 including the via hole 17 through the metal wiring process. Unlike the related art, since the hardened layer 20 is formed on the surface of the SOG film 15 exposed through the sidewalls of the via hole 17, moisture emission from the SOG film 15 is suppressed to have a good layer covering property. Minimize defects caused by In addition, the metallization structure having excellent layer covering property can suppress the disconnection phenomenon caused by the movement of metal atoms during the operation of the device, thereby improving the reliability of the device.
상술한 바와같이 본 발명은 SOG막이 일부 노출되는 비아홀을 형성한 후, 급속열처리를 통해 SOG막내의 수분을 제거함과 동시에 노출된 SOG막의 표면에 치밀화된 경화층이 형성되도록 한다.As described above, the present invention forms a via hole in which the SOG film is partially exposed, and then removes water in the SOG film through rapid heat treatment and simultaneously forms a densified cured layer on the exposed surface of the SOG film.
따라서, 본 발명은 비아홀의 측벽에 노출된 SOG막의 표면에 경화층을 형성하므로써, SOG막 내부로 수분유입현상을 억제하는 한편 고온에서 금속막 증착시 비아홀 측벽면에 노출된 SOG막으로 부터의 수분 방출을 억제하여 금속막의 층덮힘성을개선시키므로 단선으로 인한 불량이 감소되어 수율이 증가되고, 소자의 동작으로 인한 단선의 가능성을 최소화하여 소자의 신뢰성을 증가시킬 수 있을 뿐만 아니라 보다 고집적한 소자의 제조를 실현할 수 있게한다.Therefore, the present invention forms a cured layer on the surface of the SOG film exposed on the sidewalls of the via holes, thereby suppressing water inflow into the SOG film, while moisture from the SOG film exposed on the sidewalls of the via holes when the metal film is deposited at a high temperature. By suppressing the emission to improve the layer coverage of the metal film, defects due to disconnection are reduced, yield is increased, and the reliability of the device can be increased by minimizing the possibility of disconnection due to the operation of the device. To realize.
제 1A 및 1B 도는 종래 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining the method of manufacturing a conventional semiconductor device.
제 2A 및 2B 도는 본 발명의 실시예에 의한 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도.2A and 2B are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1, 11: 실리콘 기판 2, 12: 폴리-금속 층간절연막1, 11: silicon substrate 2, 12: poly-metal interlayer insulating film
3, 13: 하부 금속배선 4, 14: 제 1 절연막3, 13: lower metal wiring 4, 14: first insulating film
5, 15: SOG막 6, 16: 제 2 절연막5, 15: SOG film 6, 16: Second insulating film
7, 17: 비아홀 8, 18: 상부 금속배선7, 17: via hole 8, 18: upper metal wiring
10: 부식층 20: 경화층10: corrosion layer 20: hardened layer
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