KR20010061583A - A method for forming damascene metal wire in semiconductor device - Google Patents
A method for forming damascene metal wire in semiconductor device Download PDFInfo
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- KR20010061583A KR20010061583A KR1019990064079A KR19990064079A KR20010061583A KR 20010061583 A KR20010061583 A KR 20010061583A KR 1019990064079 A KR1019990064079 A KR 1019990064079A KR 19990064079 A KR19990064079 A KR 19990064079A KR 20010061583 A KR20010061583 A KR 20010061583A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속배선 형성 공정에 관한 것이며, 더 자세히는 사용한 대머신(damascene) 금속배선 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a metal wiring forming process in a semiconductor device manufacturing process, and more particularly, to a damascene metal wiring forming process used.
반도체 소자의 고집적화에 따라 디자인 룰(design rule)의 축소가 가속되고 있으며, 이에 따라 금속배선의 피치(pitch)가 줄어들고 있어 통상적인 금속배선 공정을 적용할 경우에는 고단차비를 가지는 금속배선의 형성시 금속배선의 CD(critical dimension) 균일도(uniformity), 라인 식각 프로파일(line etch profile) 및 포토레지스트의 식각 선택비 등에서 만족할만한 결과를 얻기 힘들게 되었다. 이를 개선하기 위해서는 하드 마스크(hard mask) 등을 사용하여야 하며, 이에 따른 제조비용의 증가와 소자 개발 일정의 지연이라는 문제점이 도출된다.As the integration of semiconductor devices increases, the reduction of design rules is accelerating. As a result, the pitch of metal wiring is reduced. Therefore, when a metal wiring having a high step ratio is formed when a conventional metal wiring process is applied. Satisfactory results have not been obtained in the CD (critical dimension) uniformity of the metallization, the line etch profile and the etching selectivity of the photoresist. In order to improve this, a hard mask should be used, which leads to an increase in manufacturing cost and delay in device development schedule.
한편, 상감형 금속배선 공정은 상기의 문제점을 해결할 수 있는 기술로 차세대 초고집적 소자에 적용이 유망하다. 한편, 금속 원소, 특히 구리는 실리콘이나, 층간절연막으로 사용되는 산화막, 저유전율막 등에 확산/침투하는 경향이 크고, 특히 실리콘 소자의 접합(junction) 등에 불순물로 작용하여, 소위 딥 레벨 디펙트(deep level defect)라 불리우는 또 다른 불순물 에너지 준위를 형성하여 소자의 오동작을 야기할 우려가 있다. 때문에, 금속배선에는 거의 필수적으로 확산방지막을 적용하고 있다.On the other hand, the damascene metal wiring process is a technology that can solve the above problems is likely to be applied to the next generation ultra-high integration device. On the other hand, metallic elements, especially copper, tend to diffuse / infiltrate into silicon, oxide films used as interlayer insulating films, low dielectric constant films, and the like, and act as impurities in junctions of silicon devices, and so-called deep level defects ( Another impurity energy level, called a deep level defect, may be formed, causing the device to malfunction. Therefore, diffusion barriers are almost always applied to metal wirings.
첨부된 도면 도 1a 내지 도 1c는 종래기술에 따른 듀얼 대머신 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A to 1C illustrate a dual damascene metal wiring forming process according to the prior art, which will be described below with reference to the drawings.
종래기술에 따른 듀얼 대머신 금속배선 형성 공정은, 우선 도 1a에 도시된바와 같이 소정의 공정을 마친 하부층(10) 상에 하부 구리배선(12) 및 층간절연막(11)을 형성하고, 전체 구조 상부에 제1 확산방지막(13)을 증착한다. 이어서, 전체 구조 상부에 저유전율 층간절연막(14) 및 비아홀 형성용 하드마스크막(15)을 증착하고 비아홀 형성 영역의 하드마스크막(15)을 선택적으로 제거한 다음, 다시 저유전율 층간절연막(16) 및 라인용 하드마스크막(17)을 증착하고 금속배선 마스크를 사용한 사진 및 식각 공정을 실시하여 듀얼 대머신 타입의 비아홀 및 라인용 트렌치를 형성한다. 한편, 제1 확산방지막(13) 식각시에 하부 구리배선(12)이 노출되면서 재스퍼터링(re-sputtering)된 구리(Cu++)가 저유전율 층간 절연막(14, 16)의 측벽에 흡착/확산된다.In the process of forming a dual damascene metal wiring according to the prior art, first, as shown in FIG. 1A, a lower copper wiring 12 and an interlayer insulating film 11 are formed on a lower layer 10 that has undergone a predetermined process, and has an overall structure. The first diffusion barrier 13 is deposited on the top. Subsequently, the low dielectric constant interlayer insulating film 14 and the via hole forming hard mask film 15 are deposited on the entire structure, the hard mask film 15 in the via hole forming region is selectively removed, and then the low dielectric constant interlayer insulating film 16 is again formed. And depositing a line hard mask film 17 and performing a photolithography and etching process using a metallization mask to form a dual damascene type via hole and a line trench. Meanwhile, when the first diffusion barrier 13 is etched, the lower copper wiring 12 is exposed and re-sputtered copper (Cu ++ ) is adsorbed to the sidewalls of the low dielectric constant interlayer insulating films 14 and 16. Spreads.
다음으로, 도 1b에 도시된 바와 같이 습식 세정 공정을 실시하여 구리에 의해 오염된 영역을 제거한다. 이때, 저유전율 층간절연막(14, 16)의 측벽 프로파일이 열화된다.Next, a wet cleaning process is performed as shown in FIG. 1B to remove the areas contaminated with copper. At this time, the sidewall profiles of the low dielectric constant interlayer insulating films 14 and 16 deteriorate.
계속하여, 도 1c에 도시된 바와 같이 전체 구조 표면을 따라 제2 확산방지막(18)을 증착하고, 상부 구리배선 형성을 위한 구리 시드(seed)층(19a) 및 구리막(19b)을 형성한 다음, 화학·기계적 평탄화(CMP) 공정을 실시하여 상부 구리배선을 형성한다. 이때, 구리막(19b) 형성을 위해서는 전해도금법 또는 화학기상증착법 등을 사용할 수 있으며, 비아홀 및 라인용 트렌치의 측벽을 이루는 저유전율 층간절연막(14, 16)의 손상으로 인하여 제2 확산방지막(18)의 스텝 커버리지가 열악해지고, 이로 인하여 구리 시드층(19a)이 불균일하게 형성되며 구리막(19b) 형성시 보이드(void)(A)가 형성되는 문제점이 있었다.Subsequently, as shown in FIG. 1C, a second diffusion barrier film 18 is deposited along the entire structure surface, and a copper seed layer 19a and a copper film 19b are formed to form upper copper wiring. Next, a chemical and mechanical planarization (CMP) process is performed to form the upper copper wiring. In this case, an electroplating method or a chemical vapor deposition method may be used to form the copper film 19b, and the second diffusion barrier layer 18 may be damaged due to damage of the low dielectric constant interlayer insulating films 14 and 16 forming sidewalls of the via hole and the trench for the line. ), The step coverage is poor, which causes the copper seed layer 19a to be unevenly formed and void A when the copper film 19b is formed.
상기와 같은 문제점을 고려하여, 구리에 의한 오염 영역을 제거하기 위해 습식 세정을 실시하지 않고 수소를 이용한 반응성 건식 세정(reactive dry cleaning)을 실시하는 방법이 제안되었으나, 이 방법은 구리에 의한 측벽 오염 방지 효과가 떨어지는 문제점이 있다.In view of the above problems, a method of performing reactive dry cleaning using hydrogen without wet cleaning to remove the contaminated area by copper has been proposed. There is a problem that the prevention effect is inferior.
한편, 이와 같은 문제점은 비아홀 식각시 하부 금속배선이 노출되는데 기인한 것으로, 비아홀 식각시 하부 금속배선을 노출시키지 않도록 하부 금속배선 상부의 확산방지막을 잔류시키면 해결 가능하지만, 이 경우 접촉 저항의 증가의 문제점이 발생하게 된다. 물론 비저항이 매우 낮은 물질을 확산방지막으로 사용하면 접촉 저항 증가를 방지할 수는 있으나, 이처럼 비저항이 매우 낮으면서 확산방지력을 확보할 수 있는 물질을 얻기가 쉽지 않아 공정 마진이 매우 작아지게 된다.On the other hand, such a problem is caused by the lower metal wiring exposed during the via hole etching, which can be solved by leaving the diffusion barrier on the lower metal wiring so as not to expose the lower metal wiring during the via hole etching. Problems will arise. Of course, if a material having a very low resistivity is used as the diffusion barrier, it is possible to prevent an increase in contact resistance. However, the process margin is very small because it is not easy to obtain a material having a low resistivity and a diffusion barrier.
상기의 문제점들은 비단 구리 금속배선에 국한되지 않고 알루미늄, 알루미늄 합금, 텅스텐 등 다른 금속을 사용하는 경우에도 발생하고 있다.The above problems are not limited to copper metal wiring but also occur when using other metals such as aluminum, aluminum alloy, tungsten and the like.
본 발명은 대머신 금속배선 형성을 위한 라인용 트렌치 및 비아홀 식각시 노출된 하부 금속배선으로부터의 재스퍼터링에 의한 층간절연막 측벽의 금속성 오염을 방지할 수 있는 반도체 소자의 대머신 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method for forming metal wires in a semiconductor device capable of preventing metallic contamination of sidewalls of an interlayer dielectric layer by re-sputtering from a line trench for forming metal wires and a lower metal wire exposed during etching of via holes. Its purpose is to.
도 1a 내지 도 1c는 종래기술에 따른 듀얼 대머신 금속배선 형성 공정도.1a to 1c is a dual damascene metallization process diagram according to the prior art.
도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 듀얼 대머신 금속배선 형성 공정도.2A to 2C are diagrams illustrating a dual damascene metal wiring forming process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 하부층 21 : 층간절연막20: lower layer 21: interlayer insulating film
22 : 하부 구리배선 23 : 제1 확산방지막22: lower copper wiring 23: first diffusion barrier
24, 26 : 저유전율 층간절연막 25 : 비아홀 형성용 하드마스크막24, 26: low dielectric constant interlayer insulating film 25: hard mask film for via hole formation
27 : 라인용 하드마스크막 28 : 제2 확산방지막27: line hard mask film 28: second diffusion barrier film
29a : 구리 시드층 29b : 구리막29a: copper seed layer 29b: copper film
상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 소자의 대머신 금속배선 형성방법은, 하부 금속배선 및 그 간극을 매립하는 절연막이 형성된 전체 구조 상부에 제1 확산방지막을 형성하는 제1 단계; 상기 제1 확산방지막 상에 소정의 층간절연막 및 하드마스크막을 형성하는 제2 단계; 상기 층간절연막 및 상기 하드마스크막을 선택 식각하여 라인용 트렌치 및 비아홀을 형성하되, 상기 하부 금속배선이 노출되지 않도록 상기 제1 확산방지막을 잔류시키는 제3 단계; 상기 제3 단계를 마친 전체 구조 표면을 따라 제2 확산방지막을 형성하는 제4 단계; 상기 제2 확산방지막을 전면 건식식각하여 상기 라인용 트렌치 및 비아홀 측벽을 덮도록 잔류시키는 제5 단계; 상기 제5 단계 수행 후 노출된 상기 제1 확산방지막을 제거하는 제6 단계; 및 상기 라인용 트렌치 및 비아홀 내에 상부 금속배선용 금속막을 매립하는 제7 단계를 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of forming a metallization of a semiconductor device in a semiconductor device, the first step of forming a first diffusion barrier layer over an entire structure in which an insulating layer filling a lower metal wiring and a gap is formed. ; Forming a predetermined interlayer insulating film and a hard mask film on the first diffusion barrier film; A third step of selectively etching the interlayer insulating layer and the hard mask layer to form trenches and via holes for the lines, and leaving the first diffusion barrier layer to prevent the lower metal wiring from being exposed; A fourth step of forming a second diffusion barrier along the entire structure surface of the third step; A fifth step of dry etching the second diffusion barrier layer so as to cover the sidewalls of the trench and the via hole; A sixth step of removing the first diffusion barrier film exposed after the fifth step; And a seventh step of filling the upper metal wiring metal film in the line trench and the via hole.
즉, 본 발명은 대머신 금속배선 형성을 위한 라인용 트렌치 및 비아홀 식각시 하부 금속배선이 노출되지 않도록 제1 확산방지막(예컨대, 실리콘질화막, 실리콘산화질화막 등)을 잔류시키고, 라인용 트렌치 및 비아홀 측벽을 제2 확산방지막(예컨대, TiNx, Ta, TaNx, TaCx, WxN, TiSiNx, WSiNx등)으로 덮은 상태에서 제1 확산방지막을 식각함으로써 하부 금속배선으로부터의 재스퍼터링에 의한 금속성 오염을 근본적으로 방지할 수 있다. 본 발명에서는 하부 금속배선과 상부 금속배선이 집적 접촉하게 되므로, 제1 확산방지막의 비저항이 낮더라도 접촉 저항의 증가는 일어나지 않게 되며, 이에 따라 확산방지막에 대한 선택의 폭을 넓힐 수 있다.That is, according to the present invention, the first diffusion barrier layer (eg, silicon nitride layer, silicon oxynitride layer, etc.) is left to prevent the lower metal line from being exposed during the etching of the line trench and the via hole for forming the metallization of the damascene line. By etching the first diffusion barrier while the sidewall is covered with a second diffusion barrier (eg, TiN x , Ta, TaN x , TaC x , W x N, TiSiN x , WSiN x, etc.), the resputtering from the lower metal wiring is performed. It is possible to fundamentally prevent the metallic contamination caused by. In the present invention, since the lower metal interconnection and the upper metal interconnection are integrated in contact with each other, even if the specific resistance of the first diffusion barrier is low, the increase in contact resistance does not occur, thereby increasing the range of choice for the diffusion barrier.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 듀얼 대머신 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명하기로 한다.2A to 2C illustrate a dual damascene metal wiring forming process according to an embodiment of the present invention, which will be described below with reference to the drawings.
본 실시예에 따른 듀얼 대머신 금속배선 형성 공정은, 우선 도 2a에 도시된 바와 같이 소정의 공정을 마친 하부층(20) 상에 하부 구리배선(22) 및 층간절연막(21)을 형성하고, 전체 구조 상부에 제1 확산방지막(23)을 증착한다. 제1 확산방지막(23)으로는 질소를 함유한 실리콘질화막이나 실리콘산화질화막을 사용하는 것이 바람직하다. 이어서, 전체 구조 상부에 저유전율 층간절연막(3000∼10000Å)(24) 및 비아홀 형성용 하드마스크막(25)을 증착하고 비아홀 형성 영역의 하드마스크막(25)을 선택적으로 제거한 다음, 다시 저유전율 층간절연막(3000∼10000Å)(26) 및 라인용 하드마스크막(27)을 증착하고 금속배선 마스크를 사용한 사진 및 식각 공정을 실시하여 듀얼 대머신 타입의 비아홀 및 라인용 트렌치를 형성한다. 이때, 종래와는 달리 하부 구리배선(22)이 노출되지 않도록 제1 확산방지막(23)을 잔류시킨다. 하드마스크막(25, 27)은 구리 확산 방지 특성을 갖도록 실리콘질화막이나 실리콘산화질화막을 사용하는 것이 바람직하며, 경우에 따라서는 라인용 하드마스크막(27)를 사용하지 않을 수도 있다.In the dual damascene metal wiring forming process according to the present embodiment, first, as shown in FIG. 2A, the lower copper wiring 22 and the interlayer insulating film 21 are formed on the lower layer 20 after the predetermined process is completed. The first diffusion barrier 23 is deposited on the structure. As the first diffusion barrier 23, a silicon nitride film or a silicon oxynitride film containing nitrogen is preferably used. Subsequently, a low dielectric constant interlayer insulating film (3000 to 10000 GPa) 24 and a hard mask film 25 for via hole formation are deposited on the entire structure, and the hard mask film 25 in the via hole forming region is selectively removed, and then the low dielectric constant is again applied. The interlayer insulating film (3000 to 10000 kPa) 26 and the line hard mask film 27 are deposited, and a photolithography and etching process using a metal wiring mask is performed to form a dual damascene type via hole and a line trench. At this time, unlike the prior art, the first diffusion barrier 23 is left so that the lower copper wiring 22 is not exposed. The hard mask films 25 and 27 preferably use a silicon nitride film or a silicon oxynitride film so as to have a copper diffusion preventing property, and in some cases, the line hard mask film 27 may not be used.
다음으로, 도 2b에 도시된 바와 같이 전체 구조 표면을 따라 확산방지막을 증착하고, 전면 건식식각을 수행하여 라인용 트렌치 및 비아홀 측벽에 측벽 스페이서 형태의 제2 확산방지막(28)을 형성한다. 제2 확산방지막(28)은 TiNx, Ta, TaNx, TaCx, WxN, TiSiNx, WSiNx등을 단층 또는 다층으로 사용하여 형성할 수 있으며, PVD법으로 100Å 이상 증착하고 이를 전면 건식 식각하여 라인용 트렌치 및 비아홀 측벽에 10Å 이상 잔류되도록 하거나, CVD법으로 10Å 이상 증착하고 이를 전면 건식 식각하여 라인용 트렌치 및 비아홀 측벽에 10Å 이상 잔류되도록 할 수 있다. 이때, 하부의 제1 확산방지막(23)까지 식각하여 하부 구리배선(22)을 노출시킨다.Next, as shown in FIG. 2B, the diffusion barrier layer is deposited along the entire structure surface, and the entire surface is etched to form a second diffusion barrier layer 28 in the form of sidewall spacers on the sidewall trench and via hole sidewalls. The second diffusion barrier 28 may be formed by using TiN x , Ta, TaN x , TaC x , W x N, TiSiN x , WSiN x, etc. as a single layer or a multilayer, and is deposited by PVD method at least 100 Å and the front surface thereof. The dry etching may be performed to leave 10 Å or more on the line trenches and via hole sidewalls, or may be deposited by 10 CVD or more by CVD, and the surface may be dry etched to leave 10 Å or more on the line trenches and via hole sidewalls. In this case, the lower copper interconnection 22 is exposed by etching to the lower first diffusion barrier 23.
계속하여, 도 2c에 도시된 바와 같이 전체 구조 상부에 상부 구리배선 형성을 위한 구리 시드층(29a) 및 구리막(29b)을 형성한 다음, 화학·기계적 평탄화(CMP) 공정을 실시하여 상부 구리배선을 형성한다. 이때, 구리 시드층(29a)은 물리기상증착법(PVD)을 이용하여 -50∼350℃의 온도에서 증착하거나, 화학기상증착법(CVD)을 이용하여 100∼400℃의 온도에서 50Å 이상 증착할 수 있다. 구리막(29b)은 전기도금법을 이용하여 0∼100℃의 온도에서 증착하거나, 화학기상증착법(CVD)을 이용하여 100∼400℃의 온도에서 1000Å 이상 증착할 수 있다.Subsequently, as shown in FIG. 2C, the copper seed layer 29a and the copper film 29b for forming the upper copper wirings are formed on the entire structure, followed by chemical and mechanical planarization (CMP) processes. Form the wiring. In this case, the copper seed layer 29a may be deposited at a temperature of −50 to 350 ° C. using physical vapor deposition (PVD), or may be deposited at 50 ° C. or more at a temperature of 100 to 400 ° C. using chemical vapor deposition (CVD). have. The copper film 29b may be deposited at a temperature of 0 ° C. to 100 ° C. using an electroplating method, or may be deposited at 1000 ° C. or more at a temperature of 100 ° C. to 400 ° C. using chemical vapor deposition (CVD).
상기와 같은 공정을 실시하게 되면, 하부 구리배선(22)과 상부 구리배선이 집적 접촉하게 되므로, 제1 확산방지막(23)으로 비저항이 높은 물질을 사용하더라도 접촉 저항의 증가는 일어나지 않게 되며, 이에 따라 실리콘질화막, 실리콘산화질화막 등 금속의 확산력이 우수한 물질의 다양한 적용이 가능하다. 즉, 확산방지막의 선택의 폭이 넓어 공정마진을 확보할 수 있다. 또한, 라인용 트렌치 및 비아홀 식각시 하부 구리배선(22)이 노출되는 시점에서 그 측벽에 제2 확산방지막(28)이 존재하므로 구리의 재스퍼터링에 의한 측벽 오염 문제를 근본적으로 방지할 수 있어 보이드와 같은 금속배선의 열화를 억제할 수 있다.When the above process is performed, the lower copper wiring 22 and the upper copper wiring are in contact with each other, so that even if a material having a high specific resistance is used as the first diffusion barrier 23, the increase in contact resistance does not occur. Accordingly, it is possible to apply a variety of materials having excellent diffusion force of the metal, such as silicon nitride film, silicon oxynitride film. In other words, a wider selection of diffusion barrier films can ensure process margins. In addition, since the second diffusion barrier layer 28 is present on the sidewalls when the lower copper wiring 22 is exposed during the etching of the line trench and the via hole, the sidewall contamination problem caused by the re-sputtering of copper may be fundamentally prevented. Deterioration of the metal wiring such as can be suppressed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 하부 및 상부 금속배선 재료로 구리를 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 알루미늄, 알루미늄 합금, 텅스텐 등 다른 금속을 단층 또는 다층으로 사용하여 하부 및 상부 금속배선을 형성하는 경우에도 적용될 수 있다.For example, in the above-described embodiment, a case in which copper is used as the lower and upper metal wiring materials has been described as an example, but the present invention uses lower and upper metal wirings by using other metals such as aluminum, an aluminum alloy, and tungsten as a single layer or a multilayer. It can also be applied to form.
또한, 전술한 실시예에서는 듀얼 대머신 공정을 일례로 들어 설명하였으나, 본 발명은 통상의 싱글 대머신 공정에도 적용될 수 있다.In addition, in the above-described embodiment, the dual damascene process has been described as an example, but the present invention may be applied to a conventional single damascene process.
본 발명은 대머신 금속배선 형성을 위한 라인용 트렌치 및 비아홀 식각시 노출된 하부 금속배선으로부터의 재스퍼터링에 의한 층간절연막 측벽의 금속성 오염을 근본적으로 방지할 수 있는 효과가 있으며, 하부 금속배선과 상부 금속배선이 집적 접촉하는 방식을 사용하기 때문에 확산방지막의 비저항 특성을 고려하지 않아도 되는 공정 마진 측면에서의 장점이 있다.The present invention has the effect of fundamentally preventing metallic contamination of the sidewalls of the interlayer insulating layer by re-sputtering from the lower metal wiring exposed during the etching of the via hole and via hole for forming the metallization of the damascene metal, and the lower metal wiring and the upper Since the metal wires use the integrated contact method, there is an advantage in terms of process margin in which the resistivity characteristic of the diffusion barrier layer does not have to be considered.
Claims (5)
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| KR1019990064079A KR20010061583A (en) | 1999-12-28 | 1999-12-28 | A method for forming damascene metal wire in semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451767B1 (en) * | 2001-12-22 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for forming interconnect structures of semiconductor device |
| KR100562985B1 (en) * | 2003-12-30 | 2006-03-23 | 주식회사 하이닉스반도체 | Method of forming metal wiring in flash memory device |
| KR100604803B1 (en) * | 2000-03-16 | 2006-07-26 | 삼성전자주식회사 | Method for forming contact plug for semiconductor device |
| US7550822B2 (en) | 2005-08-06 | 2009-06-23 | Samsung Electronics Co., Ltd. | Dual-damascene metal wiring patterns for integrated circuit devices |
-
1999
- 1999-12-28 KR KR1019990064079A patent/KR20010061583A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100604803B1 (en) * | 2000-03-16 | 2006-07-26 | 삼성전자주식회사 | Method for forming contact plug for semiconductor device |
| KR100451767B1 (en) * | 2001-12-22 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for forming interconnect structures of semiconductor device |
| KR100562985B1 (en) * | 2003-12-30 | 2006-03-23 | 주식회사 하이닉스반도체 | Method of forming metal wiring in flash memory device |
| US7550822B2 (en) | 2005-08-06 | 2009-06-23 | Samsung Electronics Co., Ltd. | Dual-damascene metal wiring patterns for integrated circuit devices |
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