KR20010061583A - A method for forming damascene metal wire in semiconductor device - Google Patents

A method for forming damascene metal wire in semiconductor device Download PDF

Info

Publication number
KR20010061583A
KR20010061583A KR1019990064079A KR19990064079A KR20010061583A KR 20010061583 A KR20010061583 A KR 20010061583A KR 1019990064079 A KR1019990064079 A KR 1019990064079A KR 19990064079 A KR19990064079 A KR 19990064079A KR 20010061583 A KR20010061583 A KR 20010061583A
Authority
KR
South Korea
Prior art keywords
step
film
forming
line
metal wiring
Prior art date
Application number
KR1019990064079A
Other languages
Korean (ko)
Inventor
박상균
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1019990064079A priority Critical patent/KR20010061583A/en
Publication of KR20010061583A publication Critical patent/KR20010061583A/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating

Abstract

PURPOSE: A method for forming the damascene metal line of a semiconductor device is provided to prevent the sidewall from polluting due to the re-sputtering of copper by forming the second diffusion barrier when a lower copper line is exposed in the etching process of a trench for line and a via hole. CONSTITUTION: In the etching process of a trench for line and a via hole, the first diffusion barrier(23) is left not to expose a lower metal line(22). The first diffusion barrier(23) is made of a silicon nitride film, a silicon oxide nitride film and so on. While the trench for line and the via hole is covered with the second diffusion barrier(28), the first diffusion barrier(23) is etched. The second diffusion barrier(28) is the type of a sidewall spacer.

Description

반도체 소자의 대머신 금속배선 형성방법{A METHOD FOR FORMING DAMASCENE METAL WIRE IN SEMICONDUCTOR DEVICE} Damascene metal wiring formation method of a semiconductor device {A METHOD FOR FORMING DAMASCENE METAL WIRE IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속배선 형성 공정에 관한 것이며, 더 자세히는 사용한 대머신(damascene) 금속배선 형성 공정에 관한 것이다. The invention relates to that, in particular semiconductor device manufacturing metal wiring forming step of the process relates to a semiconductor manufacturing technology, in more detail, to a machine stand (damascene) wiring metal forming process used.

반도체 소자의 고집적화에 따라 디자인 룰(design rule)의 축소가 가속되고 있으며, 이에 따라 금속배선의 피치(pitch)가 줄어들고 있어 통상적인 금속배선 공정을 적용할 경우에는 고단차비를 가지는 금속배선의 형성시 금속배선의 CD(critical dimension) 균일도(uniformity), 라인 식각 프로파일(line etch profile) 및 포토레지스트의 식각 선택비 등에서 만족할만한 결과를 얻기 힘들게 되었다. And a reduction in design rules (design rule) is accelerated in accordance with high integration of semiconductor devices, so that when applying a conventional metal wiring process it reduces the pitch (pitch) of the metal wiring at the time of formation of the metal wiring having a high-stage fare was difficult to obtain satisfactory results, etc. CD (critical dimension) uniformity (uniformity) of the metal interconnection, the etch profile line (line etch profile) and the etching selectivity ratio of the photoresist. 이를 개선하기 위해서는 하드 마스크(hard mask) 등을 사용하여야 하며, 이에 따른 제조비용의 증가와 소자 개발 일정의 지연이라는 문제점이 도출된다. In order to improve this and to be used for a hard mask (hard mask), this problem of increasing the delay of the development schedule of the device manufacturing cost accordingly is derived.

한편, 상감형 금속배선 공정은 상기의 문제점을 해결할 수 있는 기술로 차세대 초고집적 소자에 적용이 유망하다. On the other hand, inlaid metal wiring process can be applied to next-generation highly integrated device is promising as a second technique that can solve the above problems. 한편, 금속 원소, 특히 구리는 실리콘이나, 층간절연막으로 사용되는 산화막, 저유전율막 등에 확산/침투하는 경향이 크고, 특히 실리콘 소자의 접합(junction) 등에 불순물로 작용하여, 소위 딥 레벨 디펙트(deep level defect)라 불리우는 또 다른 불순물 에너지 준위를 형성하여 소자의 오동작을 야기할 우려가 있다. On the other hand, the metal elements, in particular copper, silicon, or large and an oxide film, a tendency to diffusion / penetration or the like with a low dielectric constant film used as the interlayer insulating film, in particular, acts as an impurity or the like junction (junction) of the silicon element, a so-called deep level defect ( forming a deep level defect) called an impurity energy level to another there is a possibility to cause the malfunction of the device. 때문에, 금속배선에는 거의 필수적으로 확산방지막을 적용하고 있다. Accordingly, there is applied a diffusion barrier in much the essential metal wiring.

첨부된 도면 도 1a 내지 도 1c는 종래기술에 따른 듀얼 대머신 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다. The accompanying drawings, Fig. 1a to Fig. 1c is shown to have a dual damascene metal interconnection forming step according to the prior art is now described with reference to.

종래기술에 따른 듀얼 대머신 금속배선 형성 공정은, 우선 도 1a에 도시된바와 같이 소정의 공정을 마친 하부층(10) 상에 하부 구리배선(12) 및 층간절연막(11)을 형성하고, 전체 구조 상부에 제1 확산방지막(13)을 증착한다. A dual damascene metal interconnection forming step according to the prior art, first forming a lower copper wiring 12 and the interlayer insulating film 11 on a lower layer (10) completing the predetermined process, as shown in Figure 1a, and the entire structure and depositing a first diffusion preventing film 13 to the top. 이어서, 전체 구조 상부에 저유전율 층간절연막(14) 및 비아홀 형성용 하드마스크막(15)을 증착하고 비아홀 형성 영역의 하드마스크막(15)을 선택적으로 제거한 다음, 다시 저유전율 층간절연막(16) 및 라인용 하드마스크막(17)을 증착하고 금속배선 마스크를 사용한 사진 및 식각 공정을 실시하여 듀얼 대머신 타입의 비아홀 및 라인용 트렌치를 형성한다. Then, the low-dielectric-constant interlayer insulating film 14 and depositing a via-hole film hard mask 15 for the formation and selective removal of the hard mask layer 15 in the via hole formation region, and then again with a low dielectric constant interlayer insulating film 16 on the entire structure, the top conducting line and photo and etching processes for depositing the hard mask film 17 and used for the metallization mask to form a trench for a via hole and a line of a dual damascene type. 한편, 제1 확산방지막(13) 식각시에 하부 구리배선(12)이 노출되면서 재스퍼터링(re-sputtering)된 구리(Cu ++ )가 저유전율 층간 절연막(14, 16)의 측벽에 흡착/확산된다. On the other hand, the suction on the side wall of the first diffusion preventing film 13. As the lower copper wiring 12 is exposed at the time of etching the sputtering material (re-sputtering), copper (Cu ++) have a low dielectric constant interlayer insulating film (14, 16) / It is dispersed.

다음으로, 도 1b에 도시된 바와 같이 습식 세정 공정을 실시하여 구리에 의해 오염된 영역을 제거한다. Next, remove the contaminated zone by the copper subjected to the wet cleaning process, as illustrated in Figure 1b. 이때, 저유전율 층간절연막(14, 16)의 측벽 프로파일이 열화된다. At this time, the low dielectric constant of the interlayer insulating film side wall profile 14, 16 is deteriorated.

계속하여, 도 1c에 도시된 바와 같이 전체 구조 표면을 따라 제2 확산방지막(18)을 증착하고, 상부 구리배선 형성을 위한 구리 시드(seed)층(19a) 및 구리막(19b)을 형성한 다음, 화학·기계적 평탄화(CMP) 공정을 실시하여 상부 구리배선을 형성한다. Then, depositing a second diffusion preventing film (18) along the entire structure surface to form a copper seed (seed) layer (19a) and a copper film (19b) for the top copper wiring formed as shown in Figure 1c and then subjected to chemical and mechanical planarization (CMP) process to form the upper part of copper wiring. 이때, 구리막(19b) 형성을 위해서는 전해도금법 또는 화학기상증착법 등을 사용할 수 있으며, 비아홀 및 라인용 트렌치의 측벽을 이루는 저유전율 층간절연막(14, 16)의 손상으로 인하여 제2 확산방지막(18)의 스텝 커버리지가 열악해지고, 이로 인하여 구리 시드층(19a)이 불균일하게 형성되며 구리막(19b) 형성시 보이드(void)(A)가 형성되는 문제점이 있었다. At this time, the second diffusion preventing film (18, due to damage of the copper film (19b) may be used as the electrolytic plating or chemical vapor deposition in order to form via holes and lines with a low dielectric constant interlayer insulating film (14, 16) forming the side walls of the trench for ), there is a problem in that a step coverage becomes poor, which results a copper seed layer (19a) is non-uniformly formed and forming a void (void) (a) when forming the copper film (19b) of.

상기와 같은 문제점을 고려하여, 구리에 의한 오염 영역을 제거하기 위해 습식 세정을 실시하지 않고 수소를 이용한 반응성 건식 세정(reactive dry cleaning)을 실시하는 방법이 제안되었으나, 이 방법은 구리에 의한 측벽 오염 방지 효과가 떨어지는 문제점이 있다. In consideration of the above problems, has been proposed a method of carrying out a reactive dry-cleaning (reactive dry cleaning) using the hydrogen does not have a wet cleaning to eliminate polluted area by the copper, the method sidewall contamination by copper there is an effect of preventing dripping problems.

한편, 이와 같은 문제점은 비아홀 식각시 하부 금속배선이 노출되는데 기인한 것으로, 비아홀 식각시 하부 금속배선을 노출시키지 않도록 하부 금속배선 상부의 확산방지막을 잔류시키면 해결 가능하지만, 이 경우 접촉 저항의 증가의 문제점이 발생하게 된다. On the other hand, such a problem is a via hole that etching when the lower metal wiring is exposed there is caused, resolved when the residual via holes film etching when the lower metal wiring to not lower metal wiring upper diffusion of the so exposed is possible, but in this case the increase of contact resistance problems will occur. 물론 비저항이 매우 낮은 물질을 확산방지막으로 사용하면 접촉 저항 증가를 방지할 수는 있으나, 이처럼 비저항이 매우 낮으면서 확산방지력을 확보할 수 있는 물질을 얻기가 쉽지 않아 공정 마진이 매우 작아지게 된다. Of course, the specific resistance is to use a very low material as a diffusion barrier to prevent the contact resistance is increased. However, this way becomes the resistivity is very low flew not easy to obtain a material capable of ensuring the diffusion preventing ability significantly reduces the processing margin.

상기의 문제점들은 비단 구리 금속배선에 국한되지 않고 알루미늄, 알루미늄 합금, 텅스텐 등 다른 금속을 사용하는 경우에도 발생하고 있다. The problems are caused even when using another metal, such as silk, but is not limited to copper metal wiring of aluminum, aluminum alloy, and tungsten.

본 발명은 대머신 금속배선 형성을 위한 라인용 트렌치 및 비아홀 식각시 노출된 하부 금속배선으로부터의 재스퍼터링에 의한 층간절연막 측벽의 금속성 오염을 방지할 수 있는 반도체 소자의 대머신 금속배선 형성방법을 제공하는데 그 목적이 있다. The present invention provides a damascene metal wiring formation method of a semiconductor device capable of preventing metallic contamination of the interlayer insulating film side wall by the material sputtered from the underlying metal wiring exposed during line trenches and via holes etched for for a damascene metal line formed to have its purpose.

도 1a 내지 도 1c는 종래기술에 따른 듀얼 대머신 금속배선 형성 공정도. Figure 1a to 1c is a dual damascene metal interconnection forming step according to the prior art.

도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 듀얼 대머신 금속배선 형성 공정도. Figures 2a to 2c is a dual damascene metal interconnection forming step according to one embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 * Description of the Related Art

20 : 하부층 21 : 층간절연막 20: lower layer 21: insulating film between layers

22 : 하부 구리배선 23 : 제1 확산방지막 22: the lower copper interconnection 23: first diffusion barrier film

24, 26 : 저유전율 층간절연막 25 : 비아홀 형성용 하드마스크막 24, 26: low-dielectric-constant interlayer insulating film 25 as hard mask layer for forming via holes

27 : 라인용 하드마스크막 28 : 제2 확산방지막 27: line for the hard mask layer 28: second diffusion barrier film

29a : 구리 시드층 29b : 구리막 29a: copper seed layer 29b: copper film

상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 소자의 대머신 금속배선 형성방법은, 하부 금속배선 및 그 간극을 매립하는 절연막이 형성된 전체 구조 상부에 제1 확산방지막을 형성하는 제1 단계; A first step of forming a first diffusion preventing film on the entire structure, the top two machine metal wiring formation method of a characteristic semiconductor device of the present invention to an aspect of the lower metal wiring and an insulating film burying the gap formed .; 상기 제1 확산방지막 상에 소정의 층간절연막 및 하드마스크막을 형성하는 제2 단계; A second step of forming said first diffusion barrier onto a predetermined interlayer insulating film and hard mask; 상기 층간절연막 및 상기 하드마스크막을 선택 식각하여 라인용 트렌치 및 비아홀을 형성하되, 상기 하부 금속배선이 노출되지 않도록 상기 제1 확산방지막을 잔류시키는 제3 단계; The interlayer insulating film and a third step of forming a line, but the trench and via hole by selecting for etching the hard mask film, the residual of the first diffusion preventing film not to the lower metal wiring is exposed; 상기 제3 단계를 마친 전체 구조 표면을 따라 제2 확산방지막을 형성하는 제4 단계; A fourth step of forming a second diffusion barrier along the entire structure surface finishing the third step; 상기 제2 확산방지막을 전면 건식식각하여 상기 라인용 트렌치 및 비아홀 측벽을 덮도록 잔류시키는 제5 단계; A fifth step of remaining in the second diffusion preventing film front dry etching so as to cover the trench and the via hole side wall for the line; 상기 제5 단계 수행 후 노출된 상기 제1 확산방지막을 제거하는 제6 단계; A sixth step of removing the barrier film of the first diffusion exposed after performing the fifth step; 및 상기 라인용 트렌치 및 비아홀 내에 상부 금속배선용 금속막을 매립하는 제7 단계를 포함하여 이루어진다. And it comprises a seventh step of embedding the upper metal wiring metal film in the trench and the via hole for the line.

즉, 본 발명은 대머신 금속배선 형성을 위한 라인용 트렌치 및 비아홀 식각시 하부 금속배선이 노출되지 않도록 제1 확산방지막(예컨대, 실리콘질화막, 실리콘산화질화막 등)을 잔류시키고, 라인용 트렌치 및 비아홀 측벽을 제2 확산방지막(예컨대, TiN x , Ta, TaN x , TaC x , W x N, TiSiN x , WSiN x 등)으로 덮은 상태에서 제1 확산방지막을 식각함으로써 하부 금속배선으로부터의 재스퍼터링에 의한 금속성 오염을 근본적으로 방지할 수 있다. That is, the present invention is to avoid the lower metal wiring is exposed when the line trenches and via holes etched for for a damascene metal line forming the first diffusion preventing film and the residual (e.g., silicon nitride film, a silicon nitride oxide and the like), line trenches and via holes for the side wall of the material sputtered from the lower metal interconnection by etching the second diffusion barrier film first diffusion in a state covered with (e.g., TiN x, Ta, TaN x , TaC x, W x N, TiSiN x, WSiN x , etc.) by may essentially prevent the metal contamination. 본 발명에서는 하부 금속배선과 상부 금속배선이 집적 접촉하게 되므로, 제1 확산방지막의 비저항이 낮더라도 접촉 저항의 증가는 일어나지 않게 되며, 이에 따라 확산방지막에 대한 선택의 폭을 넓힐 수 있다. Since in the present invention, the lower metal line with an upper metal wiring to the integrated contact, the specific resistance of the first diffusion preventing film is low even if the increase of the contact resistance is not occurred, thereby widen the range of selection for the diffusion preventing film.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다. It will be introduced to a preferred embodiment of the present invention to the following, to allow the present invention to make the self-of ordinary skill in the art, the present invention facilitates a more embodiments belong.

첨부된 도면 도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 듀얼 대머신 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명하기로 한다. The accompanying drawings, Figures 2a to 2c is shown to have a dual damascene metal interconnection forming step according to one embodiment of the invention, it will be described below with reference to.

본 실시예에 따른 듀얼 대머신 금속배선 형성 공정은, 우선 도 2a에 도시된 바와 같이 소정의 공정을 마친 하부층(20) 상에 하부 구리배선(22) 및 층간절연막(21)을 형성하고, 전체 구조 상부에 제1 확산방지막(23)을 증착한다. Full dual damascene metal interconnection forming step according to the present embodiment, first, and form a lower layer 20, the lower the copper wiring 22 and the interlayer insulating film 21 on the completion of the predetermined process, as shown in Figure 2a, and depositing a first diffusion preventing film 23 to the upper structure. 제1 확산방지막(23)으로는 질소를 함유한 실리콘질화막이나 실리콘산화질화막을 사용하는 것이 바람직하다. A first diffusion preventing film 23, it is preferable to use a silicon nitride film or a silicon oxynitride film containing nitrogen. 이어서, 전체 구조 상부에 저유전율 층간절연막(3000∼10000Å)(24) 및 비아홀 형성용 하드마스크막(25)을 증착하고 비아홀 형성 영역의 하드마스크막(25)을 선택적으로 제거한 다음, 다시 저유전율 층간절연막(3000∼10000Å)(26) 및 라인용 하드마스크막(27)을 증착하고 금속배선 마스크를 사용한 사진 및 식각 공정을 실시하여 듀얼 대머신 타입의 비아홀 및 라인용 트렌치를 형성한다. Then, the entire structure of the upper deposited a low-dielectric-constant interlayer dielectric (3000~10000Å) (24) and via hole formation the hard mask film 25 and for the selective removal of the hard mask layer 25 in the via hole formation region, and then again with a low dielectric constant performing inter-layer insulating film (3000~10000Å) (26) and picture line, and the etching process using a hard mask film 27 and the deposited metal wiring mask to form a trench for a via hole and a line of a dual damascene type. 이때, 종래와는 달리 하부 구리배선(22)이 노출되지 않도록 제1 확산방지막(23)을 잔류시킨다. At this time, the residue of the first diffusion preventing film 23 is not conventional and is otherwise lower the copper wiring 22 is not exposed. 하드마스크막(25, 27)은 구리 확산 방지 특성을 갖도록 실리콘질화막이나 실리콘산화질화막을 사용하는 것이 바람직하며, 경우에 따라서는 라인용 하드마스크막(27)를 사용하지 않을 수도 있다. Hard mask 25 and 27 is to have the copper diffusion barrier properties it is preferred to use a silicon nitride film or a silicon oxynitride film, as the case may or may not use the hard mask film 27 for the line.

다음으로, 도 2b에 도시된 바와 같이 전체 구조 표면을 따라 확산방지막을 증착하고, 전면 건식식각을 수행하여 라인용 트렌치 및 비아홀 측벽에 측벽 스페이서 형태의 제2 확산방지막(28)을 형성한다. Next, to form the entire structure along the surface, and depositing a diffusion barrier, by performing dry-etching film over the second spreading of the side wall spacer form on line trench and the via hole side wall (28), as shown in Figure 2b. 제2 확산방지막(28)은 TiN x , Ta, TaN x , TaC x , W x N, TiSiN x , WSiN x 등을 단층 또는 다층으로 사용하여 형성할 수 있으며, PVD법으로 100Å 이상 증착하고 이를 전면 건식 식각하여 라인용 트렌치 및 비아홀 측벽에 10Å 이상 잔류되도록 하거나, CVD법으로 10Å 이상 증착하고 이를 전면 건식 식각하여 라인용 트렌치 및 비아홀 측벽에 10Å 이상 잔류되도록 할 수 있다. A second diffusion film 28 is TiN x, Ta, TaN x, TaC x, W x N, TiSiN x, WSiN x etc. may be formed of a single layer or multiple layers, at least 100Å deposited by PVD method, and the front it It may be such that dry etching by, or to be more than 10Å remaining in the line trenches and via holes for the side wall, is deposited by CVD over 10Å and 10Å front dry etching it over the trench for lines and the via hole side wall remaining. 이때, 하부의 제1 확산방지막(23)까지 식각하여 하부 구리배선(22)을 노출시킨다. At this time, by etching to the first diffusion preventing film 23 of the lower portion to expose the underlying copper line 22. The

계속하여, 도 2c에 도시된 바와 같이 전체 구조 상부에 상부 구리배선 형성을 위한 구리 시드층(29a) 및 구리막(29b)을 형성한 다음, 화학·기계적 평탄화(CMP) 공정을 실시하여 상부 구리배선을 형성한다. Subsequently, the formation of the entire structure above the copper seed layer (29a) and a copper film (29b) for the top copper wiring formed as shown in Figure 2c, and then, chemical and subjected to mechanical planarization (CMP) process, the top copper to form a wiring. 이때, 구리 시드층(29a)은 물리기상증착법(PVD)을 이용하여 -50∼350℃의 온도에서 증착하거나, 화학기상증착법(CVD)을 이용하여 100∼400℃의 온도에서 50Å 이상 증착할 수 있다. In this case, a copper seed layer (29a) is by using a physical vapor deposition (PVD) vapor deposition at a temperature of -50~350 ℃, or chemical vapor deposition (CVD) using a depositing more than 50Å at a temperature of 100~400 ℃ have. 구리막(29b)은 전기도금법을 이용하여 0∼100℃의 온도에서 증착하거나, 화학기상증착법(CVD)을 이용하여 100∼400℃의 온도에서 1000Å 이상 증착할 수 있다. The copper film (29b) may be deposited over 1000Å at a temperature of 100~400 ℃ by a deposition, or chemical vapor deposition (CVD) at a temperature of 0~100 ℃ using an electroplating method.

상기와 같은 공정을 실시하게 되면, 하부 구리배선(22)과 상부 구리배선이 집적 접촉하게 되므로, 제1 확산방지막(23)으로 비저항이 높은 물질을 사용하더라도 접촉 저항의 증가는 일어나지 않게 되며, 이에 따라 실리콘질화막, 실리콘산화질화막 등 금속의 확산력이 우수한 물질의 다양한 적용이 가능하다. When subjected to the process as described above, since the lower the copper wiring 22 and the upper copper wiring to the integrated contact, first, even if one uses a high resistivity material diffusion preventing film 23 increase the contact resistance is not occurred, thereby along hwaksanryeok of metal such as a silicon nitride film, a silicon oxynitride film can be applied to various materials it is excellent. 즉, 확산방지막의 선택의 폭이 넓어 공정마진을 확보할 수 있다. That is, it is possible to ensure the selection of the film spread wider process margin. 또한, 라인용 트렌치 및 비아홀 식각시 하부 구리배선(22)이 노출되는 시점에서 그 측벽에 제2 확산방지막(28)이 존재하므로 구리의 재스퍼터링에 의한 측벽 오염 문제를 근본적으로 방지할 수 있어 보이드와 같은 금속배선의 열화를 억제할 수 있다. Further, the line a second diffusion barrier 28 is present, because the voids can be essentially prevented by the side wall pollution problems caused by re-sputtering of copper on the side wall at the point when the trench and via hole below the copper wiring 22 is exposed during the etching for and it is possible to suppress the deterioration of the same metal wire.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다. The present invention described above is not limited by the embodiments described above and the accompanying drawings, it is that various changes and modifications may be made without departing from the scope of the present invention in the art got to those of ordinary skill will be obvious.

예컨대, 전술한 실시예에서는 하부 및 상부 금속배선 재료로 구리를 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 알루미늄, 알루미늄 합금, 텅스텐 등 다른 금속을 단층 또는 다층으로 사용하여 하부 및 상부 금속배선을 형성하는 경우에도 적용될 수 있다. For example, in the above embodiment has been described for the case of using copper as the lower and upper metal wiring material for example, the present invention is aluminum, aluminum alloy, tungsten, etc. by using different metals as a single layer or a multi-layered bottom and top metal line It may be applied to the case of forming.

또한, 전술한 실시예에서는 듀얼 대머신 공정을 일례로 들어 설명하였으나, 본 발명은 통상의 싱글 대머신 공정에도 적용될 수 있다. Further, in the above-described embodiments it has been described containing a dual damascene process, for example, the invention can also be applied to conventional single damascene process.

본 발명은 대머신 금속배선 형성을 위한 라인용 트렌치 및 비아홀 식각시 노출된 하부 금속배선으로부터의 재스퍼터링에 의한 층간절연막 측벽의 금속성 오염을 근본적으로 방지할 수 있는 효과가 있으며, 하부 금속배선과 상부 금속배선이 집적 접촉하는 방식을 사용하기 때문에 확산방지막의 비저항 특성을 고려하지 않아도 되는 공정 마진 측면에서의 장점이 있다. The present invention has an effect capable of fundamentally preventing the metal contamination of the interlayer insulating film side wall by the material sputtered from the underlying metal wiring exposed during line trenches and via holes etched for for a damascene metal line forming a lower metal line and the upper there is an advantage in the process margin side which does not need to be considered, the specific resistance characteristic of the diffusion barrier film due to the use of how the metal wire is integrated contact.

Claims (5)

  1. 하부 금속배선 및 그 간극을 매립하는 절연막이 형성된 전체 구조 상부에 제1 확산방지막을 형성하는 제1 단계; A first step of the overall structure of the upper insulating film for burying the lower metal line and the gaps formed form the first diffusion preventing film;
    상기 제1 확산방지막 상에 소정의 층간절연막 및 하드마스크막을 형성하는 제2 단계; A second step of forming said first diffusion barrier onto a predetermined interlayer insulating film and hard mask;
    상기 층간절연막 및 상기 하드마스크막을 선택 식각하여 라인용 트렌치 및 비아홀을 형성하되, 상기 하부 금속배선이 노출되지 않도록 상기 제1 확산방지막을 잔류시키는 제3 단계; The interlayer insulating film and a third step of forming a line, but the trench and via hole by selecting for etching the hard mask film, the residual of the first diffusion preventing film not to the lower metal wiring is exposed;
    상기 제3 단계를 마친 전체 구조 표면을 따라 제2 확산방지막을 형성하는 제4 단계; A fourth step of forming a second diffusion barrier along the entire structure surface finishing the third step;
    상기 제2 확산방지막을 전면 건식식각하여 상기 라인용 트렌치 및 비아홀 측벽을 덮도록 잔류시키는 제5 단계; A fifth step of remaining in the second diffusion preventing film front dry etching so as to cover the trench and the via hole side wall for the line;
    상기 제5 단계 수행 후 노출된 상기 제1 확산방지막을 제거하는 제6 단계; A sixth step of removing the barrier film of the first diffusion exposed after performing the fifth step; And
    상기 라인용 트렌치 및 비아홀 내에 상부 금속배선용 금속막을 매립하는 제7 단계 A seventh step for embedding the upper metal wiring metal film in the trench and the via hole for the line
    를 포함하여 이루어진 반도체 소자의 대머신 금속배선 형성방법. Damascene metal wiring method for forming a semiconductor device comprising an.
  2. 제1항에 있어서, According to claim 1,
    상기 제2 단계가, The second stage is,
    상기 제1 확산방지막 상에 제1 층간절연막을 형성하는 제8 단계; An eighth step of forming a first interlayer insulating film on the first diffusion preventing film;
    상기 제1 층간절연막 상에 제1 하드마스크막을 형성하는 제9 단계; A ninth step of forming the first hard mask film on the first interlayer insulating film;
    상기 비아홀 영역의 상기 제1 하드마스크막을 선택적으로 제거하는 제10 단계; A tenth step of the first selective removal of the hard mask layer in the via hole region;
    상기 제10 단계를 마친 전체 구조 상부에 제2 층간절연막을 형성하는 제11 단계; Step 11 of forming a second interlayer insulating film on the entire structure, the upper finish the step 10; And
    상부 금속배선 마스크를 사용하여 상기 제2 층간절연막을 선택 식각하고, 노출된 상기 제1 층간절연막을 식각하는 제12 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 대머신 금속배선 형성방법. Using the upper metallization mask selecting the second interlayer dielectric film etching, and damascene metal wiring method for forming a semiconductor device characterized in that comprising an twelfth step of etching the exposed first interlayer insulating film.
  3. 제1항 또는 제2항에 있어서, According to claim 1 or 2,
    상기 제6 단계 수행 후, After performing the sixth step,
    전체 구조 상부에 금속 씨드층을 형성하는 제13 단계를 더 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 대머신 금속배선 형성방법. Damascene metal wiring formation method of a semiconductor device, characterized in that made in claim 13 further comprising the step of forming a metal seed layer on the entire upper structure.
  4. 제1항 또는 제2항에 있어서, According to claim 1 or 2,
    상기 제1 확산방지막이, The film of the first diffusion,
    실리콘질화막 또는 실리콘산화질화막인 것을 특징으로 하는 반도체 소자의 대머신 금속배선 형성방법. Damascene metal wiring formation method of a semiconductor device, characterized in that the silicon nitride or silicon nitride oxide.
  5. 제1항 또는 제2항에 있어서, According to claim 1 or 2,
    제2 확산방지막이, The diffusion prevention film of claim 2,
    TiNx, Ta, TaNx, TaCx, WxN, TiSiNx, WSiNx 중 적어도 어느 하나를 포함하여 구성된 것을 특징으로 하는 반도체 소자의 대머신 금속배선 형성방법. TiNx, Ta, TaNx, TaCx, WxN, TiSiNx, damascene metal wiring formation method of a semiconductor device, characterized in that configured to include at least one of WSiNx.
KR1019990064079A 1999-12-28 1999-12-28 A method for forming damascene metal wire in semiconductor device KR20010061583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990064079A KR20010061583A (en) 1999-12-28 1999-12-28 A method for forming damascene metal wire in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990064079A KR20010061583A (en) 1999-12-28 1999-12-28 A method for forming damascene metal wire in semiconductor device

Publications (1)

Publication Number Publication Date
KR20010061583A true KR20010061583A (en) 2001-07-07

Family

ID=19631397

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990064079A KR20010061583A (en) 1999-12-28 1999-12-28 A method for forming damascene metal wire in semiconductor device

Country Status (1)

Country Link
KR (1) KR20010061583A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7550822B2 (en) 2005-08-06 2009-06-23 Samsung Electronics Co., Ltd. Dual-damascene metal wiring patterns for integrated circuit devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7550822B2 (en) 2005-08-06 2009-06-23 Samsung Electronics Co., Ltd. Dual-damascene metal wiring patterns for integrated circuit devices

Similar Documents

Publication Publication Date Title
US9508593B1 (en) Method of depositing a diffusion barrier for copper interconnect applications
US9219036B2 (en) Interconnect structure for semiconductor devices
US7998855B2 (en) Solving via-misalignment issues in interconnect structures having air-gaps
US8420533B2 (en) Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding
KR100530306B1 (en) Electronic structure
EP1233448B1 (en) Reliable interconnects with low via/contact resistance
US6383920B1 (en) Process of enclosing via for improved reliability in dual damascene interconnects
EP0561132B1 (en) Method of forming a conformal refractory metal layer in a submicron opening
US7256121B2 (en) Contact resistance reduction by new barrier stack process
US6656841B1 (en) Method of forming multi layer conductive line in semiconductor device
US8178437B2 (en) Barrier material and process for Cu interconnect
EP0506426B1 (en) Integrated circuit metallization with zero contact enclosure requirements and method of making the same
US7553756B2 (en) Process for producing semiconductor integrated circuit device
US8232196B2 (en) Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for BEOL integration
US6465888B2 (en) Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
US7393777B2 (en) Sacrificial metal spacer damascene process
JP4516640B2 (en) Method for forming interconnect structure in semiconductor device
US6258710B1 (en) Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US8664766B2 (en) Interconnect structure containing non-damaged dielectric and a via gouging feature
US7541276B2 (en) Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer
US7365009B2 (en) Structure of metal interconnect and fabrication method thereof
US6949461B2 (en) Method for depositing a metal layer on a semiconductor interconnect structure
US7176571B2 (en) Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure
US6071809A (en) Methods for forming high-performing dual-damascene interconnect structures
KR100442863B1 (en) Method for fabricating semiconductor device having metal-insulator-metal capacitor and damascene wiring structure

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination