KR20000001084A - Semiconductor devices and method thereof - Google Patents

Abstract

PURPOSE: A semiconductor devices and method thereof having a silicide layer for local connecting between electrodes is provided to simplify manufacturing process. CONSTITUTION: The semiconductor devices comprises: a gate conductive layer(16) formed on an active region of a silicon substrate(10); spacers(18) having different width each other and formed at both sidewalls of the gate conductive layer(16); source and drain regions(20) formed in the active region adjacent to the edge of the gate conductive layer; and a silicide layer(26) formed on the source and drain region(20) and the gate conductive layer(16), and commonly connected to the source and drain regions(20) and the gate conductive layer(16) through the spacer(18) having narrow width.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a silicide layer for local connection between terminals of a device capable of performing the terminal-to-terminal connection process of a device in a fine local range in a simple manufacturing process. And a method for producing the same.

In general, when a memory device adopts embedded memory using a CMOS logic process, the latch implementation of GT SRAM is used by connecting an input terminal of one inverter to an output terminal of another inverter. The manufacturing process of the above SRAMs includes a contact mask / etching process for local interconnection, a conductor deposition and patterning process for local interconnection to electrically connect the input terminal of the inverter, the output terminal of the polysilicon and the inverter, and the active area. Because of this need, the manufacturing process becomes somewhat complicated.

SUMMARY OF THE INVENTION The object of the present invention is to simplify the process of connecting terminals in the local range of fine devices by forming the terminal-to-terminal connection of the devices together when forming the silicide used in the high-level process to solve the problems of the prior art as described above. A semiconductor device having a silicide layer for local connection between terminals of a device that can be implemented, and a method of manufacturing the same.

1 to 4 are flowcharts illustrating a manufacturing process of a semiconductor device having a silicide layer for local connection between terminals of a device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: silicon substrate

12: field oxide film

14: gate oxide film

16: gate conductive layer

18: spacer

20: Source / Drain Area

22: insulating film pattern

26 ': silicide layer

In order to achieve the above object, an apparatus of the present invention includes a gate conductive layer formed over an active region of a semiconductor substrate, a spacer having an asymmetric width on both sidewalls of the gate conductive layer, and an active region near the edge of the gate conductive layer. And a silicide layer formed on the source and drain regions formed on the source and drain regions and the gate conductive layer and connected to the source or drain region and the gate conductive layer in common through a spacer having a narrow width.

In order to achieve the above object, the manufacturing method of the present invention comprises the steps of forming a gate conductive layer in the active region of the semiconductor substrate, forming a spacer having the same width on the sidewall of the gate conductive layer, the edge of the gate conductive layer Forming a source / drain region in a nearby active region, selectively reducing only the width of one spacer, and a silicide for commonly connecting the narrower spacer with a neighboring source or drain region and a gate conductive layer; Forming a layer.

In the manufacturing method of the present invention, reducing the width of only one spacer includes forming an insulating film on the entire surface of the substrate on which the source / drain regions are formed, and designating a portion for interconnecting the gate conductive layer and the source or drain region. And forming an insulating layer pattern to form an insulating layer pattern, and forming a width of one spacer to have a normal thickness by forming an entire surface etching process on the entire surface of the substrate on which the pattern is formed. It features.

According to the present invention, a metal wiring process for connecting subsequent gates and source / drain regions can be shortened and securely connected by locally interconnecting a source or drain region constituting a semiconductor device and a gate conductive layer in a silicide process. A contact area can be secured.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 4 are flowcharts illustrating a manufacturing process of a semiconductor device having a silicide layer for local connection between terminals of a device according to an embodiment of the present invention.

In the manufacturing process of the present invention, first, as shown in FIG. 1, a field oxide film 12 is formed on a silicon substrate 10 to separate an active region between terminals of a device using a conventional LOCOS (LOCal Oxidation of Silicon) process. After that, the gate electrode G including the gate oxide layer 14 and the gate conductive layer 16 that are sequentially stacked on the active region of the substrate 10 is formed. After the spacer 18 is formed on the sidewall of the gate electrode G, the active region and other conductive impurities are implanted at a high concentration, so that a source is formed in the active region between the edge of the gate electrode G and the field oxide film 12. The drain region 20 is formed. Subsequently, TEOS (TetraEthlyOrthoSilicate) is deposited as an insulating film 22 on the entire substrate 10 on which the source / drain regions 20 are formed. At this time, the TEOS film 22 is deposited at a low temperature so as not to change the characteristics of the transistor.

Subsequently, as shown in FIG. 2, a photolithography process using a mask for designating a portion of the gate conductive layer 16 and the drain region 20 to be interconnected is performed to form a photoresist pattern 24 on the TEOS layer 22. Form. As the TEOS layer 22 is patterned by a wet etching process, a portion where the gate conductive layer 16 and the drain region 20 are interconnected is opened.

The pattern 24 is removed, and a blank etching process is performed to form a width of the spacer 18 on the sidewall of the gate conductive layer 16 in the source direction B to a normal thickness. The spacer 18 is relatively reduced in width and almost eliminated. In the present invention, it is important to adjust the widths of both spacers, so the etching target should be determined in consideration of the deposition thickness of the insulating film. Next, Ti 26 is deposited on the entire surface of the substrate 10 to form silicide as shown in FIG. 3.

A thermal process is performed on the wafer on which the Ti film 26 is formed. When Ti, which does not react with silicon, is removed by an etching process and recrystallized, a silicide layer 26 ′ is formed as shown in FIG. 4. The silicide layer 26 ′ may form a bridge as the diffusion distance between the poly silicon of the gate conductive layer 16 and the silicon of the drain region 20 is shortened through the narrow spacers, thereby forming a bridge between the gate electrode G and the gate electrode G. FIG. It also acts as a connection contact between the drain regions 20.

The present invention provides an additional local terminal connection process after the silicide process, for example contact mask, etching, conductor deposition, in contrast to the prior art in the terminal connection process of the device. Since the manufacturing process, such as a mask and an etching, is not necessary, the manufacturing process becomes very simple. In addition, the present invention has an effect that can always provide a stable contact characteristics because the entire poly gate surface serves as a contact even if misalignment occurs in the mask process.

Claims (3)

A gate conductive layer formed over the active region of the semiconductor substrate; Spacers having an asymmetric width on both sidewalls of the gate conductive layer; A source and drain region formed in an active region near the edge of the gate conductive layer; And a silicide layer formed on the source and drain regions and the gate conductive layer and connected to the source or drain region and the gate conductive layer in common through a narrow spacer. Forming a gate conductive layer in an active region of the semiconductor substrate; Forming spacers having the same width on sidewalls of the gate conductive layer; Forming a source / drain region in an active region near an edge of the gate conductive layer; Selectively reducing only the width of one spacer; And And forming a silicide layer for commonly connecting the narrower spacer, the adjacent source or drain region, and the gate conductive layer. The method of claim 2, wherein only reducing the width of the one spacer is Forming an insulating film on an entire surface of the substrate on which the source / drain regions are formed; Forming an insulating film pattern for designating a portion for interconnecting the gate conductive layer and the source or drain region; And And forming a width of one spacer to have a normal thickness by forming an entire surface etching process on the entire surface of the substrate on which the pattern is formed, and forming a width of the other spacer to have a narrow thickness.