JP2676764B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, particularly an LDD (Lightly Doped D).
The present invention relates to a structure of a MOS semiconductor device having a rain structure, a mask ROM using the same, and an integrated circuit using the mask ROM.

[Conventional technology]

The structure and structure steps of a conventional MOS semiconductor device will be described with reference to the drawings.

6 and 7 show a conventional structure and connecting portion.
In the figure, 1 is a substrate of the first conductivity type, 2 is a diffusion layer of the second conductivity type, 2a is a low concentration region of the diffusion layer, 2b is a high concentration region of the diffusion layer, 3 is a gate power source (first 1 wiring layer),
Reference numeral 4 is a gate insulating film, 10 is an interlayer insulating film, 6 is a sidewall, 8 is a second wiring layer, and 9 is a connecting portion (contact portion).

As shown in FIG. 4, the LDD structure includes a low concentration region 2a and a high concentration region 2b in which the diffusion layer 2 of the second conductivity type has a low concentration.
Since the concentration of the region 2a is low, the diffusion does not spread below the channel region, that is, under the gate insulating film 4, so that the channel length can be secured. In addition, the resistance of this portion becomes higher than that of the region 2b due to the region 2a. This is suitable for miniaturization because the electric field can be alleviated, and deterioration of transistor characteristics such as threshold caused by injection and capture of carriers in the gate insulating film near the drain by the electric field, so-called hot carrier phenomenon, can be suppressed.

The manufacturing method is shown in FIGS. 8 (a) to 8 (e). FIG. 8 (a) shows the gate electrode 3 formed by the conventional method.
Is formed on the gate insulating film 4, then a low-concentration diffusion region 2a is formed as shown in FIG. 8 (b), and further interlayer insulation for forming a side wall as shown in FIG. 8 (c). Membrane 6a
Is formed, and then the sidewalls 6 are formed by anisotropic etching as shown in FIG. 8 (d), and then the high-concentration diffusion region 2b is formed as shown in FIG. 8 (e).
The above is the method of forming the LDD structure.

[Problems to be solved by the invention]

As a problem of the conventional MOS type semiconductor device as described above,
The following points are mentioned.

(1) As shown in FIG. 7, the connecting portion 9 between the two layers has conventionally formed a hole-shaped opening. Therefore, photolithography is performed so that the opening 9 and the metal of the first wiring layer 3 are not short-circuited. The combination allowance a was required. This is a bottleneck in high integration because the margin a cannot be simply reduced because it is determined by the capability of the exposure apparatus.

(2) For the same reason as in the previous section,
The length of the second wiring layer 8 cannot be reduced, and the speed cannot be increased due to the propagation delay due to this resistance.

(3) For the same reason as in the above item (1), the parasitic diffusion capacitance is not reduced due to the combination allowance a, and the speed cannot be increased.

These are particularly remarkable in a read-only memory so-called mask ROM in which data is written in a process and an integrated circuit incorporating the read-only memory, which has been a major cause of unintegration accompanying the increase in capacity.

The present invention is directed to a semiconductor device and a mask RO which solve the above problems.
It is an object of the present invention to provide an integrated circuit including M and a mask ROM.

[Means for solving the problem]

A semiconductor device of the present invention is a semiconductor substrate of a first conductivity type,
A second conductivity type diffusion layer provided on the surface of the semiconductor substrate, and polycrystalline silicon, a refractory metal, a silicide provided on the semiconductor substrate, or a combination of polycrystalline silicon and a refractory metal or a silicide. A first wiring layer made of any one of the following polycides, an insulating film provided on the first wiring layer, and sidewall insulation provided on a sidewall of the first wiring layer and the insulating film. A film, a second wiring layer that intersects with the first wiring layer and is adjacent to the sidewall insulating film and connected to the diffusion layer, and a second wiring layer that is provided at least on the insulating film, A semiconductor device having an interlayer insulating film having an opening for connecting to the diffusion layer, wherein an opening width of the opening is larger than a boundary between the diffusion layer and the sidewall insulating film. On the diffusion layer, A conductor layer made of any one of a point metal, a refractory metal silicide, and a nitride film of a refractory metal, or a combination of two or more kinds thereof is provided, and the second wiring layer is provided through the conductor layer. And is connected to the diffusion layer.

Further, the surface of the diffusion layer is larger than the width of the second wiring layer at the location where the diffusion layer and the second wiring layer are connected.

(Operation)

In the conventional method, the wiring interval of the first layer is as shown in FIG.
It becomes 1 + 2a. Here, l: size of the opening between the first-layer wiring layers a: alignment margin However, in the method of the present invention, it is not necessary to provide an alignment margin, and the minimum wiring interval which is processing-limited as shown in FIG. 2 is sufficient. .

For example, the line width and spacing of the first layer are 1.2μm and 1.2μ, respectively.
m, the alignment margin a is 1.0 μm, and l is 1.2 μm, the conventional method: l + 2a = (1.2 + 1.0 × 2) μm = 3.2 μm The method of the present invention: 1.2 μm, which is about the same as the conventional method. Less than half.

Since the semiconductor device of the present invention is configured as described above, the chip area can be reduced, and accordingly, the diffusion area of the source or drain diffusion layer is reduced, and the parasitic capacitance is reduced. Similarly, the wiring length of the second layer is shortened by this amount, the wiring resistance is reduced, the propagation delay can be reduced, and high speed and low cost can be accommodated.

〔Example〕

An example in which the embodiment of the present invention is applied to an N-channel MOSFET will be described.

FIG. 1 and FIG. 2 are explanatory views of a semiconductor device of the present invention and a connection portion thereof.

In the drawings, the same reference numerals as those in FIGS. 6 to 8 indicate the same or corresponding portions, and thus the repetitive description will be omitted. In the figure, 5 is an interlayer insulating film selectively formed on the second wiring layer 3, and 11 is a sidewall insulating film of the gate electrode 3 in the opening 9. Reference numeral 13 is a conductor layer arranged on the diffusion layer and between the first and second wiring layers.

1 In Figure 1 the P-type semiconductor substrate or N made of silicon single crystal ^- P formed -type semiconductor substrate ^- a region, 2 is N ⁺ -type low diffusion layer in the diffusion layer 2a concentrations of 2b is a high concentration diffusion layer. 3 and 7 in FIG. 2 are a first wiring layer (gate electrode), which is made of polycrystalline silicon, a refractory metal such as Mo or W, or a silicide such as molybdenum silicide, tungsten silicide or titanium silicide. 4 is a substrate 1 mainly used as a gate insulating film
An insulating film 5 made of SiO ₂ or the like formed above is an interlayer insulating film made of SiO ₂ , Si ₃ N ₄ or the like selectively provided on the first wiring 3, whereby the first and second insulating films are formed. If the wiring is separated and the opening as shown in FIG.
One wiring layer is short-circuited on the gate electrode 3. Therefore, the formation of the interlayer insulating film 5 is a point of the present invention, and this point will be described in an embodiment of a manufacturing method described later. This film 5 is made of SiO ₂ or CVD formed by thermal oxidation or CVD.
An insulating film such as Si ₃ N ₄ formed by a method is used. Reference numeral 6 is a sidewall mainly provided on both side surfaces of the first wiring layer 3 by anisotropic etching. In the gate electrode portion, a pair of semiconductor regions used as a source and a drain are further isolated from each other, and an effective channel length is provided. It is used to secure enough.

Reference numeral 10 is an interlayer insulating film between the first wiring layer and the second wiring layer, and 11 is a side wall of the gate electrode 3 in the opening for contacting the first wiring layer and the second wiring layer 8. Is a side wall insulating film formed on the gate insulating film 4 by anisotropic etching. The first side wall insulating film is an LDD structure side wall, and the second side wall insulating film is the second fall and interlayer insulating film 10. Is a sidewall insulating film formed by a combination with a sidewall insulating film formed by a mechanism similar to that of the sidewall when forming the opening (9 in FIG. 2) by anisotropic etching. The difference is explained by overetching during the opening etching. That is, if the over-etching is long, the interlayer insulating film 10 is completely etched even on the side wall of the gate electrode 3, and the side wall insulating film 11 becomes only the side wall. Conversely, if the etching amount is reduced, the second state occurs.

Further, 13 is a conductor layer formed between the first wiring and the second wiring, which is made of a combination of one or two of a refractory metal or its silicide or its nitride. When the second wiring layer is a metal such as AL that easily reacts with Si at low temperature, the metal such as AL is the second layer near the boundary between the sidewall insulating film 11 and the Si surface (the arrow in the figure). The heat treatment of the wiring layer causes the diffusion layer 2a or the boundary between 2a and 2b to pass through. Therefore, in order to prevent this, the conductor layer 13
To form This conductor layer is preferably made of a refractory metal such as Ti, W, or Mo, or a silicide thereof, or a nitride thereof, and may be a single layer or a combination of two or more thereof. This conductor layer may be formed over the entire second wiring layer,
It may be formed only on the Si surface of the connection portion between the first and second wiring layers. On the other hand, this can also reduce the connection resistance of the connection portion of the first and second wiring layers.

Further, as the conductor layer 13, if one having a large selection ratio at the time of etching with the second wiring layer is used (for example, the second wiring layer is Poly-Si and the conductor layer is MoSi, etc.), FIG. When the wiring width of the second wiring layer 8 is smaller than that of the Si surface in the opening 9 as shown in), when the second wiring layer is etched, the Si surface is etched to form a groove. As a result, there will be no problems such as disconnection of the AL.

(Note that 14 is an element isolation insulating film.) The semiconductor device of the present invention is as shown in FIG. 1. (1) The opening 9 is a diffusion layer region on the substrate surface as shown in FIG. Is formed to be larger than the boundary between the sidewall and the sidewall insulating film 11, so that there is no alignment margin in the design rule.

However, on the pattern, the alignment margin a can be eliminated, but there is still a misalignment between the first wiring layer 7 and the opening 9 of the photolithography, so that the gap between the first and second wiring layers is reduced. The contact area in the opening 9 becomes small, and the contact resistance increases.
Therefore, the misalignment can be avoided by reaching the upper part of the first wiring layer 7 of the opening 9.

(2) If the structure as described in (1) above is introduced in a conventional process, the first and second wiring layers will be short-circuited.

Therefore, the insulating film 5 is selectively formed only on the first wiring layer for isolation.

(3) On the side surface of the first wiring layer, it is separated from the second wiring layer in a self-aligned manner by the side wall or sidewall insulating film 11.

(4) Further, at the connecting portion between the second wiring layer and the diffusion layer, a conductor layer made of a combination of one or two layers of refractory metal, silicide thereof or nitride thereof is provided between the two.

Etc. are different from the conventional device.

Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 (a) to 3 (l).

 In the figure, 12 is a photoresist pattern.

The method of manufacturing a semiconductor device according to the present invention includes the following steps: (1) First, as shown in FIG. 3A, after forming a gate insulating film 4 on the surface of a p-type semiconductor substrate 1, a polycrystalline silicon layer or a high melting point A gate electrode layer (first wiring layer 7) of a metal layer or a polycide layer composed of a combination of the two is formed.

(2) Next, as shown in FIG. 3B, an insulating film 5 is formed on the gate electrode layer 7 by CVD. (In this case, or by heat treatment for oxidizing the gate electrode 7 layer, SiO ₂ or Si ₃ N ₄ is used as a film.) (3) As shown in FIG. A resist pattern 12 is formed.

(4) As shown in FIG. 3 (d), reactive etching (RI
E), the insulating film 5 is removed by etching. Next, as shown in FIG. 3 (e), a gate electrode 3 is formed by the same reactive etching, and a photoresist pattern 12 is formed.
Is removed.

(5) As shown in FIG. 3 (f), by using the gate electrode 3 as a mask and implanting ³¹ P ⁺ or ⁷⁵ As ⁺ ions into the substrate 1, n
^-A layer (a low concentration diffusion layer 2a) is formed.

(6) As shown in FIG. 3 (g), the interlayer insulating film 6 is formed by CVD.
a is formed on the entire surface of the gate electrode 3. This insulating film is made of SiO ₂
Alternatively, Si ₃ N ₄ is used.

(7) As shown in FIG. 3H, the entire surface is removed by reactive etching to form sidewalls 6 on the sidewalls of the gate electrode 3.

(8) Next, as shown in FIG. 3 (i), an n ⁺ layer (dense diffusion layer 2b) is formed on the substrate 1 by ion implantation of ³¹ P ⁺ or ⁷⁵ As ^+.
To form

(9) As shown in FIG. 3 (j), the interlayer insulating film 1 is formed by CVD.
Form a 0. This film uses SiO ₂ or Si ₃ N ₄ .

(10) As shown in FIG. 3 (k), a part of the interlayer insulating film 5 and a part of the side wall 6 below a predetermined part of the interlayer insulating film 10 are removed by etching, and the side wall 11 and the opening 9 of the connection part are removed. To form

At this time, by optimizing the interlayer insulating film 5, the over-etching layer at the time of forming the sidewall 6, the interlayer insulating film 10, the opening 9 of the connecting portion and the etching conditions, the first wiring layer 7 and the second wiring layer are formed. Insulating film 5 or 11 between layers 8 is the minimum of the film
By adjusting it to 500Å or more, leakage between the two is prevented and pressure resistance is secured.

(11) Finally, as shown in FIG. 3 (l), one or a combination of two or more conductor layers made of refractory metals such as Mo, W, and Ti, their silicides, or their nitrides is used. Sputtering multiple conductive layers, or
It is formed by the CVD method, and the second wiring layer is further formed thereon. At this time, when this conductor layer is formed on the entire lower surface of the second wiring layer, the formation of the conductor layer and the formation of the second wiring layer are continuously performed, and after the resist pattern is formed, etching of the second wiring layer is performed. Etching the conductor layer at once,
Alternatively, the structure can be formed by etching in two steps. At the same time, the resistance to electromigration can be improved.

On the other hand, when forming a conductor layer between the second wiring layer and the Si surface of the diffusion layer or only in the vicinity thereof, the conductor layer is formed on the entire surface in the state of FIG. Is also a method of forming a silicide film only on the Si surface by silicidation, and then by selective etching, which can be formed by using Ti or the like. Similarly, in the latter case, after forming a resist pattern only on a necessary portion after forming a conductor layer and etching that portion, the second layer wiring 8 is formed by a conventional method, whereby the structure of the present invention can be realized. A MASKROM using this and an integrated circuit incorporating this MASKROM have been realized.

In the embodiment of the present invention, the example of the N-channel transistor formed in the P ⁻ region on the P type substrate or the N substrate is described, but it goes without saying that on the N ⁻ region formed on the N type substrate or the P substrate. It goes without saying that the present invention can also be applied to the P-channel transistor formed in the above.

〔The invention's effect〕

By using the structure of the semiconductor device of the present invention, (1) the alignment margin can be eliminated and the interval between the first wirings is reduced, so that high density can be realized.

(2) Since the wiring length of the second layer can be reduced, the wiring resistance can be reduced and the wiring delay can be reduced.

(3) Since the area of the diffusion layer can be reduced, the capacitance of the diffusion layer can be reduced, and the parasitic capacitance of the second-layer wiring can be reduced, thereby realizing high-speed operation.

(4) The overall chip area is reduced, the number of effective chips in the same wafer is increased, and the cost can be reduced.

(5) On the diffusion layer, a conductor layer formed of any one of refractory metal, refractory metal silicide, and nitride film of refractory metal, or a combination of two or more thereof is provided, Since the second wiring layer is connected to the diffusion layer via the conductor layer, the connection resistance of the contact portion can be reduced.

As described above, particularly high speed and low cost can be achieved without metal sticking out and processing defects, which is a great effect.

With regard to the chip area, using the example described in [Operation], in the 1M bit MASK ROM, the one-sided direction could be reduced to 2.0μ × 1000 = 2000μ in the CELL part.

In addition, this effect also made it possible to reduce the area of the ROM part for an integrated circuit with a built-in ROM.

[Brief description of the drawings]

1 and 2 are explanatory views of a semiconductor device of the present invention and its connection portion, and FIGS. 3 (a) to (l) are explanatory views of an embodiment of the present invention, FIGS. 4 and 5 ( 8A and 8B are explanatory views of the necessity of the structure of the present invention, FIGS. 6 and 7 are explanatory views of a structure and a connecting portion of a conventional semiconductor device, and FIG. 8A.
(E) is explanatory drawing of LDD structure. 1 ... Si substrate 2 ... diffusion layer 2a ... low concentration diffusion layer 2b ... high concentration diffusion layer 3 ... first wiring layer gate electrode part 4 ... gate insulating film 5 ... first Insulating film formed only on the wiring layer 6 ... Sidewall 6a ... Insulating film for forming the sidewall 7 ... First wiring layer 8 ... Second wiring layer 9 ... Connection portion 10 ... ... Interlayer insulating film between first and second wirings 11 ... Sidewall insulating film 12 ... Photoresist 13 ... Conductor layer 14 ... Element isolation insulating film The same reference numerals in the drawings indicate the same or corresponding portions.

Claims (2)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a diffusion layer of a second conductivity type provided on the surface of the semiconductor substrate, polycrystalline silicon, a refractory metal, a silicide provided on the semiconductor substrate, A first wiring layer composed of either polycide made of a combination of polycrystalline silicon and a refractory metal or silicide; an insulating film provided on the first wiring layer; and a first wiring layer A side wall insulating film provided on a side wall of the insulating film and a second wiring layer that intersects the first wiring layer and is adjacent to the side wall insulating film and connected to the diffusion layer; A semiconductor device comprising: an interlayer insulating film provided on a film, the interlayer insulating film having an opening for connecting the second wiring layer and the diffusion layer, wherein the opening width of the opening is the diffusion layer. Layer and the sidewall insulation film. A conductive layer composed of any one of refractory metal, refractory metal silicide, and refractory metal nitride film, or a combination of two or more thereof is disposed on the diffusion layer. The semiconductor device is provided, and the second wiring layer is connected to the diffusion layer via the conductor layer. 2. The surface of the diffusion layer is larger than the width of the second wiring layer at a portion where the diffusion layer and the second wiring layer are connected to each other. Semiconductor device.